maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/X86/pr26870.ll

38 lines
1.4 KiB
LLVM
Raw Normal View History

[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
; RUN: llc < %s -mtriple=i686-pc-windows-msvc18.0.0 -mcpu=pentium4
define x86_thiscallcc i32* @fn4(i32* %this, i8* dereferenceable(1) %p1) {
entry:
[CodeGen] Print register names in lowercase in both MIR and debug output As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
2017-11-29 01:15:09 +08:00
%dl = getelementptr inbounds i32, i32* %this, i32 0
%call.i = tail call x86_thiscallcc i64 @fn1(i32* %dl)
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
%getTypeAllocSize___trans_tmp_2.i = getelementptr inbounds i32, i32* %this, i32 0
%0 = load i32, i32* %getTypeAllocSize___trans_tmp_2.i, align 4
[CodeGen] Print register names in lowercase in both MIR and debug output As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
2017-11-29 01:15:09 +08:00
%call.i8 = tail call x86_thiscallcc i64 @fn1(i32* %dl)
[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG Generalise the existing SIGN_EXTEND to SIGN_EXTEND_VECTOR_INREG combine to support zero extension as well and get rid of a lot of unnecessary ANY_EXTEND + mask patterns. Reapplied with a fix for PR26870 (avoid premature use of TargetConstant in ZERO_EXTEND_VECTOR_INREG expansion). Differential Revision: http://reviews.llvm.org/D17691 llvm-svn: 263159
2016-03-11 04:40:26 +08:00
%1 = insertelement <2 x i64> undef, i64 %call.i, i32 0
%2 = insertelement <2 x i64> %1, i64 %call.i8, i32 1
%3 = add nsw <2 x i64> %2, <i64 7, i64 7>
%4 = sdiv <2 x i64> %3, <i64 8, i64 8>
%5 = add nsw <2 x i64> %4, <i64 1, i64 1>
%6 = load i32, i32* %getTypeAllocSize___trans_tmp_2.i, align 4
%7 = insertelement <2 x i32> undef, i32 %0, i32 0
%8 = insertelement <2 x i32> %7, i32 %6, i32 1
%9 = zext <2 x i32> %8 to <2 x i64>
%10 = srem <2 x i64> %5, %9
%11 = sub <2 x i64> %5, %10
%12 = trunc <2 x i64> %11 to <2 x i32>
%13 = extractelement <2 x i32> %12, i32 0
%14 = extractelement <2 x i32> %12, i32 1
%cmp = icmp eq i32 %13, %14
br i1 %cmp, label %if.then, label %cleanup
if.then:
%call4 = tail call x86_thiscallcc i32* @fn3(i8* nonnull %p1)
br label %cleanup
cleanup:
%retval.0 = phi i32* [ %call4, %if.then ], [ undef, %entry ]
ret i32* %retval.0
}
declare x86_thiscallcc i32* @fn3(i8*)
declare x86_thiscallcc i64 @fn1(i32*)