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llvm-project/llvm/test/CodeGen/PowerPC/testComparesllgeus.ll

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[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314060
2017-09-23 17:50:12 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 21:39:10 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314060
2017-09-23 17:50:12 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 21:39:10 +08:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314060
2017-09-23 17:50:12 +08:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i16 0, align 2
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: test_llgeus:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori r3, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i64
ret i64 %conv3
; CHECK-LABEL: @test_llgeus_sext
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeus_z
; CHECK: li r3, 1
; CHECK-NEXT: blr
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeus_sext_z(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
; CHECK-LABEL: @test_llgeus_sext_z
; CHECK: li r3, -1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK_LABEL: test_llgeus_store:
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
store i16 %conv3, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_sext_store
; CHECK: sub [[REG1:r[0-9]+]], r3, r4
; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
; CHECK: sth [[REG3]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = zext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_z_store
; CHECK: li [[REG1:r[0-9]+]], 1
; CHECK: sth [[REG1]]
; CHECK: blr
}
; Function Attrs: norecurse nounwind
define void @test_llgeus_sext_z_store(i16 zeroext %a) {
entry:
%cmp = icmp uge i16 %a, 0
%conv1 = sext i1 %cmp to i16
store i16 %conv1, i16* @glob
ret void
; CHECK-LABEL: @test_llgeus_sext_z_store
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 llvm-svn: 320473
2017-12-12 20:09:34 +08:00
; CHECK: li [[REG1:r[0-9]+]], -1
; CHECK: sth [[REG1]]
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETULE/SETUGE As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential revision. llvm-svn: 314060
2017-09-23 17:50:12 +08:00
; CHECK: blr
}