2016-09-01 23:03:13 +08:00
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//=- MipsScheduleGeneric.td - Generic Scheduling Definitions -*- tablegen -*-=//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2016-09-01 23:03:13 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the interAptiv processor in a manner of speaking. It
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// describes a hypothetical version of the in-order MIPS32R2 interAptiv with all
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// branches of the MIPS ISAs, ASEs and ISA variants. The itinerary lists are
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// broken down into per ISA lists, so that this file can be used to rapidly
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// develop new schedule models.
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//
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//===----------------------------------------------------------------------===//
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def MipsGenericModel : SchedMachineModel {
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int IssueWidth = 1;
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int MicroOpBufferSize = 0;
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// These figures assume an L1 hit.
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int LoadLatency = 2;
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int MispredictPenalty = 4;
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int HighLatency = 37;
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list<Predicate> UnsupportedFeatures = [];
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2019-07-03 20:28:05 +08:00
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let CompleteModel = 1;
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2016-09-01 23:03:13 +08:00
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let PostRAScheduler = 1;
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2018-03-19 03:56:15 +08:00
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// FIXME: Remove when all errors have been fixed.
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2019-07-03 20:28:05 +08:00
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let FullInstRWOverlapCheck = 1;
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2016-09-01 23:03:13 +08:00
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}
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let SchedModel = MipsGenericModel in {
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// ALU Pipeline
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// ============
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def GenericALU : ProcResource<1> { let BufferSize = 1; }
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def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
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def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
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2019-07-03 18:32:54 +08:00
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// add, addi, addiu, addu, and, andi, clo, clz, ext, ins, lui, nor, or, ori,
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// rotr, rotrv, seb, seh, sll, sllv, slt, slti, sltiu, sltu, sra, srav, srl,
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// srlv, ssnop, sub, subu, wsbh, xor, xori
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def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
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CLO, CLZ, EXT, INS, LEA_ADDiu, LUi, NOP,
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NOR, OR, ORi, ROTR, ROTRV, SEB, SEH, SLL,
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SLLV, SLT, SLTi, SLTiu, SLTu, SRA, SRAV, SRL,
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SRLV, SSNOP, SUB, SUBu, WSBH, XOR, XORi)>;
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2016-09-01 23:03:13 +08:00
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def : InstRW<[GenericWriteALU], (instrs COPY)>;
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2019-07-03 18:32:54 +08:00
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// MIPSR6
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// ======
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// addiupc, align, aluipc, aui, auipc, bitswap, clo, clz, lsa, seleqz, selnez
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def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
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AUIPC, BITSWAP, CLO_R6, CLZ_R6, LSA_R6,
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SELEQZ, SELNEZ)>;
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// MIPS16e
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// =======
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def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
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AddiuRxRxImmX16, AddiuRxRyOffMemX16,
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AddiuRxPcImmX16, AddiuSpImm16, AddiuSpImmX16,
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AdduRxRyRz16, AndRxRxRy16, CmpRxRy16,
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CmpiRxImm16, CmpiRxImmX16, LiRxImm16,
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LiRxImmX16, LiRxImmAlignX16, Move32R16,
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MoveR3216, Mfhi16, Mflo16, NegRxRy16,
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NotRxRy16, OrRxRxRy16, SebRx16, SehRx16,
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SllX16, SllvRxRy16, SltiRxImm16,
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SltiRxImmX16, SltiCCRxImmX16,
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SltiuRxImm16, SltiuRxImmX16, SltiuCCRxImmX16,
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SltRxRy16, SltCCRxRy16, SltuRxRy16,
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SltuRxRyRz16, SltuCCRxRy16, SravRxRy16,
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SraX16, SrlvRxRy16, SrlX16, SubuRxRyRz16,
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XorRxRxRy16)>;
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2019-07-03 18:33:09 +08:00
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def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
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GotPrologue16, CONSTPOOL_ENTRY)>;
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2019-07-03 18:32:54 +08:00
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// microMIPS
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// =========
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def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
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ADDIUS5_MM, ADDIUSP_MM, ADDU16_MM, ADD_MM,
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ADDi_MM, ADDiu_MM, ADDu_MM, AND16_MM,
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ANDI16_MM, AND_MM, ANDi_MM, CLO_MM, CLZ_MM,
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EXT_MM, INS_MM, LEA_ADDiu_MM, LI16_MM,
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LUi_MM, MOVE16_MM, MOVEP_MM, NOR_MM,
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NOT16_MM, OR16_MM, OR_MM, ORi_MM, ROTRV_MM,
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ROTR_MM, SEB_MM, SEH_MM, SLL16_MM, SLLV_MM,
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SLL_MM, SLT_MM, SLTi_MM, SLTiu_MM, SLTu_MM,
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SRAV_MM, SRA_MM, SRL16_MM, SRLV_MM, SRL_MM,
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SSNOP_MM, SUBU16_MM, SUB_MM, SUBu_MM,
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WSBH_MM, XOR16_MM, XOR_MM, XORi_MM)>;
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// microMIPS32r6
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// =============
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def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MMR6, ADDIU_MMR6, ADDU16_MMR6,
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ADDU_MMR6, ADD_MMR6, ALIGN_MMR6, ALUIPC_MMR6,
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AND16_MMR6, ANDI16_MMR6, ANDI_MMR6, AND_MMR6,
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AUIPC_MMR6, AUI_MMR6, BITSWAP_MMR6, CLO_MMR6,
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CLZ_MMR6, EXT_MMR6, INS_MMR6, LI16_MMR6,
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LSA_MMR6, LUI_MMR6, MOVE16_MMR6, NOR_MMR6,
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NOT16_MMR6, OR16_MMR6, ORI_MMR6, OR_MMR6,
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SELEQZ_MMR6, SELNEZ_MMR6, SLL16_MMR6,
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SLL_MMR6, SRL16_MMR6, SSNOP_MMR6, SUBU16_MMR6,
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SUBU_MMR6, SUB_MMR6, WSBH_MMR6, XOR16_MMR6,
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XORI_MMR6, XOR_MMR6)>;
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// MIPS64
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// ======
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def : InstRW<[GenericWriteALU], (instrs AND64, ANDi64, DEXT64_32, DSLL64_32,
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ORi64, SEB64, SEH64, SLL64_32, SLL64_64,
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SLT64, SLTi64, SLTiu64, SLTu64, XOR64,
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XORi64)>;
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def : InstRW<[GenericWriteALU], (instrs DADD, DADDi, DADDiu, DADDu, DCLO,
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DCLZ, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU,
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DROTR, DROTR32, DROTRV, DSBH, DSHD, DSLL,
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DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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DSRL32, DSRLV, DSUB, DSUBu, LEA_ADDiu64,
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LUi64, NOR64, OR64)>;
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// MIPS64R6
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// ========
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def : InstRW<[GenericWriteALU], (instrs DALIGN, DAHI, DATI, DAUI, DCLO_R6,
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DCLZ_R6, DBITSWAP, DLSA, DLSA_R6, SELEQZ64,
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SELNEZ64)>;
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2016-09-01 23:03:13 +08:00
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def GenericMDU : ProcResource<1> { let BufferSize = 1; }
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def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; }
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def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; }
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def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>;
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def GenericWriteALULong : SchedWriteRes<[GenericIssueALU]> { let Latency = 5; }
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def GenericWriteMove : SchedWriteRes<[GenericIssueALU]> { let Latency = 2; }
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2019-07-03 18:32:54 +08:00
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def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; }
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def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 20:27:51 +08:00
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def : InstRW<[GenericWriteHILO], (instrs PseudoMADD_MM, PseudoMADDU_MM,
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PseudoMSUB_MM, PseudoMSUBU_MM,
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PseudoMULT_MM, PseudoMULTu_MM)>;
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteHILO], (instrs PseudoMADD, PseudoMADDU, PseudoMSUB,
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PseudoMSUBU, PseudoMULT, PseudoMULTu)>;
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2016-09-01 23:03:13 +08:00
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def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> {
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let Latency = 5;
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}
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def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
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// Estimated worst case
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let Latency = 33;
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2018-05-02 21:37:28 +08:00
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let ResourceCycles = [33];
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2016-09-01 23:03:13 +08:00
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}
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def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
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// Estimated worst case
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let Latency = 31;
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2018-05-02 21:37:28 +08:00
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let ResourceCycles = [31];
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2016-09-01 23:03:13 +08:00
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}
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2019-07-03 18:32:54 +08:00
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// mul
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def : InstRW<[GenericWriteMDUtoGPR], (instrs MUL)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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// mult, multu
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def : InstRW<[GenericWriteMul], (instrs MULT, MULTu)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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// div, sdiv
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def : InstRW<[GenericWriteDIV], (instrs PseudoSDIV, SDIV)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteDIVU], (instrs PseudoUDIV, UDIV)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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// mfhi, mflo, movn, mthi, mtlo, rdwhr
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def : InstRW<[GenericWriteALULong], (instrs MFHI, MFLO, PseudoMFHI,
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PseudoMFLO)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 20:27:51 +08:00
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def : InstRW<[GenericWriteALULong], (instrs PseudoMFHI_MM, PseudoMFLO_MM)>;
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteMove], (instrs MTHI, MTLO, RDHWR, PseudoMTLOHI)>;
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2019-07-03 20:27:51 +08:00
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def : InstRW<[GenericWriteMove], (instrs PseudoMTLOHI_MM)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteALU], (instrs MOVN_I_I, MOVZ_I_I)>;
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// MIPSR6
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// ======
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// muh, muhu, mulu, mul
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def : InstRW<[GenericWriteMul], (instrs MUH, MUHU, MULU, MUL_R6)>;
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// divu, udiv
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def : InstRW<[GenericWriteDIV], (instrs MOD, MODU, DIV, DIVU)>;
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2016-09-01 23:03:13 +08:00
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// MIPS16e
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// =======
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteHILO], (instrs MultRxRy16, MultuRxRy16,
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MultRxRyRz16, MultuRxRyRz16)>;
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def : InstRW<[GenericWriteDIV], (instrs DivRxRy16)>;
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def : InstRW<[GenericWriteDIVU], (instrs DivuRxRy16)>;
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2016-09-01 23:03:13 +08:00
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// microMIPS
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// =========
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteMul], (instrs MULT_MM, MULTu_MM, MADD_MM, MADDU_MM,
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MSUB_MM, MSUBU_MM)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteALULong], (instrs MUL_MM)>;
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def : InstRW<[GenericWriteDIV], (instrs SDIV_MM, SDIV_MM_Pseudo)>;
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def : InstRW<[GenericWriteDIVU], (instrs UDIV_MM, UDIV_MM_Pseudo)>;
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def : InstRW<[GenericWriteMove], (instrs MFHI16_MM, MFLO16_MM, MOVF_I_MM,
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MOVT_I_MM, MFHI_MM, MFLO_MM, MTHI_MM,
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MTLO_MM)>;
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def : InstRW<[GenericWriteMove], (instrs RDHWR_MM)>;
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// microMIPS32r6
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// =============
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def : InstRW<[GenericWriteMul], (instrs MUHU_MMR6, MUH_MMR6, MULU_MMR6,
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MUL_MMR6)>;
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def : InstRW<[GenericWriteDIV], (instrs MODU_MMR6, MOD_MMR6, DIVU_MMR6,
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DIV_MMR6)>;
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def : InstRW<[GenericWriteMove], (instrs RDHWR_MMR6)>;
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// MIPS64
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2016-09-01 23:03:13 +08:00
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// ======
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteHILO], (instrs DMULU, DMULT, DMULTu, PseudoDMULT,
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PseudoDMULTu)>;
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def : InstRW<[GenericWriteDIV], (instrs DSDIV, PseudoDSDIV)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteDIVU], (instrs DUDIV, PseudoDUDIV)>;
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def : InstRW<[GenericWriteALULong], (instrs MFHI64, MFLO64, PseudoMFHI64,
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PseudoMFLO64, PseudoMTLOHI64)>;
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def : InstRW<[GenericWriteMove], (instrs MTHI64, MTLO64, RDHWR64)>;
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// mov[zn]
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def : InstRW<[GenericWriteALU], (instrs MOVN_I_I64, MOVN_I64_I, MOVN_I64_I64,
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MOVZ_I_I64, MOVZ_I64_I, MOVZ_I64_I64)>;
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2016-09-01 23:03:13 +08:00
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// MIPS64R6
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// ========
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUH, DMUHU, DMUL_R6)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteDIV], (instrs DDIV, DMOD)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteDIVU], (instrs DDIVU, DMODU)>;
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2016-09-01 23:03:13 +08:00
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// CTISTD Pipeline
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// ---------------
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def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; }
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def GenericLDST : ProcResource<1> { let BufferSize = 1; }
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def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; }
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def GenericWriteJump : SchedWriteRes<[GenericIssueCTISTD]>;
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def GenericWriteJumpAndLink : SchedWriteRes<[GenericIssueCTISTD]> {
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let Latency = 2;
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}
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// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx,
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// jalr, jr.hb, jr, jalr.hb, jarlc, jialc
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJump], (instrs B, BAL, BAL_BR, BEQ, BNE, BGTZ, BGEZ,
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BLEZ, BLTZ, BLTZAL, J, JALX, JR, JR_HB, ERET,
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ERet, ERETNC, DERET)>;
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def : InstRW<[GenericWriteJump], (instrs BEQL, BNEL, BGEZL, BGTZL, BLEZL,
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BLTZL)>;
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def : InstRW<[GenericWriteJump], (instrs TAILCALL, TAILCALLREG,
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TAILCALLREGHB, PseudoIndirectBranch,
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PseudoIndirectHazardBranch, PseudoReturn,
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RetRA)>;
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def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZAL, JAL, JALR, JALR_HB,
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JALRHBPseudo, JALRPseudo)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALL, BLTZALL)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteTrap], (instrs BREAK, SYSCALL, TEQ, TEQI,
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TGE, TGEI, TGEIU, TGEU, TNE,
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TNEI, TLT, TLTI, TLTU, TTLTIU,
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TRAP, SDBBP)>;
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2016-09-01 23:03:13 +08:00
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// MIPSR6
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// ======
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJumpAndLink], (instrs BALC, BEQZALC, BGEZALC,
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BGTZALC, BLEZALC, BLTZALC,
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BNEZALC,
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JIALC)>;
|
2016-09-01 23:03:13 +08:00
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|
2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJump], (instrs BC, BC2EQZ, BC2NEZ, BEQC, BEQZC, BGEC,
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BGEUC, BGEZC, BGTZC, BLEZC, BLTC, BLTUC,
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BLTZC, BNEC, BNEZC, BNVC, BOVC, JIC, JR_HB_R6,
|
2019-07-03 18:33:16 +08:00
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SIGRIE, PseudoIndirectBranchR6,
|
2019-07-03 18:32:54 +08:00
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|
PseudoIndrectHazardBranchR6)>;
|
2016-09-01 23:03:13 +08:00
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|
2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJump], (instrs TAILCALLR6REG, TAILCALLHBR6REG)>;
|
2016-09-01 23:03:13 +08:00
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|
2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteTrap], (instrs SDBBP_R6)>;
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// MIPS16e
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// =======
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def : InstRW<[GenericWriteJump], (instrs Bimm16, BimmX16, BeqzRxImm16,
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BeqzRxImmX16, BnezRxImm16, BnezRxImmX16,
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Bteqz16, BteqzX16, BteqzT8CmpX16,
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BteqzT8CmpiX16, BteqzT8SltX16,
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BteqzT8SltuX16, BteqzT8SltiX16,
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BteqzT8SltiuX16, Btnez16, BtnezX16,
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BtnezT8CmpX16, BtnezT8CmpiX16,
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BtnezT8SltX16, BtnezT8SltuX16,
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BtnezT8SltiX16, BtnezT8SltiuX16, JrRa16,
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JrcRa16, JrcRx16, RetRA16)>;
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|
def : InstRW<[GenericWriteJumpAndLink], (instrs Jal16, JalB16, JumpLinkReg16)>;
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def : InstRW<[GenericWriteTrap], (instrs Break16)>;
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|
def : InstRW<[GenericWriteALULong], (instrs SelBeqZ, SelTBteqZCmp,
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|
SelTBteqZCmpi, SelTBteqZSlt,
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|
SelTBteqZSlti, SelTBteqZSltu,
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SelTBteqZSltiu, SelBneZ, SelTBtneZCmp,
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SelTBtneZCmpi, SelTBtneZSlt,
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SelTBtneZSlti, SelTBtneZSltu,
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|
SelTBtneZSltiu)>;
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|
// microMIPS
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|
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|
|
// =========
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|
2019-07-03 20:27:51 +08:00
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|
def : InstRW<[GenericWriteJump], (instrs B16_MM, BAL_BR_MM, BC1F_MM, BC1T_MM,
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BEQZ16_MM, BEQZC_MM, BEQ_MM, BGEZ_MM,
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BGTZ_MM, BLEZ_MM, BLTZ_MM, BNEZ16_MM,
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BNEZC_MM, BNE_MM, B_MM, DERET_MM, ERET_MM,
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JR16_MM, JR_MM, J_MM, B_MM_Pseudo)>;
|
2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteJumpAndLink], (instrs BGEZALS_MM, BGEZAL_MM,
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|
BLTZALS_MM, BLTZAL_MM, JALR16_MM,
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JALRS16_MM, JALRS_MM, JALR_MM,
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JALS_MM, JALX_MM, JAL_MM)>;
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|
def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MM, TAILCALL_MM,
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|
PseudoIndirectBranch_MM)>;
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|
def : InstRW<[GenericWriteTrap], (instrs BREAK16_MM, BREAK_MM, SDBBP16_MM,
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|
SDBBP_MM, SYSCALL_MM, TEQI_MM, TEQ_MM,
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|
|
TGEIU_MM, TGEI_MM, TGEU_MM, TGE_MM, TLTIU_MM,
|
2019-07-03 20:27:51 +08:00
|
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|
TLTI_MM, TLTU_MM, TLT_MM, TNEI_MM, TNE_MM,
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|
|
|
TRAP_MM)>;
|
2019-07-03 18:32:54 +08:00
|
|
|
|
|
|
|
|
// microMIPS32r6
|
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|
|
|
// =============
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteJump], (instrs BC16_MMR6, BC1EQZC_MMR6, BC1NEZC_MMR6,
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BC2EQZC_MMR6, BC2NEZC_MMR6, BC_MMR6,
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|
BEQC_MMR6, BEQZC16_MMR6, BEQZC_MMR6,
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|
|
BGEC_MMR6, BGEUC_MMR6, BGEZC_MMR6,
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|
BGTZC_MMR6, BLEZC_MMR6, BLTC_MMR6,
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|
|
BLTUC_MMR6, BLTZC_MMR6, BNEC_MMR6,
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|
|
BNEZC16_MMR6, BNEZC_MMR6, BNVC_MMR6,
|
2019-07-12 12:58:45 +08:00
|
|
|
BOVC_MMR6, DERET_MMR6, ERETNC_MMR6, JAL_MMR6,
|
2019-07-03 18:32:54 +08:00
|
|
|
ERET_MMR6, JIC_MMR6, JRADDIUSP, JRC16_MM,
|
2019-07-03 18:33:16 +08:00
|
|
|
JRC16_MMR6, JRCADDIUSP_MMR6, SIGRIE_MMR6,
|
2019-07-03 20:27:51 +08:00
|
|
|
B_MMR6_Pseudo, PseudoIndirectBranch_MMR6)>;
|
2019-07-03 18:32:54 +08:00
|
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|
|
def : InstRW<[GenericWriteJumpAndLink], (instrs BALC_MMR6, BEQZALC_MMR6,
|
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|
BGEZALC_MMR6, BGTZALC_MMR6,
|
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|
|
BLEZALC_MMR6, BLTZALC_MMR6,
|
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|
|
BNEZALC_MMR6, JALRC16_MMR6,
|
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|
|
JALRC_HB_MMR6, JALRC_MMR6,
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|
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|
|
JIALC_MMR6)>;
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|
|
def : InstRW<[GenericWriteJump], (instrs TAILCALLREG_MMR6, TAILCALL_MMR6)>;
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|
def : InstRW<[GenericWriteTrap], (instrs BREAK16_MMR6, BREAK_MMR6, SDBBP_MMR6,
|
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|
SDBBP16_MMR6)>;
|
|
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|
|
// MIPS64
|
|
|
|
|
// ======
|
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|
|
def : InstRW<[GenericWriteJump], (instrs BEQ64, BGEZ64, BGTZ64, BLEZ64,
|
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BLTZ64, BNE64, JR64)>;
|
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|
|
def : InstRW<[GenericWriteJumpAndLink], (instrs JALR64, JALR64Pseudo,
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|
JALRHB64Pseudo, JALR_HB64)>;
|
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|
|
def : InstRW<[GenericWriteJump], (instrs JR_HB64, TAILCALLREG64,
|
|
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|
|
TAILCALLREGHB64, PseudoReturn64)>;
|
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|
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|
|
|
// MIPS64R6
|
|
|
|
|
// ========
|
|
|
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|
|
|
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|
|
def : InstRW<[GenericWriteJump], (instrs BEQC64, BEQZC64, BGEC64, BGEUC64,
|
|
|
|
|
BGEZC64, BGTZC64, BLEZC64, BLTC64, BLTUC64,
|
|
|
|
|
BLTZC64, BNEC64, BNEZC64, JIC64,
|
|
|
|
|
PseudoIndirectBranch64,
|
|
|
|
|
PseudoIndirectHazardBranch64)>;
|
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|
|
def : InstRW<[GenericWriteJumpAndLink], (instrs JIALC64)>;
|
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|
|
def : InstRW<[GenericWriteJump], (instrs JR_HB64_R6, TAILCALL64R6REG,
|
|
|
|
|
TAILCALLHB64R6REG, PseudoIndirectBranch64R6,
|
|
|
|
|
PseudoIndrectHazardBranch64R6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// COP0 Pipeline
|
|
|
|
|
// =============
|
|
|
|
|
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|
|
def GenericCOP0 : ProcResource<1> { let BufferSize = 1; }
|
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|
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|
|
def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; }
|
|
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|
|
def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; }
|
|
|
|
|
def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; }
|
|
|
|
|
def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; }
|
2017-07-13 00:23:57 +08:00
|
|
|
def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>;
|
|
|
|
|
def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> {
|
|
|
|
|
let Latency = 5;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP, TLBR, TLBWI, TLBWR)>;
|
|
|
|
|
def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV, TLBINVF)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericReadCOP0], (instrs MFC0)>;
|
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|
|
|
def : InstRW<[GenericWriteCOP0], (instrs MTC0)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs EVP, DVP)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs DI, EI)>;
|
|
|
|
|
|
|
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|
|
def : InstRW<[GenericWriteCOP0], (instrs EHB, PAUSE, WAIT)>;
|
|
|
|
|
|
|
|
|
|
// microMIPS
|
|
|
|
|
// =========
|
|
|
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|
|
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|
|
def : InstRW<[GenericWriteCOP0TLB], (instrs TLBP_MM, TLBR_MM, TLBWI_MM,
|
|
|
|
|
TLBWR_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs DI_MM, EI_MM)>;
|
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|
|
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|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs EHB_MM, PAUSE_MM, WAIT_MM)>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// microMIPS32R6
|
|
|
|
|
// =============
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs RDPGPR_MMR6, WRPGPR_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0TLB], (instrs TLBINV_MMR6, TLBINVF_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericReadCOP0], (instrs MFHC0_MMR6, MFC0_MMR6, MFHC2_MMR6,
|
|
|
|
|
MFC2_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs MTHC0_MMR6, MTC0_MMR6, MTHC2_MMR6,
|
|
|
|
|
MTC2_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs EVP_MMR6, DVP_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs DI_MMR6, EI_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs EHB_MMR6, PAUSE_MMR6, WAIT_MMR6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// MIPS64
|
|
|
|
|
// ======
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericReadCOP0], (instrs DMFC0)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCOP0], (instrs DMTC0)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
def GenericCOP2 : ProcResource<1> { let BufferSize = 1; }
|
|
|
|
|
def GenericWriteCOPOther : SchedWriteRes<[GenericCOP2]>;
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCOPOther], (instrs MFC2, MTC2)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCOPOther], (instrs DMFC2, DMTC2)>;
|
|
|
|
|
|
|
|
|
|
// microMIPS32R6
|
|
|
|
|
// =============
|
|
|
|
|
|
|
|
|
|
// The latency and repeat rate of these instructions are implementation
|
|
|
|
|
// dependant.
|
|
|
|
|
def : InstRW<[GenericWriteMove], (instrs CFC2_MM, CTC2_MM)>;
|
|
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|
|
// MIPS MT ASE - hasMT
|
|
|
|
|
// ====================
|
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|
|
|
|
|
def : InstRW<[GenericWriteMove], (instrs DMT, DVPE, EMT, EVPE, MFTR,
|
|
|
|
|
MTTR)>;
|
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|
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|
|
def : InstRW<[GenericReadWriteCOP0Long], (instrs YIELD)>;
|
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|
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|
|
def : InstRW<[GenericWriteCOP0Short], (instrs FORK)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:33:01 +08:00
|
|
|
// MIPS Virtualization ASE
|
|
|
|
|
// =======================
|
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|
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|
|
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|
|
def : InstRW<[GenericWriteCOP0Short], (instrs HYPCALL, TLBGINV, TLBGINVF, TLBGP,
|
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|
|
|
TLBGR, TLBGWI, TLBGWR, MFGC0, MFHGC0,
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|
|
|
MTGC0, MTHGC0)>;
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|
|
// MIPS64 Virtualization ASE
|
|
|
|
|
// =========================
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|
|
def : InstRW<[GenericWriteCOP0Short], (instrs DMFGC0, DMTGC0)>;
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|
|
// microMIPS virtualization ASE
|
|
|
|
|
// ============================
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|
|
def : InstRW<[GenericWriteCOP0Short], (instrs HYPCALL_MM, TLBGINVF_MM,
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|
|
|
TLBGINV_MM, TLBGP_MM, TLBGR_MM,
|
|
|
|
|
TLBGWI_MM, TLBGWR_MM, MFGC0_MM,
|
|
|
|
|
MFHGC0_MM, MTGC0_MM, MTHGC0_MM)>;
|
|
|
|
|
|
2016-09-01 23:03:13 +08:00
|
|
|
// LDST Pipeline
|
|
|
|
|
// -------------
|
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|
|
def GenericWriteLoad : SchedWriteRes<[GenericIssueLDST]> {
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|
|
let Latency = 2;
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|
|
}
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|
|
def GenericWritePref : SchedWriteRes<[GenericIssueLDST]>;
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|
|
def GenericWriteSync : SchedWriteRes<[GenericIssueLDST]>;
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|
|
def GenericWriteCache : SchedWriteRes<[GenericIssueLDST]> { let Latency = 5; }
|
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|
|
def GenericWriteStore : SchedWriteRes<[GenericIssueLDST]>;
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|
|
def GenericWriteStoreSC : SchedWriteRes<[GenericIssueLDST]> { let Latency = 2; }
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|
|
def GenericWriteGPRFromBypass : SchedWriteRes<[GenericIssueLDST]> {
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|
|
|
|
let Latency = 2;
|
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|
|
|
}
|
|
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|
|
def GenericWriteStoreFromOtherUnits : SchedWriteRes<[GenericIssueLDST]>;
|
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|
|
|
def GenericWriteLoadToOtherUnits : SchedWriteRes<[GenericIssueLDST]> {
|
|
|
|
|
let Latency = 0;
|
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|
|
|
}
|
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|
|
// l[bhw], l[bh]u, ll
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LB, LBu, LH, LHu, LW, LL,
|
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|
|
|
LWC2, LWC3, LDC2, LDC3)>;
|
2016-09-01 23:03:13 +08:00
|
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|
|
// lw[lr]
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LWL, LWR)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// s[bhw], sc, s[dw]c[23]
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SB, SH, SW, SWC2, SWC3,
|
|
|
|
|
SDC2, SDC3)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// PreMIPSR6 sw[lr]
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 20:27:51 +08:00
|
|
|
def : InstRW<[GenericWriteStoreSC], (instrs SC, SC_MMR6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// pref
|
|
|
|
|
def : InstRW<[GenericWritePref], (instrs PREF)>;
|
|
|
|
|
// cache
|
|
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// sync
|
|
|
|
|
def : InstRW<[GenericWriteSync], (instrs SYNC, SYNCI)>;
|
2017-07-12 19:57:44 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// MIPSR6
|
|
|
|
|
// ======
|
2017-07-12 19:57:44 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LDC2_R6, LL_R6, LWC2_R6, LWPC)>;
|
2017-11-15 06:26:42 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs SWC2_R6, SDC2_R6)>;
|
2017-07-12 19:57:44 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStoreSC], (instrs SC_R6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWritePref], (instrs PREF_R6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHE_R6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:33:16 +08:00
|
|
|
def : InstRW<[GenericWriteSync], (instrs GINVI, GINVT)>;
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// MIPS32 EVA
|
|
|
|
|
// ==========
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LBE, LBuE, LHE, LHuE, LWE,
|
|
|
|
|
LLE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs SBE, SHE, SWE, SCE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LWLE, LWRE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs SWLE, SWRE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWritePref], (instrs PREFE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHEE)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// microMIPS EVA ASE - InMicroMipsMode, hasEVA
|
|
|
|
|
// ===========================================
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LBE_MM, LBuE_MM, LHE_MM, LHuE_MM,
|
|
|
|
|
LWE_MM, LWLE_MM, LWRE_MM, LLE_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs SBE_MM, SB_MM, SHE_MM, SWE_MM,
|
|
|
|
|
SWLE_MM, SWRE_MM, SCE_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWritePref], (instrs PREFE_MM)>;
|
|
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHEE_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
|
|
|
|
|
// MIPS16e
|
|
|
|
|
// =======
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs Restore16, RestoreX16,
|
|
|
|
|
LbRxRyOffMemX16,
|
|
|
|
|
LbuRxRyOffMemX16, LhRxRyOffMemX16,
|
|
|
|
|
LhuRxRyOffMemX16, LwRxRyOffMemX16,
|
|
|
|
|
LwRxSpImmX16, LwRxPcTcp16, LwRxPcTcpX16)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs Save16, SaveX16, SbRxRyOffMemX16,
|
|
|
|
|
ShRxRyOffMemX16, SwRxRyOffMemX16,
|
|
|
|
|
SwRxSpImmX16)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// microMIPS
|
|
|
|
|
// =========
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LBU16_MM, LB_MM, LBu_MM, LHU16_MM,
|
|
|
|
|
LH_MM, LHu_MM, LL_MM, LW16_MM, LWGP_MM,
|
|
|
|
|
LWL_MM, LWM16_MM, LWM32_MM, LWP_MM, LWR_MM,
|
|
|
|
|
LWSP_MM, LWU_MM, LWXS_MM, LW_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteStore], (instrs SB16_MM, SC_MM, SH16_MM, SH_MM,
|
2019-07-03 20:27:51 +08:00
|
|
|
SW16_MM, SWL_MM, SWM16_MM, SWM32_MM, SWM_MM,
|
2019-07-03 18:32:54 +08:00
|
|
|
SWP_MM, SWR_MM, SWSP_MM, SW_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWritePref], (instrs PREF_MM, PREFX_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHE_MM)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteSync], (instrs SYNC_MM, SYNCI_MM)>;
|
2019-07-03 18:33:16 +08:00
|
|
|
def : InstRW<[GenericWriteSync], (instrs GINVI_MMR6, GINVT_MMR6)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// microMIPS32r6
|
|
|
|
|
// =============
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 20:27:51 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LBU_MMR6, LB_MMR6, LDC2_MMR6, LL_MMR6,
|
2019-07-03 18:32:54 +08:00
|
|
|
LWM16_MMR6, LWC2_MMR6, LWPC_MMR6, LW_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SB16_MMR6, SB_MMR6, SDC2_MMR6,
|
|
|
|
|
SH16_MMR6, SH_MMR6, SW16_MMR6, SWC2_MMR6,
|
|
|
|
|
SWM16_MMR6, SWSP_MMR6, SW_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteSync], (instrs SYNC_MMR6, SYNCI_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWritePref], (instrs PREF_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteCache], (instrs CACHE_MMR6)>;
|
|
|
|
|
|
|
|
|
|
// MIPS64
|
|
|
|
|
// ======
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LD, LL64, LLD, LWu, LB64, LBu64,
|
|
|
|
|
LH64, LHu64, LW64)>;
|
|
|
|
|
|
|
|
|
|
// l[dw][lr]
|
|
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LWL64, LWR64, LDL, LDR)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64,
|
|
|
|
|
SWL64, SWR64)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SDL, SDR)>;
|
|
|
|
|
|
|
|
|
|
// MIPS64R6
|
|
|
|
|
// ========
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LWUPC, LDPC)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LLD_R6, LL64_R6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteStoreSC], (instrs SC64_R6, SCD_R6)>;
|
|
|
|
|
|
|
|
|
|
// MIPSR6 CRC ASE - hasCRC
|
|
|
|
|
// =======================
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteALU], (instrs CRC32B, CRC32H, CRC32W, CRC32CB,
|
|
|
|
|
CRC32CH, CRC32CW)>;
|
|
|
|
|
|
|
|
|
|
// MIPS64R6 CRC ASE - hasCRC
|
|
|
|
|
// -------------------------
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteALU], (instrs CRC32D, CRC32CD)>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips
|
|
|
|
|
// =================================================
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteALU], (instrs BADDu, BBIT0, BBIT032, BBIT1, BBIT132,
|
|
|
|
|
CINS, CINS32, CINS64_32, CINS_i32,
|
|
|
|
|
DMFC2_OCTEON, DMTC2_OCTEON, DPOP, EXTS,
|
|
|
|
|
EXTS32, MTM0, MTM1, MTM2, MTP0, MTP1, MTP2,
|
|
|
|
|
POP, SEQ, SEQi, SNE, SNEi, V3MULU, VMM0,
|
|
|
|
|
VMULU)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteMDUtoGPR], (instrs DMUL)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// FPU Pipelines
|
|
|
|
|
// =============
|
|
|
|
|
|
|
|
|
|
def GenericFPQ : ProcResource<1> { let BufferSize = 1; }
|
|
|
|
|
def GenericIssueFPUS : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
def GenericIssueFPUL : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
def GenericIssueFPULoad : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
def GenericIssueFPUStore : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
def GenericIssueFPUMove : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
def GenericFPUDivSqrt : ProcResource<1> { let Super = GenericFPQ; }
|
|
|
|
|
|
|
|
|
|
// The floating point compare of the 24k series including interAptiv has a
|
|
|
|
|
// listed latency of 1-2. Using the higher latency here.
|
|
|
|
|
|
|
|
|
|
def GenericWriteFPUCmp : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 2; }
|
|
|
|
|
def GenericWriteFPUS : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 4; }
|
|
|
|
|
def GenericWriteFPUL : SchedWriteRes<[GenericIssueFPUL]> { let Latency = 5; }
|
|
|
|
|
def GenericWriteFPUStore : SchedWriteRes<[GenericIssueFPUStore]> { let
|
|
|
|
|
Latency = 1;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPULoad : SchedWriteRes<[GenericIssueFPULoad]> {
|
|
|
|
|
let Latency = 2;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPUMoveFP : SchedWriteRes<[GenericIssueFPUMove]> {
|
|
|
|
|
let Latency = 4;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> {
|
|
|
|
|
let Latency = 2;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> {
|
|
|
|
|
let Latency = 17;
|
|
|
|
|
let ResourceCycles = [ 14 ];
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> {
|
|
|
|
|
let Latency = 32;
|
|
|
|
|
let ResourceCycles = [ 29 ];
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> {
|
|
|
|
|
let Latency = 13;
|
|
|
|
|
let ResourceCycles = [ 10 ];
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> {
|
|
|
|
|
let Latency = 25;
|
|
|
|
|
let ResourceCycles = [ 21 ];
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
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let Latency = 17;
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let ResourceCycles = [ 14 ];
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}
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def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
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let Latency = 32;
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let ResourceCycles = [ 29 ];
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}
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def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
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let Latency = 17;
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let ResourceCycles = [ 14 ];
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}
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def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
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let Latency = 29;
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let ResourceCycles = [ 29 ];
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}
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// Floating point compare and branch
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// ---------------------------------
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//
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// c.<cc>.[ds], bc1[tf], bc1[tf]l
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_D32, FCMP_D64, FCMP_S32, BC1F,
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BC1T, BC1FL, BC1TL)>;
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2016-09-01 23:03:13 +08:00
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteFPUCmp], (instregex "C_[A-Z]+_(S|D32|D64)$")>;
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2016-09-01 23:03:13 +08:00
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// Short Pipe
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// ----------
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//
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// abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s
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// nmsub.s, sub.[ds], mul.s
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, FADD_D32,
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FADD_D64, FADD_S, MADD_S, MSUB_S, FMUL_S,
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FNEG_S, FNEG_D32, FNEG_D64, NMADD_S, NMSUB_S,
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FSUB_S, FSUB_D32, FSUB_D64)>;
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2016-09-01 23:03:13 +08:00
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// Long Pipe
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// ----------
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//
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// nmadd.d, nmsub.d, mul.[ds], mul.ps, ceil.[wl].[sd], cvt.d.[sw], cvt.s.[dw],
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// cvt.w.[sd], cvt.[sw].ps, trunc.w.[ds], trunc.w.ps, floor.[ds],
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// round.[lw].[ds], floor.[lw].ds
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// madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw],
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// cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds,
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// trunc.w.[ds], trunc.w.ps,
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32,
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CEIL_W_D64, CEIL_W_S, CVT_D32_S, CVT_D32_W,
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CVT_D64_L, CVT_D64_S, CVT_D64_W, CVT_L_D64,
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CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L,
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CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S,
|
2019-07-03 20:27:51 +08:00
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CVT_PS_S64, CVT_S_PL64, CVT_S_PU64,
|
2019-07-03 18:32:54 +08:00
|
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FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32,
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FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64,
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MADD_D32, MADD_D64, MSUB_D32, MSUB_D64,
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NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64,
|
2019-07-03 20:27:51 +08:00
|
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PLL_PS64, PLU_PS64,
|
2019-07-03 18:32:54 +08:00
|
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|
ROUND_L_D64, ROUND_L_S, ROUND_W_D32,
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ROUND_W_D64, ROUND_W_S, TRUNC_L_D64,
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TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64,
|
2019-07-03 20:27:51 +08:00
|
|
|
TRUNC_W_S, PseudoTRUNC_W_D,
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|
|
PseudoTRUNC_W_D32, PseudoTRUNC_W_S)>;
|
2019-07-03 18:32:54 +08:00
|
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|
|
// Pseudo convert instruction
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|
def : InstRW<[GenericWriteFPUL], (instrs PseudoCVT_D32_W, PseudoCVT_D64_L,
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|
PseudoCVT_D64_W, PseudoCVT_S_L,
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|
|
PseudoCVT_S_W)>;
|
2016-09-01 23:03:13 +08:00
|
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|
|
// div.[ds], div.ps
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S)>;
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def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32, FDIV_D64)>;
|
2016-09-01 23:03:13 +08:00
|
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|
|
// sqrt.[ds], sqrt.ps
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S)>;
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def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32, FSQRT_D64)>;
|
2016-09-01 23:03:13 +08:00
|
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|
|
2016-10-06 00:11:01 +08:00
|
|
|
// rsqrt.[ds], recip.[ds]
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S, RSQRT_S)>;
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|
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|
|
def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32, RECIP_D64,
|
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|
|
RSQRT_D32, RSQRT_D64)>;
|
2016-10-06 00:11:01 +08:00
|
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|
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// Load Pipe
|
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|
|
// ---------
|
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|
|
// ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs BuildPairF64,
|
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|
|
BuildPairF64_64, ExtractElementF64,
|
|
|
|
|
ExtractElementF64_64, CFC1, CTC1,
|
|
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|
|
MFC1, MFC1_D64, MFHC1_D32,
|
|
|
|
|
MFHC1_D64, MTC1, MTC1_D64,
|
|
|
|
|
MTHC1_D32, MTHC1_D64)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// swc1, swxc1
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUStore], (instrs SDC1, SDC164, SDXC1, SDXC164,
|
|
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|
|
SUXC1, SUXC164, SWC1, SWXC1)>;
|
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|
|
|
def : InstRW<[GenericWriteFPUMoveFP], (instrs FMOV_D32, FMOV_D64, FMOV_S)>;
|
|
|
|
|
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
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|
|
// movn.[ds], movz.[ds]
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_I, MOVF_D32, MOVF_D64,
|
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|
|
MOVF_S, MOVT_I, MOVT_D32, MOVT_D64,
|
|
|
|
|
MOVT_S, MOVN_I_D32, MOVN_I_D64,
|
|
|
|
|
MOVN_I_S, MOVZ_I_D32, MOVZ_I_D64,
|
|
|
|
|
MOVZ_I_S)>;
|
|
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|
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|
|
|
|
def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVT_I64, MOVF_I64, MOVZ_I64_S,
|
|
|
|
|
MOVN_I64_D64, MOVN_I64_S,
|
|
|
|
|
MOVZ_I64_D64)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// l[dw]x?c1
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPULoad], (instrs LDC1, LDC164, LDXC1, LDXC164,
|
|
|
|
|
LUXC1, LUXC164, LWC1, LWXC1)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// MIPSR6
|
2016-09-01 23:03:13 +08:00
|
|
|
// ======
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds]
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs SELEQZ_S, SELNEZ_S, SELEQZ_D, SELNEZ_D,
|
|
|
|
|
MAX_S, MAX_D, MAXA_S, MAXA_D, MIN_S, MIN_D,
|
|
|
|
|
MINA_S, MINA_D, CLASS_S, CLASS_D)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUL], (instrs RINT_S, RINT_D)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instrs BC1EQZ, BC1NEZ, SEL_D, SEL_S)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs MADDF_S, MSUBF_S, MADDF_D, MSUBF_D)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
// microMIPS
|
|
|
|
|
// =========
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUMoveFP], (instrs MOVF_D32_MM, MOVF_S_MM,
|
|
|
|
|
MOVN_I_D32_MM, MOVN_I_S_MM,
|
|
|
|
|
MOVT_D32_MM, MOVT_S_MM, MOVZ_I_D32_MM,
|
|
|
|
|
MOVZ_I_S_MM)>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// cvt.?.?, ceil.?, floor.?, round.?, trunc.? (n)madd.? (n)msub.?
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instrs CVT_D32_S_MM, CVT_D32_W_MM,
|
|
|
|
|
CVT_D64_S_MM, CVT_D64_W_MM, CVT_L_D64_MM,
|
|
|
|
|
CVT_L_S_MM, CVT_S_D32_MM, CVT_S_D64_MM,
|
|
|
|
|
CVT_S_W_MM, CVT_W_D32_MM, CVT_W_D64_MM,
|
|
|
|
|
CVT_W_S_MM, CEIL_W_MM, CEIL_W_S_MM,
|
|
|
|
|
FLOOR_W_MM, FLOOR_W_S_MM, NMADD_S_MM,
|
|
|
|
|
NMADD_D32_MM, NMSUB_S_MM, NMSUB_D32_MM,
|
|
|
|
|
MADD_S_MM, MADD_D32_MM, ROUND_W_MM,
|
|
|
|
|
ROUND_W_S_MM, TRUNC_W_MM, TRUNC_W_S_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z]_(S|D32|D64)_MM$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z]_(S|D32|D64)_MM$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instregex "^C_[A-Z][A-Z][A-Z]_(S|D32|D64)_MM$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instregex "^C_NGLE_(S|D32|D64)_MM$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instrs FCMP_S32_MM, FCMP_D32_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs MFC1_MM, MFHC1_D32_MM, MFHC1_D64_MM,
|
2019-07-03 20:27:51 +08:00
|
|
|
MTC1_MM, MTC1_D64_MM,
|
|
|
|
|
MTHC1_D32_MM, MTHC1_D64_MM)>;
|
2019-07-03 18:32:54 +08:00
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs FABS_D32_MM, FABS_D64_MM, FABS_S_MM,
|
|
|
|
|
FNEG_D32_MM, FNEG_D64_MM, FNEG_S_MM,
|
|
|
|
|
FADD_D32_MM, FADD_D64_MM, FADD_S_MM,
|
|
|
|
|
FMOV_D32_MM, FMOV_D64_MM, FMOV_S_MM,
|
|
|
|
|
FMUL_D32_MM, FMUL_D64_MM, FMUL_S_MM,
|
|
|
|
|
FSUB_D32_MM, FSUB_D64_MM, FSUB_S_MM,
|
|
|
|
|
MSUB_S_MM, MSUB_D32_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUDivS], (instrs FDIV_S_MM)>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUDivD], (instrs FDIV_D32_MM, FDIV_D64_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUSqrtS], (instrs FSQRT_S_MM)>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUSqrtD], (instrs FSQRT_D32_MM, FSQRT_D64_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPURcpS], (instrs RECIP_S_MM, RSQRT_S_MM)>;
|
|
|
|
|
def : InstRW<[GenericWriteFPURcpD], (instrs RECIP_D32_MM, RECIP_D64_MM,
|
|
|
|
|
RSQRT_D32_MM, RSQRT_D64_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUStore], (instrs SDC1_MM, SWC1_MM, SUXC1_MM,
|
|
|
|
|
SWXC1_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs CFC1_MM, CTC1_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPULoad], (instrs LDC1_MM, LUXC1_MM, LWC1_MM,
|
|
|
|
|
LWXC1_MM)>;
|
|
|
|
|
|
|
|
|
|
// microMIPS32r6
|
|
|
|
|
// =============
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs FNEG_S_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp], (instregex "CMP_[A-Z][A-Z]_(S|D)_MMR6")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp],
|
|
|
|
|
(instregex "CMP_[A-Z][A-Z][A-Z]_(S|D)_MMR6")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUCmp],
|
|
|
|
|
(instregex "CMP_[A-Z][A-Z][A-Z][A-Z]_(S|D)_MMR6")>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteFPUL],
|
|
|
|
|
(instregex "CVT_(L|D|S|W)_(L|D|S|L|W)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUL],
|
|
|
|
|
(instregex "TRUNC_(L|W)_(D|S)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUL],
|
|
|
|
|
(instregex "ROUND_(L|W)_(D|S)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUL],
|
|
|
|
|
(instregex "FLOOR_(L|W)_(D|S)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUL],
|
|
|
|
|
(instregex "CEIL_(L|W)_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS],
|
|
|
|
|
(instrs MFC1_MMR6, MTC1_MMR6, CLASS_S_MMR6, CLASS_D_MMR6,
|
|
|
|
|
FADD_S_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instregex "M(IN|AX)A_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instregex "SEL(EQ|NE)Z_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instregex "SEL_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instrs RINT_S_MMR6, RINT_D_MMR6)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instregex "M(ADD|SUB)F_(S|D)_MMR6")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUS], (instrs FMOV_S_MMR6, FMUL_S_MMR6,
|
2019-07-03 20:27:51 +08:00
|
|
|
FSUB_S_MMR6, FMOV_D_MMR6)>;
|
2019-07-03 18:32:54 +08:00
|
|
|
|
|
|
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|
def : InstRW<[GenericWriteFPUL], (instrs FDIV_S_MMR6)>;
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def : InstRW<[GenericWriteFPUStore], (instrs SDC1_D64_MMR6)>;
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def : InstRW<[GenericWriteFPULoad], (instrs LDC1_D64_MMR6)>;
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// MIPS64
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// ======
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def : InstRW<[GenericWriteFPUMoveGPRFPU], (instrs DMFC1, DMTC1)>;
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2016-09-01 23:03:13 +08:00
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// MIPS DSP ASE, HasDSP
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// ====================
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2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteStore], (instrs SWDSP)>;
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def : InstRW<[GenericWriteLoad], (instrs LWDSP)>;
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def : InstRW<[GenericWriteMove], (instrs PseudoMTLOHI_DSP)>;
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2016-09-01 23:03:13 +08:00
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def GenericDSP : ProcResource<1> { let BufferSize = 1; }
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def GenericDSPShort : SchedWriteRes<[GenericDSP]> { let Latency = 2; }
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def GenericDSPLong : SchedWriteRes<[GenericDSP]> { let Latency = 6; }
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def GenericDSPBypass : SchedWriteRes<[GenericDSP]> { let Latency = 1; }
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def GenericDSPMTHILO : SchedWriteRes<[GenericDSP]> { let Latency = 5; }
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def GenericDSPLoad : SchedWriteRes<[GenericDSP]> { let Latency = 4; }
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def GenericDSPMTHLIP : SchedWriteRes<[GenericDSP]> { let Latency = 5; }
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def : InstRW<[GenericDSPLong], (instregex "^EXTRV_RS_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTRV_R_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTRV_S_H$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTRV_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTR_RS_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTR_R_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTR_S_H$")>;
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def : InstRW<[GenericDSPLong], (instregex "^EXTR_W$")>;
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def : InstRW<[GenericDSPLong], (instregex "^INSV$")>;
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def : InstRW<[GenericDSPMTHLIP], (instregex "^MTHLIP$")>;
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def : InstRW<[GenericDSPMTHILO], (instregex "^MTHI_DSP$")>;
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def : InstRW<[GenericDSPMTHILO], (instregex "^MTLO_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDSC$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^ADDWC$")>;
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def : InstRW<[GenericDSPShort], (instregex "^BITREV$")>;
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def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV$")>;
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def : InstRW<[GenericDSPShort], (instregex "^EXTPDP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^EXTPV$")>;
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def : InstRW<[GenericDSPShort], (instregex "^EXTP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^LBUX$")>;
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def : InstRW<[GenericDSPShort], (instregex "^LHX$")>;
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def : InstRW<[GenericDSPShort], (instregex "^LWX$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MODSUB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PICK_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PICK_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^RDDSP$")>;
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def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^REPL_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^REPL_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHILOV$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHILO$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W$")>;
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def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB$")>;
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|
def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB$")>;
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|
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|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^WRDSP$")>;
|
|
|
|
|
|
2019-07-03 18:33:01 +08:00
|
|
|
def : InstRW<[GenericDSPShort],
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|
|
|
|
(instregex "^Pseudo(CMP|CMPU)_(EQ|LE|LT)_(PH|QB)$")>;
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|
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|
|
def : InstRW<[GenericDSPShort],
|
|
|
|
|
(instregex "^PseudoPICK_(PH|QB)$")>;
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|
|
|
|
|
2016-09-01 23:03:13 +08:00
|
|
|
// MIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips
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|
|
|
|
// ===========================================
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|
|
def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^APPEND$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^BALIGN$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB$")>;
|
|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB$")>;
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|
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|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH$")>;
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|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MUL_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PREPEND$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB$")>;
|
|
|
|
|
|
|
|
|
|
// microMIPS DSP R1 - HasDSP, InMicroMips
|
|
|
|
|
// ======================================
|
|
|
|
|
|
2019-07-03 18:32:54 +08:00
|
|
|
def : InstRW<[GenericWriteLoad], (instrs LWDSP_MM)>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteStore], (instrs SWDSP_MM)>;
|
|
|
|
|
|
2016-09-01 23:03:13 +08:00
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDSC_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDWC_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^BITREV_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTPDP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTPV_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTRV_RS_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTRV_R_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTRV_S_H_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTRV_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTR_RS_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTR_R_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTR_S_H_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^EXTR_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^INSV_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^LBUX_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^LHX_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^LWX_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>;
|
2017-11-06 20:59:53 +08:00
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>;
|
2016-09-01 23:03:13 +08:00
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PICK_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PICK_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^RDDSP_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^REPL_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^REPL_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHILOV_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHILO_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB_MM$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^WRDSP_MM$")>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// microMIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips
|
|
|
|
|
// ================================================
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^APPEND_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^BALIGN_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MUL_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^PREPEND_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB_MMR2$")>;
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB_MMR2$")>;
|
|
|
|
|
|
|
|
|
|
// microMIPS DSP R3 - hasDSP, hasDSPR2, hasDSPR3, InMicroMips
|
|
|
|
|
// ==========================================================
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32C_MMR3$")>;
|
|
|
|
|
|
|
|
|
|
// MIPS MSA ASE - hasMSA
|
|
|
|
|
// =====================
|
|
|
|
|
|
|
|
|
|
def GenericWriteMSAShortLogic : SchedWriteRes<[GenericIssueFPUS]>;
|
|
|
|
|
def GenericWriteMSAShortInt : SchedWriteRes<[GenericIssueFPUS]> {
|
|
|
|
|
let Latency = 2;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteMoveOtherUnitsToFPU : SchedWriteRes<[GenericIssueFPUS]>;
|
|
|
|
|
def GenericWriteMSAOther3 : SchedWriteRes<[GenericIssueFPUS]> {
|
|
|
|
|
let Latency = 3;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteMSALongInt : SchedWriteRes<[GenericIssueFPUS]> {
|
|
|
|
|
let Latency = 5;
|
|
|
|
|
}
|
|
|
|
|
def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> {
|
|
|
|
|
let Latency = 33;
|
|
|
|
|
let ResourceCycles = [ 33 ];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// FPUS is also used in moves from floating point and MSA registers to general
|
|
|
|
|
// purpose registers.
|
|
|
|
|
def GenericWriteMoveFPUSToOtherUnits : SchedWriteRes<[GenericIssueFPUS]> {
|
|
|
|
|
let Latency = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// FPUL is also used in moves from floating point and MSA registers to general
|
|
|
|
|
// purpose registers.
|
|
|
|
|
def GenericWriteMoveFPULToOtherUnits : SchedWriteRes<[GenericIssueFPUL]>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd],
|
|
|
|
|
// aver?_[us].[bhwd]
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>;
|
|
|
|
|
|
|
|
|
|
// TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it.
|
|
|
|
|
// add.[bhwd], addvi.[bhwd], asub_[us].[bhwd], ave.[bhwd], aver.[bhwd]
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>;
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|
2019-07-03 18:32:54 +08:00
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|
// and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b, lsa
|
2016-09-01 23:03:13 +08:00
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|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^MOVE_V$")>;
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def : InstRW<[GenericWriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>;
|
2019-07-03 18:32:54 +08:00
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def : InstRW<[GenericWriteMSAShortLogic], (instrs LSA)>;
|
2016-09-01 23:03:13 +08:00
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def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>;
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def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>;
|
2019-07-03 18:33:01 +08:00
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def : InstRW<[GenericWriteMSAShortLogic],
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(instregex "^(AND|OR|[XN]OR)_V_[DHW]_PSEUDO$")>;
|
2016-09-01 23:03:13 +08:00
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// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd],
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// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>;
|
2019-07-03 18:33:01 +08:00
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def : InstRW<[GenericWriteMSAShortInt],
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(instregex "^BSEL_(H|W|D|FW|FD)_PSEUDO$")>;
|
2016-09-01 23:03:13 +08:00
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|
2019-07-03 18:32:54 +08:00
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// pcnt.[bhwd], sat_s.[bhwd], sat_u.[bhwd]
|
2016-09-01 23:03:13 +08:00
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def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>;
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// bnz.[bhwdv], cfcmsa, ctcmsa
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def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>;
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def : InstRW<[GenericWriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>;
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// shf.[bhw], fill[bhwd], splat?.[bhwd]
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^SHF_[BHW]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^FILL_[BHWD]$")>;
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def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>;
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// fexp2_w, fexp2_d
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def : InstRW<[GenericWriteFPUS], (instregex "^FEXP2_(W|D)$")>;
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// compare, converts, round to int, floating point truncate.
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def : InstRW<[GenericWriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UN_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_EQ_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LT_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULT_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LE_(S|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULE_(S|D)$")>;
|
2019-07-03 18:32:54 +08:00
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|
def : InstRW<[GenericWriteFPUS], (instregex "^CMP_F_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SAF_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SEQ_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLE_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SLT_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUEQ_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULE_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SULT_(D|S)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^CMP_SUN_(D|S)$")>;
|
2016-09-01 23:03:13 +08:00
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FSUEQ_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FSULE_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FSULT_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FSUNE_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FSUN_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCAF_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCEQ_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCLE_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCLT_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCNE_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCOR_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCUEQ_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCULE_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCULT_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCUNE_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FCUN_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FABS_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FFQL_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FFQR_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FRINT_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FTQ_(H|W)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>;
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|
// fexdo.[hw], fexupl.[wd], fexupr.[wd]
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FEXDO_(H|W)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPL_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPR_(W|D)$")>;
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|
// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd]
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FCLASS_(W|D)$")>;
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def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_A_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_A_(W|D)$")>;
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|
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_(W|D)$")>;
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|
def : InstRW<[GenericWriteFPUS], (instregex "^FLOG2_(W|D)$")>;
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|
|
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|
|
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|
|
// interleave right/left, interleave even/odd, insert
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>;
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|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>;
|
|
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|
|
|
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|
|
// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd],
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|
|
|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>;
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|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>;
|
|
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|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>;
|
|
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|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>;
|
|
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|
|
def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>;
|
|
|
|
|
|
|
|
|
|
// mod_[su].[bhwd], div_[su].[bhwd]
|
|
|
|
|
def : InstRW<[GenericWriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>;
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|
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|
|
def : InstRW<[GenericWriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>;
|
|
|
|
|
|
|
|
|
|
// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd],
|
|
|
|
|
// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd],
|
|
|
|
|
// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd],
|
|
|
|
|
// insve.[bhwd]
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic],
|
|
|
|
|
(instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>;
|
2019-07-03 18:33:01 +08:00
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSERT_F(D|W)_PSEUDO$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSAShortLogic], (instregex "^FILL_F(D|W)_PSEUDO$")>;
|
2016-09-01 23:03:13 +08:00
|
|
|
|
|
|
|
|
// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd]
|
|
|
|
|
// mulv.[bhwd].
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDV_[BHWD]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MULV_[BHWD]$")>;
|
|
|
|
|
|
|
|
|
|
// madd?.q.[hw], msub?.q.[hw], mul?.q.[hw]
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>;
|
|
|
|
|
|
|
|
|
|
// fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw]
|
|
|
|
|
// fsub.[dw], fdiv.[dw]
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FADD_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FMADD_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FMSUB_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FMUL_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FRCP_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FRSQRT_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FSQRT_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FSUB_[DW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUL], (instregex "^FDIV_[DW]$")>;
|
|
|
|
|
|
|
|
|
|
// copy.[su]_[bhwd]
|
|
|
|
|
def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_U_[BHW]$")>;
|
|
|
|
|
def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_S_[BHWD]$")>;
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteFPUStore], (instregex "^ST_[BHWD]$")>;
|
2019-07-03 18:33:01 +08:00
|
|
|
def : InstRW<[GenericWriteFPUStore], (instrs ST_F16)>;
|
2016-09-01 23:03:13 +08:00
|
|
|
def : InstRW<[GenericWriteFPULoad], (instregex "^LD_[BHWD]$")>;
|
2019-07-03 18:33:01 +08:00
|
|
|
def : InstRW<[GenericWriteFPULoad], (instrs LD_F16)>;
|
2019-07-03 20:27:58 +08:00
|
|
|
|
|
|
|
|
// Atomic instructions
|
|
|
|
|
|
|
|
|
|
// FIXME: Define `WriteAtomic` in the MipsSchedule.td and
|
|
|
|
|
// attach it to the Atomic2OpsPostRA, AtomicCmpSwapPostRA, ...
|
|
|
|
|
// classes. Then just define resources for the `WriteAtomic` in each
|
|
|
|
|
// machine models.
|
|
|
|
|
def GenericAtomic : ProcResource<1> { let BufferSize = 1; }
|
|
|
|
|
def GenericWriteAtomic : SchedWriteRes<[GenericAtomic]> { let Latency = 2; }
|
|
|
|
|
|
|
|
|
|
def : InstRW<[GenericWriteAtomic],
|
|
|
|
|
(instregex "^ATOMIC_SWAP_I(8|16|32|64)_POSTRA$")>;
|
|
|
|
|
def : InstRW<[GenericWriteAtomic],
|
|
|
|
|
(instregex "^ATOMIC_CMP_SWAP_I(8|16|32|64)_POSTRA$")>;
|
|
|
|
|
def : InstRW<[GenericWriteAtomic],
|
|
|
|
|
(instregex "^ATOMIC_LOAD_(ADD|SUB|AND|OR|XOR|NAND)_I(8|16|32|64)_POSTRA$")>;
|
2016-09-01 23:03:13 +08:00
|
|
|
}
|
