2012-12-12 05:25:42 +08:00
|
|
|
set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
|
|
|
|
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
|
|
|
|
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
|
2012-12-12 05:25:42 +08:00
|
|
|
tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
|
2016-02-18 11:42:32 +08:00
|
|
|
tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
|
|
|
|
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
|
2016-10-07 01:19:11 +08:00
|
|
|
tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
|
2017-08-04 05:52:25 +08:00
|
|
|
tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
|
AMDGPU: Make getTgtMemIntrinsic table-driven for resource-based intrinsics
Summary:
Avoids having to list all intrinsics manually.
This is in preparation for the new dimension-aware image intrinsics,
which I'd rather not have to list here by hand.
Change-Id: If7ced04998397ef68c4cb8f7de66b5050fb767e5
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44937
llvm-svn: 328938
2018-04-02 01:09:07 +08:00
|
|
|
tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
|
2018-04-04 20:37:44 +08:00
|
|
|
tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
|
|
|
|
|
AMDGPU/GlobalISel: Enable TableGen'd instruction selector
Reviewers: arsenm, nhaehnle
Reviewed By: arsenm
Subscribers: kzhuravl, wdng, mgorny, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45994
llvm-svn: 332039
2018-05-11 04:53:06 +08:00
|
|
|
set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
|
|
|
|
tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
|
|
|
|
|
AMDGPU: Separate R600 and GCN TableGen files
Summary:
We now have two sets of generated TableGen files, one for R600 and one
for GCN, so each sub-target now has its own tables of instructions,
registers, ISel patterns, etc. This should help reduce compile time
since each sub-target now only has to consider information that
is specific to itself. This will also help prevent the R600
sub-target from slowing down new features for GCN, like disassembler
support, GlobalISel, etc.
Reviewers: arsenm, nhaehnle, jvesely
Reviewed By: arsenm
Subscribers: MatzeB, kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46365
llvm-svn: 335942
2018-06-29 07:47:12 +08:00
|
|
|
set(LLVM_TARGET_DEFINITIONS R600.td)
|
|
|
|
tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
|
|
|
|
tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
|
|
|
|
tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
|
|
|
|
tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
|
|
|
|
tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
|
|
|
|
tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
|
|
|
|
tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
|
|
|
|
tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
|
|
|
|
|
2012-12-12 05:25:42 +08:00
|
|
|
add_public_tablegen_target(AMDGPUCommonTableGen)
|
|
|
|
|
2015-06-13 11:28:10 +08:00
|
|
|
add_llvm_target(AMDGPUCodeGen
|
2017-03-18 07:56:58 +08:00
|
|
|
AMDGPUAliasAnalysis.cpp
|
2014-11-04 03:49:05 +08:00
|
|
|
AMDGPUAlwaysInlinePass.cpp
|
2015-11-07 02:01:57 +08:00
|
|
|
AMDGPUAnnotateKernelFeatures.cpp
|
2015-12-16 04:55:55 +08:00
|
|
|
AMDGPUAnnotateUniformValues.cpp
|
2017-08-04 06:30:46 +08:00
|
|
|
AMDGPUArgumentUsageInfo.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
AMDGPUAsmPrinter.cpp
|
2018-10-08 23:49:19 +08:00
|
|
|
AMDGPUAtomicOptimizer.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
AMDGPUCallLowering.cpp
|
2016-06-24 15:07:55 +08:00
|
|
|
AMDGPUCodeGenPrepare.cpp
|
2018-10-26 21:18:36 +08:00
|
|
|
AMDGPUFixFunctionBitcasts.cpp
|
2013-02-07 01:32:29 +08:00
|
|
|
AMDGPUFrameLowering.cpp
|
2018-07-11 04:07:22 +08:00
|
|
|
AMDGPUHSAMetadataStreamer.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDGPUInstrInfo.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
AMDGPUInstructionSelector.cpp
|
2013-07-23 09:48:29 +08:00
|
|
|
AMDGPUISelDAGToDAG.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDGPUISelLowering.cpp
|
|
|
|
AMDGPULegalizerInfo.cpp
|
|
|
|
AMDGPULibCalls.cpp
|
|
|
|
AMDGPULibFunc.cpp
|
2017-02-10 06:00:42 +08:00
|
|
|
AMDGPULowerIntrinsics.cpp
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-27 03:10:00 +08:00
|
|
|
AMDGPULowerKernelArguments.cpp
|
2018-05-19 05:35:00 +08:00
|
|
|
AMDGPULowerKernelAttributes.cpp
|
2017-05-16 04:18:37 +08:00
|
|
|
AMDGPUMachineCFGStructurizer.cpp
|
2013-04-02 06:05:58 +08:00
|
|
|
AMDGPUMachineFunction.cpp
|
2017-07-22 05:19:23 +08:00
|
|
|
AMDGPUMachineModuleInfo.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDGPUMacroFusion.cpp
|
|
|
|
AMDGPUMCInstLower.cpp
|
2017-10-11 03:39:48 +08:00
|
|
|
AMDGPUOpenCLEnqueuedBlockLowering.cpp
|
2014-06-18 00:53:14 +08:00
|
|
|
AMDGPUPromoteAlloca.cpp
|
2019-06-18 01:47:28 +08:00
|
|
|
AMDGPUPropagateAttributes.cpp
|
2017-08-04 05:52:25 +08:00
|
|
|
AMDGPURegisterBankInfo.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
AMDGPURegisterInfo.cpp
|
2017-07-29 02:40:05 +08:00
|
|
|
AMDGPURewriteOutArguments.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDGPUSubtarget.cpp
|
|
|
|
AMDGPUTargetMachine.cpp
|
|
|
|
AMDGPUTargetObjectFile.cpp
|
|
|
|
AMDGPUTargetTransformInfo.cpp
|
2017-03-25 03:52:05 +08:00
|
|
|
AMDGPUUnifyDivergentExitNodes.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDGPUUnifyMetadata.cpp
|
2017-09-20 12:25:58 +08:00
|
|
|
AMDGPUInline.cpp
|
2018-05-26 01:25:12 +08:00
|
|
|
AMDGPUPerfHintAnalysis.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
AMDILCFGStructurizer.cpp
|
2019-08-13 01:12:29 +08:00
|
|
|
AMDGPUPrintfRuntimeBinding.cpp
|
2016-04-30 08:23:06 +08:00
|
|
|
GCNHazardRecognizer.cpp
|
2017-08-17 00:23:32 +08:00
|
|
|
GCNIterativeScheduler.cpp
|
|
|
|
GCNMinRegStrategy.cpp
|
|
|
|
GCNRegPressure.cpp
|
2016-08-30 03:42:52 +08:00
|
|
|
GCNSchedStrategy.cpp
|
2018-05-25 04:02:01 +08:00
|
|
|
R600AsmPrinter.cpp
|
2013-10-02 03:32:58 +08:00
|
|
|
R600ClauseMergePass.cpp
|
2013-04-02 06:05:58 +08:00
|
|
|
R600ControlFlowFinalizer.cpp
|
|
|
|
R600EmitClauseMarkers.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
R600ExpandSpecialInstrs.cpp
|
2016-06-24 14:30:11 +08:00
|
|
|
R600FrameLowering.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
R600InstrInfo.cpp
|
|
|
|
R600ISelLowering.cpp
|
|
|
|
R600MachineFunctionInfo.cpp
|
2013-03-06 02:54:05 +08:00
|
|
|
R600MachineScheduler.cpp
|
2018-05-13 18:04:48 +08:00
|
|
|
R600OpenCLImageTypeLoweringPass.cpp
|
2013-06-06 05:38:04 +08:00
|
|
|
R600OptimizeVectorRegisters.cpp
|
2013-04-30 08:14:27 +08:00
|
|
|
R600Packetizer.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
R600RegisterInfo.cpp
|
[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try
TFE and LWE support requires extra result registers that are written in the
event of a failure in order to detect that failure case.
The specific use-case that initiated these changes is sparse texture support.
This means that if image intrinsics are used with either option turned on, the
programmer must ensure that the return type can contain all of the expected
results. This can result in redundant registers since the vector size must be a
power-of-2.
This change takes roughly 6 parts:
1. Modify the instruction defs in tablegen to add new instruction variants that
can accomodate the extra return values.
2. Updates to lowerImage in SIISelLowering.cpp to accomodate setting TFE or LWE
(where the bulk of the work for these instruction types is now done)
3. Extra verification code to catch cases where intrinsics have been used but
insufficient return registers are used.
4. Modification to the adjustWritemask optimisation to account for TFE/LWE being
enabled (requires extra registers to be maintained for error return value).
5. An extra pass to zero initialize the error value return - this is because if
the error does not occur, the register is not written and thus must be zeroed
before use. Also added a new (on by default) option to ensure ALL return values
are zero-initialized that is required for sparse texture support.
6. Disable the inst_combine optimization in the presence of tfe/lwe (later TODO
for this to re-enable and handle correctly).
There's an additional fix now to avoid a dmask=0
For an image intrinsic with tfe where all result channels except tfe
were unused, I was getting an image instruction with dmask=0 and only a
single vgpr result for tfe. That is incorrect because the hardware
assumes there is at least one vgpr result, plus the one for tfe.
Fixed by forcing dmask to 1, which gives the desired two vgpr result
with tfe in the second one.
The TFE or LWE result is returned from the intrinsics using an aggregate
type. Look in the test code provided to see how this works, but in essence IR
code to invoke the intrinsic looks as follows:
%v = call {<4 x float>,i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15,
i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.vec = extractvalue {<4 x float>, i32} %v, 0
%v.err = extractvalue {<4 x float>, i32} %v, 1
This re-submit of the change also includes a slight modification in
SIISelLowering.cpp to work-around a compiler bug for the powerpc_le
platform that caused a buildbot failure on a previous submission.
Differential revision: https://reviews.llvm.org/D48826
Change-Id: If222bc03642e76cf98059a6bef5d5bffeda38dda
Work around for ppcle compiler bug
Change-Id: Ie284cf24b2271215be1b9dc95b485fd15000e32b
llvm-svn: 351054
2019-01-14 19:55:24 +08:00
|
|
|
SIAddIMGInit.cpp
|
2012-12-20 06:10:31 +08:00
|
|
|
SIAnnotateControlFlow.cpp
|
2013-08-07 07:12:34 +08:00
|
|
|
SIFixSGPRCopies.cpp
|
2018-11-16 09:13:34 +08:00
|
|
|
SIFixupVectorISel.cpp
|
2017-01-25 01:46:17 +08:00
|
|
|
SIFixVGPRCopies.cpp
|
2019-04-01 23:19:52 +08:00
|
|
|
SIPreAllocateWWMRegs.cpp
|
2014-11-22 06:06:37 +08:00
|
|
|
SIFoldOperands.cpp
|
2018-06-01 04:13:51 +08:00
|
|
|
SIFormMemoryClauses.cpp
|
2015-11-07 02:17:45 +08:00
|
|
|
SIFrameLowering.cpp
|
2016-08-23 03:33:16 +08:00
|
|
|
SIInsertSkips.cpp
|
2017-04-12 11:25:12 +08:00
|
|
|
SIInsertWaitcnts.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
SIInstrInfo.cpp
|
|
|
|
SIISelLowering.cpp
|
2014-10-11 06:01:59 +08:00
|
|
|
SILoadStoreOptimizer.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
SILowerControlFlow.cpp
|
2014-04-30 23:31:33 +08:00
|
|
|
SILowerI1Copies.cpp
|
2019-07-04 07:32:29 +08:00
|
|
|
SILowerSGPRSpills.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
SIMachineFunctionInfo.cpp
|
2016-01-14 00:10:10 +08:00
|
|
|
SIMachineScheduler.cpp
|
2017-07-22 05:19:23 +08:00
|
|
|
SIMemoryLegalizer.cpp
|
2016-09-29 09:44:16 +08:00
|
|
|
SIOptimizeExecMasking.cpp
|
2017-08-02 07:14:32 +08:00
|
|
|
SIOptimizeExecMaskingPreRA.cpp
|
[ADMGPU] SDWA peephole optimization pass.
Summary:
First iteration of SDWA peephole.
This pass tries to combine several instruction into one SDWA instruction. E.g. it converts:
'''
V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
'''
Into:
'''
V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
'''
Pass structure:
1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.
2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''
3. Iterate over all potential instructions and check if they can be converted into SDWA.
4. Convert instructions to SDWA.
This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).
There are several ways this pass can be improved:
1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.
2. Introduce more SDWA patterns
3. Introduce mnemonics to limit when SDWA patterns should apply
Reviewers: vpykhtin, alex-t, arsenm, rampitec
Subscribers: wdng, nhaehnle, mgorny
Differential Revision: https://reviews.llvm.org/D30038
llvm-svn: 298365
2017-03-21 20:51:34 +08:00
|
|
|
SIPeepholeSDWA.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
SIRegisterInfo.cpp
|
2014-07-22 00:55:33 +08:00
|
|
|
SIShrinkInstructions.cpp
|
2016-03-22 04:28:33 +08:00
|
|
|
SIWholeQuadMode.cpp
|
2017-11-20 22:35:53 +08:00
|
|
|
GCNILPSched.cpp
|
2019-05-02 00:49:31 +08:00
|
|
|
GCNRegBankReassign.cpp
|
2019-05-02 00:40:49 +08:00
|
|
|
GCNNSAReassign.cpp
|
2018-11-30 22:21:56 +08:00
|
|
|
GCNDPPCombine.cpp
|
2018-12-10 20:06:10 +08:00
|
|
|
SIModeRegister.cpp
|
2012-12-12 05:25:42 +08:00
|
|
|
)
|
|
|
|
|
2014-11-14 22:08:00 +08:00
|
|
|
add_subdirectory(AsmParser)
|
2016-02-18 11:42:32 +08:00
|
|
|
add_subdirectory(Disassembler)
|
2012-12-12 05:25:42 +08:00
|
|
|
add_subdirectory(MCTargetDesc)
|
2018-04-23 20:49:34 +08:00
|
|
|
add_subdirectory(TargetInfo)
|
2015-06-27 05:15:07 +08:00
|
|
|
add_subdirectory(Utils)
|