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llvm-project/llvm/test/CodeGen/RISCV/stack-realignment.ll

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[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
declare void @callee(i8*)
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller32() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller32:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -32
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 32
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi s0, sp, 32
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -32
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -32
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller32:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -32
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 32
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi s0, sp, 32
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -32
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -32
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 32
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign32() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign32:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 32
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller64() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller64:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -64
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 64
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi s0, sp, 64
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -64
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -64
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller64:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -64
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 64
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi s0, sp, 64
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -64
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -64
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 64
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign64() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 64
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller128() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller128:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -128
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 128
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi s0, sp, 128
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -128
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -128
; RV32I-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 128
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller128:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -128
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 128
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi s0, sp, 128
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -128
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -128
; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 128
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign128() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 128
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller256() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller256:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -256
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 256
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: sw ra, 252(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 248(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi s0, sp, 256
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -256
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -256
; RV32I-NEXT: lw s0, 248(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 252(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 256
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller256:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -256
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 256
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi s0, sp, 256
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -256
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -256
; RV64I-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 256
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 256
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign256() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign256:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign256:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 256
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller512() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller512:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -1024
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 1024
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: sw ra, 1020(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 1016(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi s0, sp, 1024
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -512
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi a0, sp, 512
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -1024
; RV32I-NEXT: lw s0, 1016(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 1020(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 1024
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller512:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -1024
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 1024
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: sd ra, 1016(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 1008(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi s0, sp, 1024
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -512
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi a0, sp, 512
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -1024
; RV64I-NEXT: ld s0, 1008(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 1016(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 1024
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 512
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign512() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign512:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign512:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 512
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller1024() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller1024:
; RV32I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, sp, -16
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -1024
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi a0, sp, 1024
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi sp, s0, -2048
; RV32I-NEXT: addi sp, sp, 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller1024:
; RV64I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, sp, -16
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -1024
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi a0, sp, 1024
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addi sp, s0, -2048
; RV64I-NEXT: addi sp, sp, 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 1024
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign1024() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign1024:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign1024:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 1024
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller2048() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller2048:
; RV32I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi a0, a0, -2032
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: sub sp, sp, a0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: andi sp, sp, -2048
; RV32I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi a0, a0, -2048
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: add a0, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: lui a0, 1
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: sub sp, s0, a0
; RV32I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: addi a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: add sp, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller2048:
; RV64I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addiw a0, a0, -2032
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: sub sp, sp, a0
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: andi sp, sp, -2048
; RV64I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addiw a0, a0, -2048
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: add a0, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: lui a0, 1
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: sub sp, s0, a0
; RV64I-NEXT: lui a0, 1
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: addiw a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: add sp, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 2048
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign2048() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign2048:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign2048:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 2048
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller4096() {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller4096:
; RV32I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: lui a0, 2
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: sub sp, sp, a0
; RV32I-NEXT: srli a0, sp, 12
; RV32I-NEXT: slli sp, a0, 12
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: lui a0, 1
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: add a0, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: lui a0, 2
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: sub sp, s0, a0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV32I-NEXT: lui a0, 2
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: add sp, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV32I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller4096:
; RV64I: # %bb.0:
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, -2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 2032
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 2016(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi s0, sp, 2032
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: lui a0, 2
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addiw a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: sub sp, sp, a0
; RV64I-NEXT: srli a0, sp, 12
; RV64I-NEXT: slli sp, a0, 12
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: lui a0, 1
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: add a0, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: lui a0, 2
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: sub sp, s0, a0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-10 00:49:05 +08:00
; RV64I-NEXT: lui a0, 2
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addiw a0, a0, -2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: add sp, sp, a0
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore We would like to split the SP adjustment to reduce the instructions in prologue and epilogue as the following case. In this way, the offset of the callee saved register could fit in a single store. add sp,sp,-2032 sw ra,2028(sp) sw s0,2024(sp) sw s1,2020(sp) sw s3,2012(sp) sw s4,2008(sp) add sp,sp,-64 Differential Revision: https://reviews.llvm.org/D68011 llvm-svn: 373688
2019-10-04 10:00:57 +08:00
; RV64I-NEXT: addi sp, sp, 2032
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: ret
%1 = alloca i8, align 4096
call void @callee(i8* %1)
ret void
}
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
define void @caller_no_realign4096() "no-realign-stack" {
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-LABEL: caller_no_realign4096:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV32I-NEXT: .cfi_offset ra, -4
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call callee@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller_no_realign4096:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_def_cfa_offset 16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV][NFC] Regenerate Calling Convention Tests This regenerates these tests using utils/update_llc_test_checks.py so that future changes in this area don't have the noise of lots of `@plt` lines being added. I also removed the `nounwind`s from the stack-realignment.ll test to increase coverage on the generated call frame information.
2021-01-15 06:32:17 +08:00
; RV64I-NEXT: .cfi_offset ra, -8
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: mv a0, sp
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call callee@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV] Minimal stack realignment support Summary: Currently the RISC-V backend does not realign the stack. This can be an issue even for the RV32I/RV64I ABIs (where the stack is 16-byte aligned), though is rare. It will be much more comment with RV32E (though the alignment requirements for common data types remain under-documented...). This patch adds minimal support for stack realignment. It should cope with large realignments. It will error out if the stack needs realignment and variable sized objects are present. It feels like a lot of the code like getFrameIndexReference and determineFrameLayout could be refactored somehow, as right now it feels fiddly and brittle. We also seem to allocate a lot more memory than GCC does for equivalent C code. Reviewers: asb Reviewed By: asb Subscribers: wwei, jrtc27, s.egerton, MaskRay, Jim, lenary, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62007 llvm-svn: 368300
2019-08-08 22:40:54 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = alloca i8, align 4096
call void @callee(i8* %1)
ret void
}