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llvm-project/llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll

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Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s
; The test cases check that we use the si versions of the conversions from
; double.
define i32 @fp64_to_ui32(double %a) nounwind {
; RV64I-LABEL: fp64_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
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; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: fp64_to_ui32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixunsdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = fptoui double %a to i32
ret i32 %conv
}
define i32 @fp64_to_si32(double %a) nounwind {
; RV64I-LABEL: fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: fp64_to_si32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = fptosi double %a to i32
ret i32 %conv
}
declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
; RV64I-LABEL: strict_fp64_to_ui32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixunsdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: strict_fp64_to_ui32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixunsdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv
}
define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
; RV64I-LABEL: struct_fp64_to_si32:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __fixdfsi@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IF-LABEL: struct_fp64_to_si32:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: call __fixdfsi@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC"" With new test file this time. Original message This new test covers both with and without the F extension enabled. This shows that the fptosi/fptoui for double->i32 use a different libcall depending on whether the F extension is enabled. If it's not enabled we use the 'si' library call. If it is enabled we use 'di'.
2020-11-05 11:55:52 +08:00
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
entry:
%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
ret i32 %conv
}