2020-05-15 14:44:23 +08:00
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \
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# RUN: %s -o - | FileCheck %s
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--- |
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define void @dont_outline_asm() #0 { ret void }
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define void @dont_outline_lr() #0 { ret void }
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define void @dont_outline_lr2() #0 { ret void }
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define void @dont_outline_it() #0 { ret void }
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define void @dont_outline_pic() #0 { ret void }
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define void @dont_outline_mve() #0 { ret void }
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declare void @z(i32, i32, i32, i32)
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attributes #0 = { minsize optsize }
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...
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---
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name: dont_outline_asm
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_asm
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; CHECK: bb.0:
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; CHECK: INLINEASM &"movs r0, #42", 1
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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; CHECK: bb.1:
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; CHECK: INLINEASM &"movs r0, #42", 1
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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bb.0:
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INLINEASM &"movs r0, #42", 1
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$r0, dead $cpsr = tMOVi8 1, 14, $noreg
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$r1, dead $cpsr = tMOVi8 1, 14, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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$r3, dead $cpsr = tMOVi8 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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INLINEASM &"movs r0, #42", 1
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$r0, dead $cpsr = tMOVi8 1, 14, $noreg
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$r1, dead $cpsr = tMOVi8 1, 14, $noreg
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$r2, dead $cpsr = tMOVi8 1, 14, $noreg
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$r3, dead $cpsr = tMOVi8 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_lr
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_lr
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $lr
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$r0 = tMOVr $lr, 14, $noreg
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$r1 = tMOVr $lr, 14, $noreg
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$r2 = tMOVr $lr, 14, $noreg
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$r3 = tMOVr $lr, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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liveins: $lr
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$r0 = tMOVr $lr, 14, $noreg
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$r1 = tMOVr $lr, 14, $noreg
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$r2 = tMOVr $lr, 14, $noreg
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$r3 = tMOVr $lr, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_lr2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_lr2
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $r0
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$lr = tMOVr $r0, 14, $noreg
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$r1 = tMOVr $r0, 14, $noreg
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$r2 = tMOVr $r0, 14, $noreg
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$r3 = tMOVr $r0, 14, $noreg
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$r4 = tMOVr $r0, 14, $noreg
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tBLXr 14, $lr, $noreg
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bb.1:
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liveins: $r0
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$lr = tMOVr $r0, 14, $noreg
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$r1 = tMOVr $r0, 14, $noreg
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$r2 = tMOVr $r0, 14, $noreg
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$r3 = tMOVr $r0, 14, $noreg
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$r4 = tMOVr $r0, 14, $noreg
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tBLXr 14, $lr, $noreg
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_it
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_it
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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t2IT 0, 1, implicit-def $itstate
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$r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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tBL 14, $noreg, @z
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bb.1:
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t2IT 0, 1, implicit-def $itstate
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$r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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$r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_pic
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_pic
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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$r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = PICADD $r0, 1, 14, $noreg
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$r1 = PICLDR $r0, 2, 14, $noreg
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PICSTR $r0, $r1, 3, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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$r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0
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$r0 = PICADD $r0, 1, 14, $noreg
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$r1 = PICLDR $r0, 2, 14, $noreg
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PICSTR $r0, $r1, 3, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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...
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---
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name: dont_outline_mve
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_outline_mve
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; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION
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bb.0:
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liveins: $r3, $r4, $q0, $q3, $q4, $q5
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$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5
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$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4
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$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0
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[ARM] Alter t2DoLoopStart to define lr
This changes the definition of t2DoLoopStart from
t2DoLoopStart rGPR
to
GPRlr = t2DoLoopStart rGPR
This will hopefully mean that low overhead loops are more tied together,
and we can more reliably generate loops without reverting or being at
the whims of the register allocator.
This is a fairly simple change in itself, but leads to a number of other
required alterations.
- The hardware loop pass, if UsePhi is set, now generates loops of the
form:
%start = llvm.start.loop.iterations(%N)
loop:
%p = phi [%start], [%dec]
%dec = llvm.loop.decrement.reg(%p, 1)
%c = icmp ne %dec, 0
br %c, loop, exit
- For this a new llvm.start.loop.iterations intrinsic was added, identical
to llvm.set.loop.iterations but produces a value as seen above, gluing
the loop together more through def-use chains.
- This new instrinsic conceptually produces the same output as input,
which is taught to SCEV so that the checks in MVETailPredication are not
affected.
- Some minor changes are needed to the ARMLowOverheadLoop pass, but it has
been left mostly as before. We should now more reliably be able to tell
that the t2DoLoopStart is correct without having to prove it, but
t2WhileLoopStart and tail-predicated loops will remain the same.
- And all the tests have been updated. There are a lot of them!
This patch on it's own might cause more trouble that it helps, with more
tail-predicated loops being reverted, but some additional patches can
hopefully improve upon that to get to something that is better overall.
Differential Revision: https://reviews.llvm.org/D89881
2020-11-10 23:57:58 +08:00
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$lr = t2DoLoopStart $r4
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2020-05-15 14:44:23 +08:00
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$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.1:
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liveins: $r3, $r4, $q0, $q3, $q4, $q5
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$q5 = MVE_VDUP32 $r3, 0, $noreg, $q5
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$q4 = MVE_VDUP32 $r4, 0, $noreg, $q4
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$q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0
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[ARM] Alter t2DoLoopStart to define lr
This changes the definition of t2DoLoopStart from
t2DoLoopStart rGPR
to
GPRlr = t2DoLoopStart rGPR
This will hopefully mean that low overhead loops are more tied together,
and we can more reliably generate loops without reverting or being at
the whims of the register allocator.
This is a fairly simple change in itself, but leads to a number of other
required alterations.
- The hardware loop pass, if UsePhi is set, now generates loops of the
form:
%start = llvm.start.loop.iterations(%N)
loop:
%p = phi [%start], [%dec]
%dec = llvm.loop.decrement.reg(%p, 1)
%c = icmp ne %dec, 0
br %c, loop, exit
- For this a new llvm.start.loop.iterations intrinsic was added, identical
to llvm.set.loop.iterations but produces a value as seen above, gluing
the loop together more through def-use chains.
- This new instrinsic conceptually produces the same output as input,
which is taught to SCEV so that the checks in MVETailPredication are not
affected.
- Some minor changes are needed to the ARMLowOverheadLoop pass, but it has
been left mostly as before. We should now more reliably be able to tell
that the t2DoLoopStart is correct without having to prove it, but
t2WhileLoopStart and tail-predicated loops will remain the same.
- And all the tests have been updated. There are a lot of them!
This patch on it's own might cause more trouble that it helps, with more
tail-predicated loops being reverted, but some additional patches can
hopefully improve upon that to get to something that is better overall.
Differential Revision: https://reviews.llvm.org/D89881
2020-11-10 23:57:58 +08:00
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$lr = t2DoLoopStart $r4
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2020-05-15 14:44:23 +08:00
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$r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg
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tBL 14, $noreg, @z
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bb.2:
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tBX_RET 14, $noreg
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