2017-02-14 08:33:36 +08:00
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//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
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2015-06-27 05:15:07 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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2017-03-27 22:04:01 +08:00
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#include "AMDGPU.h"
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2015-06-27 05:15:07 +08:00
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#include "AMDKernelCodeT.h"
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2016-12-10 08:39:12 +08:00
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#include "SIDefines.h"
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2017-02-14 08:33:36 +08:00
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#include "llvm/ADT/StringRef.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cstdint>
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2017-10-14 23:40:33 +08:00
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#include <string>
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2017-02-14 08:33:36 +08:00
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#include <utility>
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2016-12-10 08:39:12 +08:00
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2015-06-27 05:15:07 +08:00
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namespace llvm {
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2017-07-27 04:39:42 +08:00
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class Argument;
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2015-06-27 05:15:07 +08:00
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class FeatureBitset;
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2015-12-16 00:26:16 +08:00
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class Function;
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2015-12-03 01:00:42 +08:00
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class GlobalValue;
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2017-01-28 02:41:14 +08:00
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class MachineMemOperand;
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2015-09-26 05:41:28 +08:00
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class MCContext;
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2016-10-20 01:40:36 +08:00
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class MCRegisterClass;
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AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
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class MCRegisterInfo;
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2015-09-26 05:41:28 +08:00
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class MCSection;
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2015-12-22 02:44:27 +08:00
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class MCSubtargetInfo;
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2017-02-14 08:33:36 +08:00
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class Triple;
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2015-06-27 05:15:07 +08:00
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namespace AMDGPU {
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2017-02-08 22:05:23 +08:00
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namespace IsaInfo {
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2016-10-07 22:46:06 +08:00
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2017-02-08 22:05:23 +08:00
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enum {
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// The closed Vulkan driver sets 96, which limits the wave count to 8 but
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// doesn't spill SGPRs as much as when 80 is set.
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2018-05-17 04:47:48 +08:00
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FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
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TRAP_NUM_SGPRS = 16
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2017-02-08 22:05:23 +08:00
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};
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2018-05-01 23:54:18 +08:00
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/// Instruction set architecture version.
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2015-06-27 05:15:07 +08:00
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struct IsaVersion {
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unsigned Major;
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unsigned Minor;
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unsigned Stepping;
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};
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2017-02-08 22:05:23 +08:00
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/// \returns Isa version for given subtarget \p Features.
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2015-06-27 05:15:07 +08:00
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IsaVersion getIsaVersion(const FeatureBitset &Features);
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2017-02-08 22:05:23 +08:00
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2018-05-01 23:54:18 +08:00
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/// Streams isa version string for given subtarget \p STI into \p Stream.
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2017-10-14 23:40:33 +08:00
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void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
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2018-06-13 02:02:46 +08:00
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/// \returns True if given subtarget \p STI supports code object version 3,
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2017-10-14 23:59:07 +08:00
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/// false otherwise.
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2018-06-13 02:02:46 +08:00
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bool hasCodeObjectV3(const MCSubtargetInfo *STI);
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2017-10-14 23:59:07 +08:00
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2017-02-08 22:05:23 +08:00
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/// \returns Wavefront size for given subtarget \p Features.
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unsigned getWavefrontSize(const FeatureBitset &Features);
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/// \returns Local memory size in bytes for given subtarget \p Features.
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unsigned getLocalMemorySize(const FeatureBitset &Features);
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/// \returns Number of execution units per compute unit for given subtarget \p
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/// Features.
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unsigned getEUsPerCU(const FeatureBitset &Features);
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/// \returns Maximum number of work groups per compute unit for given subtarget
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/// \p Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Maximum number of waves per compute unit for given subtarget \p
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/// Features without any kind of limitation.
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unsigned getMaxWavesPerCU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per compute unit for given subtarget \p
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/// Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWavesPerCU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum number of waves per execution unit for given subtarget \p
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/// Features.
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unsigned getMinWavesPerEU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// Features without any kind of limitation.
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unsigned getMaxWavesPerEU(const FeatureBitset &Features);
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/// \returns Maximum number of waves per execution unit for given subtarget \p
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/// Features and limited by given \p FlatWorkGroupSize.
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unsigned getMaxWavesPerEU(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns Minimum flat work group size for given subtarget \p Features.
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unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
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/// \returns Maximum flat work group size for given subtarget \p Features.
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unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
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/// \returns Number of waves per work group for given subtarget \p Features and
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/// limited by given \p FlatWorkGroupSize.
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unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
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unsigned FlatWorkGroupSize);
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/// \returns SGPR allocation granularity for given subtarget \p Features.
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unsigned getSGPRAllocGranule(const FeatureBitset &Features);
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/// \returns SGPR encoding granularity for given subtarget \p Features.
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unsigned getSGPREncodingGranule(const FeatureBitset &Features);
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/// \returns Total number of SGPRs for given subtarget \p Features.
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unsigned getTotalNumSGPRs(const FeatureBitset &Features);
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/// \returns Addressable number of SGPRs for given subtarget \p Features.
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unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
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/// \returns Minimum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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/// \returns Maximum number of SGPRs that meets the given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
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bool Addressable);
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/// \returns VGPR allocation granularity for given subtarget \p Features.
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unsigned getVGPRAllocGranule(const FeatureBitset &Features);
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/// \returns VGPR encoding granularity for given subtarget \p Features.
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unsigned getVGPREncodingGranule(const FeatureBitset &Features);
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/// \returns Total number of VGPRs for given subtarget \p Features.
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unsigned getTotalNumVGPRs(const FeatureBitset &Features);
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/// \returns Addressable number of VGPRs for given subtarget \p Features.
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unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
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/// \returns Minimum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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/// \returns Maximum number of VGPRs that meets given number of waves per
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/// execution unit requirement for given subtarget \p Features.
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unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
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2017-02-14 08:33:36 +08:00
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} // end namespace IsaInfo
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2017-02-08 22:05:23 +08:00
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LLVM_READONLY
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int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
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2017-12-14 05:07:51 +08:00
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LLVM_READONLY
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int getMaskedMIMGOp(const MCInstrInfo &MII,
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unsigned Opc, unsigned NewChannels);
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2018-01-26 23:43:29 +08:00
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LLVM_READONLY
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int getMaskedMIMGAtomicOp(const MCInstrInfo &MII,
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unsigned Opc, unsigned NewChannels);
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2017-12-14 05:07:51 +08:00
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LLVM_READONLY
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int getMCOpcode(uint16_t Opcode, unsigned Gen);
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2015-06-27 05:58:31 +08:00
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features);
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2015-12-03 11:34:32 +08:00
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2017-11-02 03:12:38 +08:00
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bool isGroupSegment(const GlobalValue *GV);
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bool isGlobalSegment(const GlobalValue *GV);
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bool isReadOnlySegment(const GlobalValue *GV);
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2015-12-03 01:00:42 +08:00
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2016-10-21 02:12:38 +08:00
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/// \returns True if constants should be emitted to .text section for given
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/// target triple \p TT, false otherwise.
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bool shouldEmitConstantsToTextSection(const Triple &TT);
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2016-09-07 04:22:28 +08:00
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/// \returns Integer value requested using \p F's \p Name attribute.
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if requested value cannot be converted
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/// to integer.
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2016-05-12 10:45:18 +08:00
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int getIntegerAttribute(const Function &F, StringRef Name, int Default);
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2016-09-07 04:22:28 +08:00
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/// \returns A pair of integer values requested using \p F's \p Name attribute
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/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
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/// is false).
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///
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/// \returns \p Default if attribute is not present.
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///
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/// \returns \p Default and emits error if one of the requested values cannot be
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/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
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/// not present.
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std::pair<int, int> getIntegerPairAttribute(const Function &F,
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StringRef Name,
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std::pair<int, int> Default,
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bool OnlyFirstRequired = false);
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2016-10-12 02:58:22 +08:00
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/// \returns Vmcnt bit mask for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
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2016-10-01 01:01:40 +08:00
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2016-10-12 02:58:22 +08:00
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/// \returns Expcnt bit mask for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
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2016-10-01 01:01:40 +08:00
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2016-10-12 02:58:22 +08:00
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/// \returns Lgkmcnt bit mask for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
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/// \returns Waitcnt bit mask for given isa \p Version.
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unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
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2016-10-01 01:01:40 +08:00
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2016-10-12 02:58:22 +08:00
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/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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2016-10-01 01:01:40 +08:00
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2016-10-12 02:58:22 +08:00
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/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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2016-10-12 02:58:22 +08:00
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/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
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2016-10-12 02:58:22 +08:00
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2018-05-01 23:54:18 +08:00
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/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
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2016-10-12 02:58:22 +08:00
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/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
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/// \p Lgkmcnt respectively.
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///
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/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
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2017-02-19 02:29:53 +08:00
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/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
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/// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
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2016-10-12 02:58:22 +08:00
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/// \p Expcnt = \p Waitcnt[6:4]
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/// \p Lgkmcnt = \p Waitcnt[11:8]
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2017-02-08 22:05:23 +08:00
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void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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2016-10-12 02:58:22 +08:00
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unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
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/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Vmcnt);
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2016-10-12 02:58:22 +08:00
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/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Expcnt);
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2016-10-12 02:58:22 +08:00
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/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
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2017-02-08 22:05:23 +08:00
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unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
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unsigned Lgkmcnt);
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2016-10-12 02:58:22 +08:00
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2018-05-01 23:54:18 +08:00
|
|
|
/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
|
2016-10-12 02:58:22 +08:00
|
|
|
/// \p Version.
|
|
|
|
///
|
|
|
|
/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
|
2017-02-19 02:29:53 +08:00
|
|
|
/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
|
|
|
|
/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
|
|
|
|
/// Waitcnt[6:4] = \p Expcnt
|
|
|
|
/// Waitcnt[11:8] = \p Lgkmcnt
|
|
|
|
/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
|
2016-10-12 02:58:22 +08:00
|
|
|
///
|
|
|
|
/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
|
|
|
|
/// isa \p Version.
|
2017-02-08 22:05:23 +08:00
|
|
|
unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
|
2016-10-12 02:58:22 +08:00
|
|
|
unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
|
2016-10-01 01:01:40 +08:00
|
|
|
|
2016-01-13 19:45:36 +08:00
|
|
|
unsigned getInitialPSInputAddr(const Function &F);
|
|
|
|
|
2017-04-12 06:29:24 +08:00
|
|
|
LLVM_READNONE
|
|
|
|
bool isShader(CallingConv::ID CC);
|
|
|
|
|
|
|
|
LLVM_READNONE
|
|
|
|
bool isCompute(CallingConv::ID CC);
|
|
|
|
|
|
|
|
LLVM_READNONE
|
|
|
|
bool isEntryFunctionCC(CallingConv::ID CC);
|
|
|
|
|
2017-04-12 06:29:28 +08:00
|
|
|
// FIXME: Remove this when calling conventions cleaned up
|
|
|
|
LLVM_READNONE
|
|
|
|
inline bool isKernel(CallingConv::ID CC) {
|
|
|
|
switch (CC) {
|
|
|
|
case CallingConv::AMDGPU_KERNEL:
|
|
|
|
case CallingConv::SPIR_KERNEL:
|
|
|
|
return true;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2015-12-16 00:26:16 +08:00
|
|
|
|
2018-01-10 22:22:19 +08:00
|
|
|
bool hasXNACK(const MCSubtargetInfo &STI);
|
2018-02-05 20:45:43 +08:00
|
|
|
bool hasMIMG_R128(const MCSubtargetInfo &STI);
|
2018-02-05 22:18:53 +08:00
|
|
|
bool hasPackedD16(const MCSubtargetInfo &STI);
|
2018-02-05 20:45:43 +08:00
|
|
|
|
2015-12-22 02:44:27 +08:00
|
|
|
bool isSI(const MCSubtargetInfo &STI);
|
|
|
|
bool isCI(const MCSubtargetInfo &STI);
|
|
|
|
bool isVI(const MCSubtargetInfo &STI);
|
2017-05-23 18:08:55 +08:00
|
|
|
bool isGFX9(const MCSubtargetInfo &STI);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Is Reg - scalar register
|
2017-05-23 18:08:55 +08:00
|
|
|
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
|
2015-12-22 02:44:27 +08:00
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Is there any intersection between registers
|
2017-06-21 22:41:34 +08:00
|
|
|
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
|
|
|
|
|
2015-12-22 02:44:27 +08:00
|
|
|
/// If \p Reg is a pseudo reg, return the correct hardware register given
|
|
|
|
/// \p STI otherwise return \p Reg.
|
|
|
|
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Convert hardware register \p Reg to a pseudo register
|
2017-03-03 22:31:06 +08:00
|
|
|
LLVM_READNONE
|
|
|
|
unsigned mc2PseudoReg(unsigned Reg);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Can this operand also contain immediate values?
|
AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
|
|
|
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Is this floating-point operand?
|
AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
|
|
|
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Does this opearnd support only inlinable literals?
|
AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
|
|
|
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
2016-10-28 07:05:31 +08:00
|
|
|
unsigned getRegBitWidth(unsigned RCID);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Get the size in bits of a register from the register class \p RC.
|
2016-10-20 01:40:36 +08:00
|
|
|
unsigned getRegBitWidth(const MCRegisterClass &RC);
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Get size of register operand
|
AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
|
|
|
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
|
|
|
|
unsigned OpNo);
|
|
|
|
|
2016-12-10 08:39:12 +08:00
|
|
|
LLVM_READNONE
|
|
|
|
inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
|
|
|
|
switch (OpInfo.OperandType) {
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT32:
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_FP32:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT32:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP32:
|
|
|
|
return 4;
|
|
|
|
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT64:
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_FP64:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
|
|
|
|
return 8;
|
|
|
|
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_INT16:
|
|
|
|
case AMDGPU::OPERAND_REG_IMM_FP16:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_FP16:
|
2017-02-28 02:49:11 +08:00
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
|
|
|
|
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
|
2016-12-10 08:39:12 +08:00
|
|
|
return 2;
|
|
|
|
|
|
|
|
default:
|
|
|
|
llvm_unreachable("unhandled operand type");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
LLVM_READNONE
|
|
|
|
inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
|
|
|
|
return getOperandSize(Desc.OpInfo[OpNo]);
|
|
|
|
}
|
|
|
|
|
2018-05-01 23:54:18 +08:00
|
|
|
/// Is this literal inlinable
|
2016-12-06 06:26:17 +08:00
|
|
|
LLVM_READNONE
|
|
|
|
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
|
|
|
|
|
|
|
|
LLVM_READNONE
|
|
|
|
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
|
|
|
|
|
2016-12-10 08:39:12 +08:00
|
|
|
LLVM_READNONE
|
|
|
|
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
|
AMDGPU] Assembler: better support for immediate literals in assembler.
Summary:
Prevously assembler parsed all literals as either 32-bit integers or 32-bit floating-point values. Because of this we couldn't support f64 literals.
E.g. in instruction "v_fract_f64 v[0:1], 0.5", literal 0.5 was encoded as 32-bit literal 0x3f000000, which is incorrect and will be interpreted as 3.0517578125E-5 instead of 0.5. Correct encoding is inline constant 240 (optimal) or 32-bit literal 0x3FE00000 at least.
With this change the way immediate literals are parsed is changed. All literals are always parsed as 64-bit values either integer or floating-point. Then we convert parsed literals to correct form based on information about type of operand parsed (was literal floating or binary) and type of expected instruction operands (is this f32/64 or b32/64 instruction).
Here are rules how we convert literals:
- We parsed fp literal:
- Instruction expects 64-bit operand:
- If parsed literal is inlinable (e.g. v_fract_f64_e32 v[0:1], 0.5)
- then we do nothing this literal
- Else if literal is not-inlinable but instruction requires to inline it (e.g. this is e64 encoding, v_fract_f64_e64 v[0:1], 1.5)
- report error
- Else literal is not-inlinable but we can encode it as additional 32-bit literal constant
- If instruction expect fp operand type (f64)
- Check if low 32 bits of literal are zeroes (e.g. v_fract_f64 v[0:1], 1.5)
- If so then do nothing
- Else (e.g. v_fract_f64 v[0:1], 3.1415)
- report warning that low 32 bits will be set to zeroes and precision will be lost
- set low 32 bits of literal to zeroes
- Instruction expects integer operand type (e.g. s_mov_b64_e32 s[0:1], 1.5)
- report error as it is unclear how to encode this literal
- Instruction expects 32-bit operand:
- Convert parsed 64 bit fp literal to 32 bit fp. Allow lose of precision but not overflow or underflow
- Is this literal inlinable and are we required to inline literal (e.g. v_trunc_f32_e64 v0, 0.5)
- do nothing
- Else report error
- Do nothing. We can encode any other 32-bit fp literal (e.g. v_trunc_f32 v0, 10000000.0)
- Parsed binary literal:
- Is this literal inlinable (e.g. v_trunc_f32_e32 v0, 35)
- do nothing
- Else, are we required to inline this literal (e.g. v_trunc_f32_e64 v0, 35)
- report error
- Else, literal is not-inlinable and we are not required to inline it
- Are high 32 bit of literal zeroes or same as sign bit (32 bit)
- do nothing (e.g. v_trunc_f32 v0, 0xdeadbeef)
- Else
- report error (e.g. v_trunc_f32 v0, 0x123456789abcdef0)
For this change it is required that we know operand types of instruction (are they f32/64 or b32/64). I added several new register operands (they extend previous register operands) and set operand types to corresponding types:
'''
enum OperandType {
OPERAND_REG_IMM32_INT,
OPERAND_REG_IMM32_FP,
OPERAND_REG_INLINE_C_INT,
OPERAND_REG_INLINE_C_FP,
}
'''
This is not working yet:
- Several tests are failing
- Problems with predicate methods for inline immediates
- LLVM generated assembler parts try to select e64 encoding before e32.
More changes are required for several AsmOperands.
Reviewers: vpykhtin, tstellarAMD
Subscribers: arsenm, kzhuravl, artem.tamazov
Differential Revision: https://reviews.llvm.org/D22922
llvm-svn: 281050
2016-09-09 22:44:04 +08:00
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2017-02-28 02:49:11 +08:00
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LLVM_READNONE
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bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
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2017-07-27 04:39:42 +08:00
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bool isArgPassedInSGPR(const Argument *Arg);
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2017-01-28 02:41:14 +08:00
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/// \returns The encoding that will be used for \p ByteOffset in the SMRD
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/// offset field.
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int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
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/// \returns true if this offset is small enough to fit in the SMRD
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/// offset field. \p ByteOffset should be the offset in bytes and
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/// not the encoded offset.
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bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
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2018-03-05 23:12:21 +08:00
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/// \returns true if the intrinsic is divergent
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bool isIntrinsicSourceOfDivergence(unsigned IntrID);
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2015-06-27 05:15:07 +08:00
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} // end namespace AMDGPU
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} // end namespace llvm
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2017-02-14 08:33:36 +08:00
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#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
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