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llvm-project/llvm/test/MC/Mips/mips32r6/relocations.s

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[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 \
# RUN: | FileCheck %s -check-prefix=CHECK-FIXUP
# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips32r6 \
[llvm-readobj] Update tests because of changes in llvm-readobj behavior This patch updates tests using llvm-readobj and llvm-readelf, because soon reading from stdin will be achievable only via a '-' as described here: https://bugs.llvm.org/show_bug.cgi?id=46400. Patch with changes to llvm-readobj behavior is here: https://reviews.llvm.org/D83704 Differential Revision: https://reviews.llvm.org/D83912 Reviewed by: jhenderson, MaskRay, grimar
2020-07-20 15:39:14 +08:00
# RUN: | llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-ELF
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
#------------------------------------------------------------------------------
# Check that the assembler can handle the documented syntax for fixups.
#------------------------------------------------------------------------------
[mips][microMIPS] add lapc instruction Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
2017-09-12 02:34:04 +08:00
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: bnec $5, $6, bar # encoding: [0x60,0xa6,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_Mips_PC16
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: bnezc $9, bar # encoding: [0xf9,0b001AAAAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC21_S2
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: balc bar # encoding: [0b111010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-FIXUP: bc bar # encoding: [0b110010AA,A,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips64] Emit correct addend for some PC-relative relocations So far, LLVM has not emitted correct addend for N64 and N32 ABI. This patch fixes that. It also removes fixup from MCJIT for R_MIPS_PC16 relocation. Patch by Vladimir Radosavljevic. Differential Revision: http://reviews.llvm.org/D10565 llvm-svn: 240404
2015-06-23 21:54:42 +08:00
# CHECK-FIXUP: value: bar-4, kind: fixup_MIPS_PC26_S2
[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
2014-05-27 22:58:51 +08:00
# CHECK-FIXUP: aluipc $2, %pcrel_hi(bar) # encoding: [0xec,0x5f,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations. Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
2016-05-03 21:35:44 +08:00
# CHECK-FIXUP: value: %pcrel_hi(bar),
[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
2014-05-27 22:58:51 +08:00
# CHECK-FIXUP: kind: fixup_MIPS_PCHI16
# CHECK-FIXUP: addiu $2, $2, %pcrel_lo(bar) # encoding: [0x24,0x42,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
[mips] Use MipsMCExpr instead of MCSymbolRefExpr for all relocations. Summary: This is much closer to the way MIPS relocation expressions work (%hi(foo + 2) rather than %hi(foo) + 2) and removes the need for the various bodges in MipsAsmParser::evaluateRelocExpr(). Removing those bodges ensures that the constant stored in MCValue is the full 32 or 64-bit (depending on ABI) offset from the symbol. This will be used to correct the %hi/%lo matching needed to sort the relocation table correctly. As part of this: * Gave MCExpr::print() the ability to omit parenthesis when emitting a symbol reference inside a MipsMCExpr operator like %hi(X). Without this we print things like %lo(($L1)). * %hi(%neg(%gprel(X))) is now three MipsMCExpr's instead of one. Most of the related special cases have been removed or moved to MipsMCExpr. We can remove the rest as we gain support for the less common relocations when they are not part of this specific combination. * Renamed MipsMCExpr::VariantKind and the enum prefix ('VK_') to avoid confusion with MCSymbolRefExpr::VariantKind and its prefix (also 'VK_'). * fixup_Mips_GOT_Local and fixup_Mips_GOT_Global were found to be identical and merged into fixup_Mips_GOT. * MO_GOT16 and MO_GOT turned out to be identical and have been merged into MO_GOT. * VK_Mips_GOT and VK_Mips_GOT16 turned out to be the same thing so they have been merged into MEK_GOT Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19716 llvm-svn: 268379
2016-05-03 21:35:44 +08:00
# CHECK-FIXUP: value: %pcrel_lo(bar),
[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
2014-05-27 22:58:51 +08:00
# CHECK-FIXUP: kind: fixup_MIPS_PCLO16
[mips][microMIPS] add lapc instruction Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
2017-09-12 02:34:04 +08:00
# CHECK-FIXUP: lapc $2, bar # encoding: [0xec,0b01000AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
[mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions llvm-svn: 373591
2019-10-03 20:08:26 +08:00
# CHECK-FIXUP: jialc $5, bar # encoding: [0xf8,0x05,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_LO16
# CHECK-FIXUP: jic $5, bar # encoding: [0xd8,0x05,A,A]
# CHECK-FIXUP: # fixup A - offset: 0,
# CHECK-FIXUP: value: bar, kind: fixup_Mips_LO16
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
#------------------------------------------------------------------------------
# Check that the appropriate relocations were created.
#------------------------------------------------------------------------------
# CHECK-ELF: Relocations [
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-ELF: 0x0 R_MIPS_PC19_S2 bar 0x0
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-ELF: 0x4 R_MIPS_PC16 bar 0x0
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-ELF: 0x8 R_MIPS_PC16 bar 0x0
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-ELF: 0xC R_MIPS_PC21_S2 bar 0x0
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-ELF: 0x10 R_MIPS_PC21_S2 bar 0x0
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-ELF: 0x14 R_MIPS_PC26_S2 bar 0x0
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
# CHECK-ELF: 0x18 R_MIPS_PC26_S2 bar 0x0
# CHECK-ELF: 0x1C R_MIPS_PCHI16 bar 0x0
# CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
# CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
# CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
[mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions llvm-svn: 373591
2019-10-03 20:08:26 +08:00
# CHECK-ELF: 0x2C R_MIPS_LO16 bar 0x0
# CHECK-ELF: 0x30 R_MIPS_LO16 bar 0x0
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
# CHECK-ELF: ]
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
addiupc $2,bar
[mips][mips64r6] Add relocations R_MIPS_PC21_S2, R_MIPS_PC26_S2 Differential Revision: http://reviews.llvm.org/D3824 llvm-svn: 209655
2014-05-27 20:55:40 +08:00
beqc $5, $6, bar
bnec $5, $6, bar
beqzc $9, bar
bnezc $9, bar
balc bar
bc bar
[mips][mips64r6] Add Relocations R_MIPS_PCHI16, R_MIPS_PCLO16 Differential Revision: http://reviews.llvm.org/D3860 llvm-svn: 209659
2014-05-27 22:58:51 +08:00
aluipc $2, %pcrel_hi(bar)
addiu $2, $2, %pcrel_lo(bar)
[mips][microMIPS] add lapc instruction Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
2017-09-12 02:34:04 +08:00
lapc $2,bar
[mips][mips64r6] Add R_MIPS_PC19_S2 Differential Revision: http://reviews.llvm.org/D3866 llvm-svn: 210773
2014-06-12 20:40:00 +08:00
lwpc $2,bar
[mips] Push `fixup_Mips_LO16` fixup for `jialc` and `jic` instructions llvm-svn: 373591
2019-10-03 20:08:26 +08:00
jialc $5, bar
jic $5, bar