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llvm-project/llvm/test/MC/Mips/mips-cop0-reginfo.s

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[mips] Use llvm-mc -triple option instead of combination of arch,target-abi,mcpu. NFC llvm-svn: 348914
2018-12-12 15:03:04 +08:00
# RUN: llvm-mc -triple mips-unknown-linux-gnu -mcpu=mips32r2 -filetype=obj %s -o - \
[llvm-readobj] Change -long-option to --long-option in tests. NFC We use both -long-option and --long-option in tests. Switch to --long-option for consistency. In the "llvm-readelf" mode, -long-option is discouraged as it conflicts with grouped short options and it is not accepted by GNU readelf. While updating the tests, change llvm-readobj -s to llvm-readobj -S to reduce confusion ("s" is --section-headers in llvm-readobj but --symbols in llvm-readelf). llvm-svn: 359649
2019-05-01 13:27:20 +08:00
# RUN: | llvm-readobj --sections --section-data - | FileCheck %s
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
mfc0 $16, $15, 1
mfc0 $16, $16, 1
# Checking for the coprocessor 0's register usage was recorded
# and emitted.
# CHECK: Section {
# CHECK: Index: 5
# CHECK: Name: .reginfo (27)
# CHECK: Type: SHT_MIPS_REGINFO (0x70000006)
# CHECK: Flags [ (0x2)
# CHECK: SHF_ALLOC (0x2)
# CHECK: ]
# CHECK: Address: 0x0
# CHECK: Offset: 0x50
# CHECK: Size: 24
# CHECK: Link: 0
# CHECK: Info: 0
# CHECK: AddressAlignment: 4
# CHECK: EntrySize: 24
# CHECK: SectionData (
# CHECK: 0000: 00010000 00018000 00000000 00000000 |................|
# CHECK: 0010: 00000000 00000000 |........|
# CHECK: )
# CHECK: }