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llvm-project/llvm/test/MC/Mips/mips-control-instructions.s

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[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32r2 -show-inst| \
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# RUN: FileCheck -check-prefix=CHECK32 %s
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64r2 -show-inst \
This patch implements trap instructions for mips. The test cases are added. llvm-svn: 189213
2013-08-26 18:02:40 +08:00
# RUN: | FileCheck -check-prefix=CHECK64 %s
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} BREAK
TableGen: use PrintMethods to print more aliases llvm-svn: 208607
2014-05-13 02:04:06 +08:00
# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d]
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK32: eret # encoding: [0x42,0x00,0x00,0x18]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} ERET
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK32: deret # encoding: [0x42,0x00,0x00,0x1f]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DERET
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK32: di # encoding: [0x41,0x60,0x60,0x00]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} DI
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK32: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK32: ei # encoding: [0x41,0x60,0x60,0x20]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} EI
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK32: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
This patch implements wait instruction for mips. Examples are added in test files. llvm-svn: 188537
2013-08-16 18:17:03 +08:00
# CHECK32: wait # encoding: [0x42,0x00,0x00,0x20]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK32-NEXT: # <MCInst #{{[0-9]+}} WAIT
This patch implements trap instructions for mips. The test cases are added. llvm-svn: 189213
2013-08-26 18:02:40 +08:00
# CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
# CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
# CHECK32: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
# CHECK32: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
# CHECK32: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
# CHECK32: tgei $3, 3 # encoding: [0x04,0x68,0x00,0x03]
# CHECK32: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
# CHECK32: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
# CHECK32: tgeiu $3, 7 # encoding: [0x04,0x69,0x00,0x07]
# CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
# CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
# CHECK32: tlti $3, 31 # encoding: [0x04,0x6a,0x00,0x1f]
# CHECK32: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
# CHECK32: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3]
# CHECK32: tltiu $3, 255 # encoding: [0x04,0x6b,0x00,0xff]
# CHECK32: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
# CHECK32: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
# CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} BREAK
TableGen: use PrintMethods to print more aliases llvm-svn: 208607
2014-05-13 02:04:06 +08:00
# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d]
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK64: eret # encoding: [0x42,0x00,0x00,0x18]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} ERET
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
# CHECK64: deret # encoding: [0x42,0x00,0x00,0x1f]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DERET
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK64: di # encoding: [0x41,0x60,0x60,0x00]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} DI
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK64: di $10 # encoding: [0x41,0x6a,0x60,0x00]
# CHECK64: ei # encoding: [0x41,0x60,0x60,0x20]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} EI
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
# CHECK64: ei $10 # encoding: [0x41,0x6a,0x60,0x20]
This patch implements wait instruction for mips. Examples are added in test files. llvm-svn: 188537
2013-08-16 18:17:03 +08:00
# CHECK64: wait # encoding: [0x42,0x00,0x00,0x20]
[mips] Correct the definitions of some control instructions Correct the definitions of ei, di, eret, deret, wait, syscall and break. Also provide microMIPS specific aliases to match the MIPS aliases. Additionally correct the definition of the wait instruction so that it is present in the instruction mapping tables. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D45939 llvm-svn: 330952
2018-04-27 00:06:34 +08:00
# CHECK64-NEXT: # <MCInst #{{[0-9]+}} WAIT
This patch implements trap instructions for mips. The test cases are added. llvm-svn: 189213
2013-08-26 18:02:40 +08:00
# CHECK64: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
# CHECK64: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
# CHECK64: teqi $3, 1 # encoding: [0x04,0x6c,0x00,0x01]
# CHECK64: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
# CHECK64: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
# CHECK64: tgei $3, 3 # encoding: [0x04,0x68,0x00,0x03]
# CHECK64: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
# CHECK64: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
# CHECK64: tgeiu $3, 7 # encoding: [0x04,0x69,0x00,0x07]
# CHECK64: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
# CHECK64: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
# CHECK64: tlti $3, 31 # encoding: [0x04,0x6a,0x00,0x1f]
# CHECK64: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
# CHECK64: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3]
# CHECK64: tltiu $3, 255 # encoding: [0x04,0x6b,0x00,0xff]
# CHECK64: tne $zero, $3 # encoding: [0x00,0x03,0x00,0x36]
# CHECK64: tne $zero, $3, 1023 # encoding: [0x00,0x03,0xff,0xf6]
# CHECK64: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
Implement eret and deret(return from exception) instructions for Mips. Test examples are given. llvm-svn: 186507
2013-07-17 22:05:19 +08:00
break
break 7
break 7,5
eret
deret
This patch implements ei and di instructions for mips. Test cases are added. llvm-svn: 188176
2013-08-12 21:07:23 +08:00
di
di $0
di $10
ei
ei $0
ei $10
This patch implements wait instruction for mips. Examples are added in test files. llvm-svn: 188537
2013-08-16 18:17:03 +08:00
wait
This patch implements trap instructions for mips. The test cases are added. llvm-svn: 189213
2013-08-26 18:02:40 +08:00
teq $0,$3
teq $0,$3,1
teqi $3,1
tge $0,$3
tge $0,$3,3
tgei $3,3
tgeu $0,$3
tgeu $0,$3,7
tgeiu $3,7
tlt $0,$3
tlt $0,$3,31
tlti $3,31
tltu $0,$3
tltu $0,$3,255
tltiu $3,255
tne $0,$3
tne $0,$3,1023
tnei $3,1023