2014-09-10 04:07:07 +08:00
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//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for AMD btver2 (Jaguar) to support
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// instruction scheduling and other instruction cost heuristics. Based off AMD Software
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// Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
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//
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//===----------------------------------------------------------------------===//
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def BtVer2Model : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and btver2 can
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// decode 2 instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 64; // Retire Control Unit
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let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
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let HighLatency = 25;
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let MispredictPenalty = 14; // Minimum branch misdirection penalty
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let PostRAScheduler = 1;
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2017-12-13 00:12:53 +08:00
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// FIXME: SSE4/AVX is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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2014-09-10 04:07:07 +08:00
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}
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let SchedModel = BtVer2Model in {
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// Jaguar can issue up to 6 micro-ops in one cycle
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def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
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def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
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def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
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def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
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def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
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def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
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[MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca
This patch allows the description of register files in processor scheduling
models. This addresses PR36662.
A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.
Targets can optionally describe register files for their processors using that
class. In particular, class RegisterFile allows to specify:
- The total number of physical registers.
- Which target registers are accessible through the register file.
- The cost of allocating a register at register renaming stage.
Example (from this patch - see file X86/X86ScheduleBtVer2.td)
def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>
Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar
(btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM
register definitions only cost 1 physical register.
The syntax allows to specify an empty set of register classes. An empty set of
register classes means: this register file models all the registers specified by
the Target. For each register class, users can specify an optional register
cost. By default, register costs default to 1. A value of 0 for the number of
physical registers means: "this register file has an unbounded number of
physical registers".
This patch is structured in two parts.
* Part 1 - MC/Tablegen *
A first part adds the tablegen definition of RegisterFile, and teaches the
SubtargetEmitter how to emit information related to register files.
Information about register files is accessible through an instance of
MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description
which is only used by external tools (like llvm-mca) from the processor
information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra
processor information if they don't want it.
* Part 2 - llvm-mca related *
The second part of this patch is related to changes to llvm-mca.
The main differences are:
1) class RegisterFile now needs to take into account the "cost of a register"
when allocating physical registers at register renaming stage.
2) Point 1. triggered a minor refactoring which lef to the removal of the
"maximum 32 register files" restriction.
3) The BackendStatistics view has been updated so that we can print out extra
details related to each register file implemented by the processor.
The effect of point 3. is also visible in tests register-files-[1..5].s.
Differential Revision: https://reviews.llvm.org/D44980
llvm-svn: 329067
2018-04-03 21:36:24 +08:00
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// The Integer PRF for Jaguar is 64 entries, and it holds the architectural and
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// speculative version of the 64-bit integer registers.
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// Reference: www.realworldtech.com/jaguar/4/
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[llvm-mca][BtVer2] teach how to identify false dependencies on partially written
registers.
The goal of this patch is to improve the throughput analysis in llvm-mca for the
case where instructions perform partial register writes.
On x86, partial register writes are quite difficult to model, mainly because
different processors tend to implement different register merging schemes in
hardware.
When the code contains partial register writes, the IPC (instructions per
cycles) estimated by llvm-mca tends to diverge quite significantly from the
observed IPC (using perf).
Modern AMD processors (at least, from Bulldozer onwards) don't rename partial
registers. Quoting Agner Fog's microarchitecture.pdf:
" The processor always keeps the different parts of an integer register together.
For example, AL and AH are not treated as independent by the out-of-order
execution mechanism. An instruction that writes to part of a register will
therefore have a false dependence on any previous write to the same register or
any part of it."
This patch is a first important step towards improving the analysis of partial
register updates. It changes the semantic of RegisterFile descriptors in
tablegen, and teaches llvm-mca how to identify false dependences in the presence
of partial register writes (for more details: see the new code comments in
include/Target/TargetSchedule.h - class RegisterFile).
This patch doesn't address the case where a write to a part of a register is
followed by a read from the whole register. On Intel chips, high8 registers
(AH/BH/CH/DH)) can be stored in separate physical registers. However, a later
(dirty) read of the full register (example: AX/EAX) triggers a merge uOp, which
adds extra latency (and potentially affects the pipe usage).
This is a very interesting article on the subject with a very informative answer
from Peter Cordes:
https://stackoverflow.com/questions/45660139/how-exactly-do-partial-registers-on-haswell-skylake-perform-writing-al-seems-to
In future, the definition of RegisterFile can be extended with extra information
that may be used to identify delays caused by merge opcodes triggered by a dirty
read of a partial write.
Differential Revision: https://reviews.llvm.org/D49196
llvm-svn: 337123
2018-07-15 19:01:38 +08:00
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//
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// The processor always keeps the different parts of an integer register
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// together. An instruction that writes to a part of a register will therefore
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// have a false dependence on any previous write to the same register or any
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// part of it.
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// Reference: Section 21.10 "AMD Bobcat and Jaguar pipeline: Partial register
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// access" - Agner Fog's "microarchitecture.pdf".
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def JIntegerPRF : RegisterFile<64, [GR64, CCR]>;
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[MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca
This patch allows the description of register files in processor scheduling
models. This addresses PR36662.
A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.
Targets can optionally describe register files for their processors using that
class. In particular, class RegisterFile allows to specify:
- The total number of physical registers.
- Which target registers are accessible through the register file.
- The cost of allocating a register at register renaming stage.
Example (from this patch - see file X86/X86ScheduleBtVer2.td)
def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>
Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar
(btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM
register definitions only cost 1 physical register.
The syntax allows to specify an empty set of register classes. An empty set of
register classes means: this register file models all the registers specified by
the Target. For each register class, users can specify an optional register
cost. By default, register costs default to 1. A value of 0 for the number of
physical registers means: "this register file has an unbounded number of
physical registers".
This patch is structured in two parts.
* Part 1 - MC/Tablegen *
A first part adds the tablegen definition of RegisterFile, and teaches the
SubtargetEmitter how to emit information related to register files.
Information about register files is accessible through an instance of
MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description
which is only used by external tools (like llvm-mca) from the processor
information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra
processor information if they don't want it.
* Part 2 - llvm-mca related *
The second part of this patch is related to changes to llvm-mca.
The main differences are:
1) class RegisterFile now needs to take into account the "cost of a register"
when allocating physical registers at register renaming stage.
2) Point 1. triggered a minor refactoring which lef to the removal of the
"maximum 32 register files" restriction.
3) The BackendStatistics view has been updated so that we can print out extra
details related to each register file implemented by the processor.
The effect of point 3. is also visible in tests register-files-[1..5].s.
Differential Revision: https://reviews.llvm.org/D44980
llvm-svn: 329067
2018-04-03 21:36:24 +08:00
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// The Jaguar FP Retire Queue renames SIMD and FP uOps onto a pool of 72 SSE
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// registers. Operations on 256-bit data types are cracked into two COPs.
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// Reference: www.realworldtech.com/jaguar/4/
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2018-05-22 00:30:26 +08:00
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def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>;
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[MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca
This patch allows the description of register files in processor scheduling
models. This addresses PR36662.
A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.
Targets can optionally describe register files for their processors using that
class. In particular, class RegisterFile allows to specify:
- The total number of physical registers.
- Which target registers are accessible through the register file.
- The cost of allocating a register at register renaming stage.
Example (from this patch - see file X86/X86ScheduleBtVer2.td)
def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>
Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar
(btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM
register definitions only cost 1 physical register.
The syntax allows to specify an empty set of register classes. An empty set of
register classes means: this register file models all the registers specified by
the Target. For each register class, users can specify an optional register
cost. By default, register costs default to 1. A value of 0 for the number of
physical registers means: "this register file has an unbounded number of
physical registers".
This patch is structured in two parts.
* Part 1 - MC/Tablegen *
A first part adds the tablegen definition of RegisterFile, and teaches the
SubtargetEmitter how to emit information related to register files.
Information about register files is accessible through an instance of
MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description
which is only used by external tools (like llvm-mca) from the processor
information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra
processor information if they don't want it.
* Part 2 - llvm-mca related *
The second part of this patch is related to changes to llvm-mca.
The main differences are:
1) class RegisterFile now needs to take into account the "cost of a register"
when allocating physical registers at register renaming stage.
2) Point 1. triggered a minor refactoring which lef to the removal of the
"maximum 32 register files" restriction.
3) The BackendStatistics view has been updated so that we can print out extra
details related to each register file implemented by the processor.
The effect of point 3. is also visible in tests register-files-[1..5].s.
Differential Revision: https://reviews.llvm.org/D44980
llvm-svn: 329067
2018-04-03 21:36:24 +08:00
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2018-04-05 23:41:41 +08:00
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// The retire control unit (RCU) can track up to 64 macro-ops in-flight. It can
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// retire up to two macro-ops per cycle.
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// Reference: "Software Optimization Guide for AMD Family 16h Processors"
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2018-05-22 00:30:26 +08:00
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def JRCU : RetireControlUnit<64, 2>;
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2018-04-05 23:41:41 +08:00
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2014-09-10 04:07:07 +08:00
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// Integer Pipe Scheduler
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def JALU01 : ProcResGroup<[JALU0, JALU1]> {
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let BufferSize=20;
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}
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// AGU Pipe Scheduler
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def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
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let BufferSize=12;
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}
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// Fpu Pipe Scheduler
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def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
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let BufferSize=18;
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}
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2018-03-18 20:09:17 +08:00
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// Functional units
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2014-09-10 04:07:07 +08:00
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def JDiv : ProcResource<1>; // integer division
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def JMul : ProcResource<1>; // integer multiplication
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def JVALU0 : ProcResource<1>; // vector integer
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def JVALU1 : ProcResource<1>; // vector integer
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def JVIMUL : ProcResource<1>; // vector integer multiplication
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def JSTC : ProcResource<1>; // vector store/convert
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def JFPM : ProcResource<1>; // FP multiplication
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def JFPA : ProcResource<1>; // FP addition
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2018-03-18 20:09:17 +08:00
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// Functional unit groups
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def JFPX : ProcResGroup<[JFPA, JFPM]>;
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def JVALU : ProcResGroup<[JVALU0, JVALU1]>;
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2014-09-10 04:07:07 +08:00
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// Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when dispatched by the schedulers.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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2018-03-16 07:46:12 +08:00
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list<ProcResourceKind> ExePorts,
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2018-05-03 14:08:47 +08:00
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int Lat, list<int> Res = [], int UOps = 1> {
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2014-09-10 04:07:07 +08:00
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// Register variant is using a single cycle on ExePort.
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2018-03-16 07:46:12 +08:00
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def : WriteRes<SchedRW, ExePorts> {
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2018-03-15 05:55:54 +08:00
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let Latency = Lat;
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2018-03-16 07:46:12 +08:00
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let ResourceCycles = Res;
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2018-03-15 05:55:54 +08:00
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let NumMicroOps = UOps;
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}
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2014-09-10 04:07:07 +08:00
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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2018-03-16 07:46:12 +08:00
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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2018-03-13 05:35:12 +08:00
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let Latency = !add(Lat, 3);
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2018-05-03 14:08:47 +08:00
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let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
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2018-03-15 05:55:54 +08:00
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let NumMicroOps = UOps;
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2014-09-10 04:07:07 +08:00
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}
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}
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multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
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2018-03-15 07:12:09 +08:00
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list<ProcResourceKind> ExePorts,
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2018-05-03 14:08:47 +08:00
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int Lat, list<int> Res = [], int UOps = 1> {
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2014-09-10 04:07:07 +08:00
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// Register variant is using a single cycle on ExePort.
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2018-03-15 07:12:09 +08:00
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def : WriteRes<SchedRW, ExePorts> {
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2018-03-13 00:02:56 +08:00
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let Latency = Lat;
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2018-03-15 07:12:09 +08:00
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let ResourceCycles = Res;
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2018-03-13 00:02:56 +08:00
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let NumMicroOps = UOps;
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}
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2014-09-10 04:07:07 +08:00
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// Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
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// latency.
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2018-03-15 07:12:09 +08:00
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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2018-03-13 05:35:12 +08:00
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let Latency = !add(Lat, 5);
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2018-05-03 14:08:47 +08:00
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let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
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2018-03-13 05:35:12 +08:00
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let NumMicroOps = UOps;
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2014-09-10 04:07:07 +08:00
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}
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}
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2018-04-27 23:50:33 +08:00
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multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
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list<ProcResourceKind> ExePorts,
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int Lat, list<int> Res = [2], int UOps = 2> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, ExePorts> {
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let Latency = Lat;
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let ResourceCycles = Res;
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let NumMicroOps = UOps;
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}
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// Memory variant also uses 2 cycles on JLAGU and adds 5 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
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let Latency = !add(Lat, 5);
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let ResourceCycles = !listconcat([2], Res);
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let NumMicroOps = UOps;
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}
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}
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2014-09-10 04:07:07 +08:00
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// A folded store needs a cycle on the SAGU for the store data.
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def : WriteRes<WriteRMW, [JSAGU]>;
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////////////////////////////////////////////////////////////////////////////////
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// Arithmetic.
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////////////////////////////////////////////////////////////////////////////////
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2018-05-08 21:51:45 +08:00
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defm : JWriteResIntPair<WriteALU, [JALU01], 1>;
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2018-05-17 23:43:23 +08:00
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defm : JWriteResIntPair<WriteADC, [JALU01], 1, [2]>;
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2018-05-08 21:51:45 +08:00
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defm : JWriteResIntPair<WriteIMul, [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32 multiplication
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2018-05-08 22:55:16 +08:00
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defm : JWriteResIntPair<WriteIMul64, [JALU1, JMul], 6, [1, 4], 2>; // i64 multiplication
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defm : X86WriteRes<WriteIMulH, [JALU1], 6, [4], 1>;
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2018-05-08 21:51:45 +08:00
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2018-08-01 02:24:24 +08:00
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defm : X86WriteRes<WriteBSWAP32, [JALU01], 1, [1], 1>;
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defm : X86WriteRes<WriteBSWAP64, [JALU01], 1, [1], 1>;
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2018-08-30 14:26:00 +08:00
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defm : X86WriteRes<WriteCMPXCHG,[JALU01], 1, [1], 1>;
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defm : X86WriteRes<WriteCMPXCHGRMW,[JALU01, JSAGU, JLAGU], 4, [1, 1, 1], 2>;
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2018-08-09 17:23:26 +08:00
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defm : X86WriteRes<WriteXCHG, [JALU01], 1, [1], 1>;
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2018-07-20 17:39:14 +08:00
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2018-05-08 21:51:45 +08:00
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defm : JWriteResIntPair<WriteDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
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defm : JWriteResIntPair<WriteDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
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defm : JWriteResIntPair<WriteDiv32, [JALU1, JDiv], 25, [1, 25], 2>;
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defm : JWriteResIntPair<WriteDiv64, [JALU1, JDiv], 41, [1, 41], 2>;
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defm : JWriteResIntPair<WriteIDiv8, [JALU1, JDiv], 12, [1, 12], 1>;
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defm : JWriteResIntPair<WriteIDiv16, [JALU1, JDiv], 17, [1, 17], 2>;
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defm : JWriteResIntPair<WriteIDiv32, [JALU1, JDiv], 25, [1, 25], 2>;
|
|
|
|
defm : JWriteResIntPair<WriteIDiv64, [JALU1, JDiv], 41, [1, 41], 2>;
|
|
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|
defm : JWriteResIntPair<WriteCRC32, [JALU01], 3, [4], 3>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-04-09 01:53:18 +08:00
|
|
|
defm : JWriteResIntPair<WriteCMOV, [JALU01], 1>; // Conditional move.
|
2018-05-18 00:47:30 +08:00
|
|
|
defm : JWriteResIntPair<WriteCMOV2, [JALU01], 1>; // Conditional (CF + ZF flag) move.
|
2018-05-13 02:07:07 +08:00
|
|
|
defm : X86WriteRes<WriteFCMOV, [JFPU0, JFPA], 3, [1,1], 1>; // x87 conditional move.
|
2018-04-09 01:53:18 +08:00
|
|
|
def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
|
|
|
|
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
|
2018-06-20 14:13:39 +08:00
|
|
|
def : WriteRes<WriteLAHFSAHF, [JALU01]>;
|
2018-08-01 18:24:27 +08:00
|
|
|
def : WriteRes<WriteBitTest,[JALU01]>;
|
2018-04-09 01:53:18 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
// This is for simple LEAs with one or two input operands.
|
|
|
|
def : WriteRes<WriteLEA, [JALU01]>;
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|
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|
2018-03-27 02:19:28 +08:00
|
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|
// Bit counts.
|
2018-07-08 17:50:25 +08:00
|
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|
defm : JWriteResIntPair<WriteBSF, [JALU01], 5, [4], 8>;
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|
defm : JWriteResIntPair<WriteBSR, [JALU01], 5, [4], 8>;
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|
defm : JWriteResIntPair<WritePOPCNT, [JALU01], 1>;
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|
defm : JWriteResIntPair<WriteLZCNT, [JALU01], 1>;
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|
defm : JWriteResIntPair<WriteTZCNT, [JALU01], 2, [2]>;
|
2018-03-16 21:43:55 +08:00
|
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|
2018-09-14 21:09:56 +08:00
|
|
|
// BMI1 BEXTR/BLS, BMI2 BZHI
|
2018-03-30 04:41:39 +08:00
|
|
|
defm : JWriteResIntPair<WriteBEXTR, [JALU01], 1>;
|
2018-09-14 21:31:14 +08:00
|
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|
defm : JWriteResIntPair<WriteBLS, [JALU01], 2, [2]>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteBZHI>;
|
2018-03-30 04:41:39 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Integer shifts and rotates.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
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|
|
2018-03-16 07:46:12 +08:00
|
|
|
defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-07-31 18:14:43 +08:00
|
|
|
// SHLD/SHRD.
|
|
|
|
defm : X86WriteRes<WriteSHDrri, [JALU01], 3, [6], 6>;
|
|
|
|
defm : X86WriteRes<WriteSHDrrcl,[JALU01], 4, [8], 7>;
|
|
|
|
defm : X86WriteRes<WriteSHDmri, [JLAGU, JALU01], 9, [1, 22], 8>;
|
|
|
|
defm : X86WriteRes<WriteSHDmrcl,[JLAGU, JALU01], 9, [1, 22], 8>;
|
2017-11-25 18:46:53 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Loads, stores, and moves, not folded with other operations.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-05-15 02:37:19 +08:00
|
|
|
def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
|
|
|
|
def : WriteRes<WriteStore, [JSAGU]>;
|
|
|
|
def : WriteRes<WriteStoreNT, [JSAGU]>;
|
|
|
|
def : WriteRes<WriteMove, [JALU01]>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-04-22 02:07:36 +08:00
|
|
|
// Load/store MXCSR.
|
|
|
|
// FIXME: These are copy and pasted from WriteLoad/Store.
|
|
|
|
def : WriteRes<WriteLDMXCSR, [JLAGU]> { let Latency = 5; }
|
|
|
|
def : WriteRes<WriteSTMXCSR, [JSAGU]>;
|
|
|
|
|
2017-12-10 19:51:29 +08:00
|
|
|
// Treat misc copies as a move.
|
|
|
|
def : InstRW<[WriteMove], (instrs COPY)>;
|
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Idioms that clear a register, like xorps %xmm0, %xmm0.
|
|
|
|
// These can often bypass execution ports completely.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
def : WriteRes<WriteZero, []>;
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Branches don't produce values, so they have no latency, but they still
|
|
|
|
// consume resources. Indirect branches can fold loads.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-16 07:46:12 +08:00
|
|
|
defm : JWriteResIntPair<WriteJump, [JALU01], 1>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-03-13 05:35:12 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Special case scheduling classes.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-15 23:12:12 +08:00
|
|
|
def : WriteRes<WriteSystem, [JALU01]> { let Latency = 100; }
|
|
|
|
def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
|
2018-03-13 05:35:12 +08:00
|
|
|
def : WriteRes<WriteFence, [JSAGU]>;
|
2018-04-20 21:12:04 +08:00
|
|
|
|
2018-03-19 22:26:50 +08:00
|
|
|
// Nops don't have dependencies, so there's no actual latency, but we set this
|
|
|
|
// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
|
|
|
|
def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
|
2018-03-13 05:35:12 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Floating point. This covers both scalar and vector operations.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-05-31 19:41:27 +08:00
|
|
|
defm : X86WriteRes<WriteFLD0, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFLD1, [JFPU1, JSTC], 3, [1,1], 1>;
|
[X86] Introduce WriteFLDC for x87 constant loads.
Summary:
{FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI} were using WriteMicrocoded.
- I've measured the values for Broadwell, Haswell, SandyBridge, Skylake.
- For ZnVer1 and Atom, values were transferred form InstRWs.
- For SLM and BtVer2, I've guessed some values :(
Reviewers: RKSimon, craig.topper, andreadb
Subscribers: gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47585
llvm-svn: 333656
2018-05-31 22:22:01 +08:00
|
|
|
defm : X86WriteRes<WriteFLDC, [JFPU1, JSTC], 3, [1,1], 1>;
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteFLoad, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
|
2018-05-11 22:30:54 +08:00
|
|
|
defm : X86WriteRes<WriteFLoadX, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFLoadY, [JLAGU, JFPU01, JFPX], 5, [1, 1, 1], 1>;
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteFMaskedLoad, [JLAGU, JFPU01, JFPX], 6, [1, 1, 2], 1>;
|
|
|
|
defm : X86WriteRes<WriteFMaskedLoadY, [JLAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;
|
|
|
|
|
2018-05-18 22:22:22 +08:00
|
|
|
defm : X86WriteRes<WriteFStore, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
|
2018-05-11 22:30:54 +08:00
|
|
|
defm : X86WriteRes<WriteFStoreX, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFStoreY, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
2018-05-15 02:37:19 +08:00
|
|
|
defm : X86WriteRes<WriteFStoreNT, [JSAGU, JFPU1, JSTC], 3, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFStoreNTX, [JSAGU, JFPU1, JSTC], 3, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFStoreNTY, [JSAGU, JFPU1, JSTC], 3, [2, 2, 2], 1>;
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteFMaskedStore, [JSAGU, JFPU01, JFPX], 6, [1, 1, 4], 1>;
|
|
|
|
defm : X86WriteRes<WriteFMaskedStoreY, [JSAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;
|
|
|
|
|
2018-05-12 01:38:36 +08:00
|
|
|
defm : X86WriteRes<WriteFMove, [JFPU01, JFPX], 1, [1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFMoveX, [JFPU01, JFPX], 1, [1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteFMoveY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
2018-05-11 22:30:54 +08:00
|
|
|
|
2018-05-12 01:38:36 +08:00
|
|
|
defm : X86WriteRes<WriteEMMS, [JFPU01, JFPX], 2, [1, 1], 1>;
|
2018-03-15 22:45:30 +08:00
|
|
|
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFAdd, [JFPU0, JFPA], 3>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFAddX, [JFPU0, JFPA], 3>;
|
2018-05-02 00:13:42 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFAddY, [JFPU0, JFPA], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFAddZ>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFAdd64, [JFPU0, JFPA], 3>;
|
|
|
|
defm : JWriteResFpuPair<WriteFAdd64X, [JFPU0, JFPA], 3>;
|
|
|
|
defm : JWriteResYMMPair<WriteFAdd64Y, [JFPU0, JFPA], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
|
2018-04-17 15:22:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFCmp, [JFPU0, JFPA], 2>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFCmpX, [JFPU0, JFPA], 2>;
|
2018-05-02 00:50:16 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFCmpY, [JFPU0, JFPA], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFCmpZ>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFCmp64, [JFPU0, JFPA], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteFCmp64X, [JFPU0, JFPA], 2>;
|
|
|
|
defm : JWriteResYMMPair<WriteFCmp64Y, [JFPU0, JFPA], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
|
2018-04-17 15:22:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFCom, [JFPU0, JFPA, JALU0], 3>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFMul, [JFPU1, JFPM], 2>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFMulX, [JFPU1, JFPM], 2>;
|
2018-05-02 02:22:53 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFMulY, [JFPU1, JFPM], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFMulZ>;
|
2018-05-08 04:52:53 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFMul64, [JFPU1, JFPM], 4, [1,2]>;
|
|
|
|
defm : JWriteResFpuPair<WriteFMul64X, [JFPU1, JFPM], 4, [1,2]>;
|
|
|
|
defm : JWriteResYMMPair<WriteFMul64Y, [JFPU1, JFPM], 4, [2,4], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFMul64Z>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFMA>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteFMAX>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteFMAY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFMAZ>;
|
2018-05-04 06:31:19 +08:00
|
|
|
defm : JWriteResFpuPair<WriteDPPD, [JFPU1, JFPM, JFPA], 9, [1, 3, 3], 3>;
|
|
|
|
defm : JWriteResFpuPair<WriteDPPS, [JFPU1, JFPM, JFPA], 11, [1, 3, 3], 5>;
|
|
|
|
defm : JWriteResYMMPair<WriteDPPSY, [JFPU1, JFPM, JFPA], 12, [2, 6, 6], 10>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteDPPSZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFRcp, [JFPU1, JFPM], 2>;
|
2018-05-07 19:50:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFRcpX, [JFPU1, JFPM], 2>;
|
2018-05-02 02:06:07 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFRcpY, [JFPU1, JFPM], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFRcpZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFRsqrt, [JFPU1, JFPM], 2>;
|
2018-05-07 19:50:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFRsqrtX, [JFPU1, JFPM], 2>;
|
2018-05-02 02:06:07 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFRsqrtY, [JFPU1, JFPM], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFDiv, [JFPU1, JFPM], 19, [1, 19]>;
|
2018-05-08 00:15:46 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFDivX, [JFPU1, JFPM], 19, [1, 19]>;
|
2018-05-02 02:22:53 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFDivY, [JFPU1, JFPM], 38, [2, 38], 2>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFDivZ>;
|
2018-05-08 00:15:46 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFDiv64, [JFPU1, JFPM], 19, [1, 19]>;
|
|
|
|
defm : JWriteResFpuPair<WriteFDiv64X, [JFPU1, JFPM], 19, [1, 19]>;
|
|
|
|
defm : JWriteResYMMPair<WriteFDiv64Y, [JFPU1, JFPM], 38, [2, 38], 2>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFSqrt, [JFPU1, JFPM], 21, [1, 21]>;
|
2018-05-07 19:50:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFSqrtX, [JFPU1, JFPM], 21, [1, 21]>;
|
2018-05-02 02:06:07 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFSqrtY, [JFPU1, JFPM], 42, [2, 42], 2>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
|
2018-05-07 19:50:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFSqrt64, [JFPU1, JFPM], 27, [1, 27]>;
|
|
|
|
defm : JWriteResFpuPair<WriteFSqrt64X, [JFPU1, JFPM], 27, [1, 27]>;
|
|
|
|
defm : JWriteResYMMPair<WriteFSqrt64Y, [JFPU1, JFPM], 54, [2, 54], 2>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
|
2018-05-07 19:50:44 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFSqrt80, [JFPU1, JFPM], 35, [1, 35]>;
|
2018-04-21 05:16:05 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFSign, [JFPU1, JFPM], 2>;
|
2018-05-04 20:59:24 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFRnd, [JFPU1, JSTC], 3>;
|
|
|
|
defm : JWriteResYMMPair<WriteFRndY, [JFPU1, JSTC], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFRndZ>;
|
2018-04-21 05:16:05 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFLogic, [JFPU01, JFPX], 1>;
|
2018-04-27 23:50:33 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFLogicY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFLogicZ>;
|
2018-05-08 18:28:03 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFTest, [JFPU0, JFPA, JALU0], 3>;
|
|
|
|
defm : JWriteResYMMPair<WriteFTestY , [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFTestZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFShuffle, [JFPU01, JFPX], 1>;
|
2018-05-01 22:25:01 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFShuffleY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
|
2018-04-11 21:49:19 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFVarShuffle, [JFPU01, JFPX], 2, [1, 4], 3>;
|
2018-04-28 02:19:48 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFVarShuffleY,[JFPU01, JFPX], 3, [2, 6], 6>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFBlend, [JFPU01, JFPX], 1>;
|
2018-04-28 02:19:48 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFBlendY, [JFPU01, JFPX], 1, [2, 2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFBlendZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFVarBlend, [JFPU01, JFPX], 2, [1, 4], 3>;
|
2018-04-28 02:19:48 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFVarBlendY, [JFPU01, JFPX], 3, [2, 6], 6>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
|
2018-08-31 16:30:47 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFShuffle256, [JFPU01, JFPX], 1, [2, 2], 2>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-03-13 05:35:12 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Conversions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-06-07 17:26:33 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCvtSS2I, [JFPU1, JSTC, JFPA, JALU0], 7, [1,1,1,1], 2>;
|
2018-05-16 18:53:45 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCvtPS2I, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtPS2IY, [JFPU1, JSTC], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
|
2018-06-07 17:26:33 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCvtSD2I, [JFPU1, JSTC, JFPA, JALU0], 7, [1,1,1,1], 2>;
|
2018-05-16 18:53:45 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCvtPD2I, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtPD2IY, [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
|
2018-05-16 18:53:45 +08:00
|
|
|
|
|
|
|
// FIXME: f+3 ST, LD+STC latency
|
|
|
|
defm : JWriteResFpuPair<WriteCvtI2SS, [JFPU1, JSTC], 9, [1,1], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtI2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtI2PSY, [JFPU1, JSTC], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
|
2018-05-16 18:53:45 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCvtI2SD, [JFPU1, JSTC], 9, [1,1], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtI2PD, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtI2PDY, [JFPU1, JSTC], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
|
2018-05-16 01:36:49 +08:00
|
|
|
|
|
|
|
defm : JWriteResFpuPair<WriteCvtSS2SD, [JFPU1, JSTC], 7, [1,2], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtPS2PD, [JFPU1, JSTC], 2, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtPS2PDY, [JFPU1, JSTC], 2, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
|
2018-05-16 01:36:49 +08:00
|
|
|
|
|
|
|
defm : JWriteResFpuPair<WriteCvtSD2SS, [JFPU1, JSTC], 7, [1,2], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteCvtPD2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtPD2PSY, [JFPU1, JSTC, JFPX], 6, [2,2,4], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
|
2018-05-15 22:12:32 +08:00
|
|
|
|
|
|
|
defm : JWriteResFpuPair<WriteCvtPH2PS, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : JWriteResYMMPair<WriteCvtPH2PSY, [JFPU1, JSTC], 3, [2,2], 2>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
|
2018-05-15 22:12:32 +08:00
|
|
|
|
|
|
|
defm : X86WriteRes<WriteCvtPS2PH, [JFPU1, JSTC], 3, [1,1], 1>;
|
|
|
|
defm : X86WriteRes<WriteCvtPS2PHY, [JFPU1, JSTC, JFPX], 6, [2,2,2], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
|
2018-05-15 22:12:32 +08:00
|
|
|
defm : X86WriteRes<WriteCvtPS2PHSt, [JFPU1, JSTC, JSAGU], 4, [1,1,1], 1>;
|
|
|
|
defm : X86WriteRes<WriteCvtPS2PHYSt, [JFPU1, JSTC, JFPX, JSAGU], 7, [2,2,2,1], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-03-13 00:02:56 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
2014-09-10 04:07:07 +08:00
|
|
|
// Vector integer operations.
|
2018-03-13 00:02:56 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteVecLoad, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
2018-05-11 22:30:54 +08:00
|
|
|
defm : X86WriteRes<WriteVecLoadX, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecLoadY, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
2018-05-15 02:37:19 +08:00
|
|
|
defm : X86WriteRes<WriteVecLoadNT, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecLoadNTY, [JLAGU, JFPU01, JVALU], 5, [1, 1, 1], 1>;
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteVecMaskedLoad, [JLAGU, JFPU01, JVALU], 6, [1, 1, 2], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecMaskedLoadY, [JLAGU, JFPU01, JVALU], 6, [2, 2, 4], 2>;
|
|
|
|
|
2018-05-18 22:22:22 +08:00
|
|
|
defm : X86WriteRes<WriteVecStore, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
|
2018-05-11 22:30:54 +08:00
|
|
|
defm : X86WriteRes<WriteVecStoreX, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecStoreY, [JSAGU, JFPU1, JSTC], 1, [1, 1, 1], 1>;
|
2018-05-15 02:37:19 +08:00
|
|
|
defm : X86WriteRes<WriteVecStoreNT, [JSAGU, JFPU1, JSTC], 2, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecStoreNTY, [JSAGU, JFPU1, JSTC], 2, [2, 2, 2], 1>;
|
2018-05-08 20:17:55 +08:00
|
|
|
defm : X86WriteRes<WriteVecMaskedStore, [JSAGU, JFPU01, JVALU], 6, [1, 1, 4], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecMaskedStoreY, [JSAGU, JFPU01, JVALU], 6, [2, 2, 4], 2>;
|
|
|
|
|
2018-05-12 01:38:36 +08:00
|
|
|
defm : X86WriteRes<WriteVecMove, [JFPU01, JVALU], 1, [1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecMoveX, [JFPU01, JVALU], 1, [1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecMoveY, [JFPU01, JVALU], 1, [2, 2], 2>;
|
2018-05-19 01:58:36 +08:00
|
|
|
defm : X86WriteRes<WriteVecMoveToGpr, [JFPU0, JFPA, JALU0], 4, [1, 1, 1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecMoveFromGpr, [JFPU01, JFPX], 8, [1, 1], 2>;
|
2018-03-15 22:45:30 +08:00
|
|
|
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecALU, [JFPU01, JVALU], 1>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecALUX, [JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecALUY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecALUZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecShift, [JFPU01, JVALU], 1>;
|
2018-05-04 01:56:43 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecShiftX, [JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
|
2018-05-05 01:47:46 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecShiftImm, [JFPU01, JVALU], 1>;
|
2018-05-04 01:56:43 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecShiftImmX,[JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftImmY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShift>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecIMul, [JFPU0, JVIMUL], 2>;
|
2018-05-05 01:47:46 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecIMulX, [JFPU0, JVIMUL], 2>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecIMulY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
|
2018-03-31 12:54:32 +08:00
|
|
|
defm : JWriteResFpuPair<WritePMULLD, [JFPU0, JFPU01, JVIMUL, JVALU], 4, [2, 1, 2, 1], 3>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WritePMULLDY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WritePMULLDZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteMPSAD, [JFPU0, JVIMUL], 3, [1, 2]>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteMPSADY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteMPSADZ>;
|
2018-04-18 03:35:19 +08:00
|
|
|
defm : JWriteResFpuPair<WritePSADBW, [JFPU01, JVALU], 2>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WritePSADBWX, [JFPU01, JVALU], 2>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WritePSADBWY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WritePSADBWZ>;
|
2018-04-25 02:49:25 +08:00
|
|
|
defm : JWriteResFpuPair<WritePHMINPOS, [JFPU0, JVALU], 2>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteShuffle, [JFPU01, JVALU], 1>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WriteShuffleX, [JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteShuffleY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteShuffleZ>;
|
2018-04-11 21:49:19 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVarShuffle, [JFPU01, JVALU], 2, [1, 4], 3>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVarShuffleX, [JFPU01, JVALU], 2, [1, 4], 3>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffleY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteBlend, [JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteBlendY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteBlendZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVarBlend, [JFPU01, JVALU], 2, [1, 4], 3>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecLogic, [JFPU01, JVALU], 1>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecLogicX, [JFPU01, JVALU], 1>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecLogicY>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
|
2018-05-08 18:28:03 +08:00
|
|
|
defm : JWriteResFpuPair<WriteVecTest, [JFPU0, JFPA, JALU0], 3>;
|
2018-06-11 22:37:53 +08:00
|
|
|
defm : JWriteResYMMPair<WriteVecTestY, [JFPU01, JFPX, JFPA, JALU0], 4, [2, 2, 2, 1], 3>;
|
|
|
|
defm : X86WriteResPairUnsupported<WriteVecTestZ>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteShuffle256>;
|
2018-06-11 15:00:08 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-04-08 19:26:26 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
2018-04-24 21:21:41 +08:00
|
|
|
// Vector insert/extract operations.
|
2018-04-08 19:26:26 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-05-19 01:09:41 +08:00
|
|
|
defm : X86WriteRes<WriteVecInsert, [JFPU01, JVALU], 7, [1,1], 2>;
|
|
|
|
defm : X86WriteRes<WriteVecInsertLd, [JFPU01, JVALU, JLAGU], 4, [1,1,1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecExtract, [JFPU0, JFPA, JALU0], 3, [1,1,1], 1>;
|
|
|
|
defm : X86WriteRes<WriteVecExtractSt, [JFPU1, JSTC, JSAGU], 3, [1,1,1], 1>;
|
2018-04-08 19:26:26 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
2018-03-15 07:12:09 +08:00
|
|
|
// SSE42 String instructions.
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-27 00:10:08 +08:00
|
|
|
defm : JWriteResFpuPair<WritePCmpIStrI, [JFPU1, JVALU1, JFPA, JALU0], 7, [1, 2, 1, 1], 3>;
|
|
|
|
defm : JWriteResFpuPair<WritePCmpIStrM, [JFPU1, JVALU1, JFPA, JALU0], 8, [1, 2, 1, 1], 3>;
|
|
|
|
defm : JWriteResFpuPair<WritePCmpEStrI, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
|
|
|
|
defm : JWriteResFpuPair<WritePCmpEStrM, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-03-28 04:38:54 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// MOVMSK Instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-06-18 22:31:14 +08:00
|
|
|
def : WriteRes<WriteFMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
|
|
|
def : WriteRes<WriteVecMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
|
|
|
defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
|
|
|
|
def : WriteRes<WriteMMXMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
|
2018-03-28 04:38:54 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// AES Instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-16 01:45:10 +08:00
|
|
|
defm : JWriteResFpuPair<WriteAESIMC, [JFPU0, JVIMUL], 2>;
|
|
|
|
defm : JWriteResFpuPair<WriteAESKeyGen, [JFPU0, JVIMUL], 2>;
|
2018-05-03 14:08:47 +08:00
|
|
|
defm : JWriteResFpuPair<WriteAESDecEnc, [JFPU0, JVIMUL], 3, [1, 1], 2>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2017-06-09 00:44:13 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Horizontal add/sub instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WriteFHAdd, [JFPU0, JFPA], 3>;
|
2018-04-28 00:11:57 +08:00
|
|
|
defm : JWriteResYMMPair<WriteFHAddY, [JFPU0, JFPA], 3, [2,2], 2>;
|
2018-03-18 20:09:17 +08:00
|
|
|
defm : JWriteResFpuPair<WritePHAdd, [JFPU01, JVALU], 1>;
|
2018-05-11 01:06:09 +08:00
|
|
|
defm : JWriteResFpuPair<WritePHAddX, [JFPU01, JVALU], 1>;
|
2018-06-18 22:31:14 +08:00
|
|
|
defm : X86WriteResPairUnsupported<WritePHAddY>;
|
2017-06-09 00:44:13 +08:00
|
|
|
|
2014-09-10 04:07:07 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Carry-less multiplication instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-16 01:45:10 +08:00
|
|
|
defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2017-07-16 20:06:06 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// SSE4A instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-03-18 21:05:09 +08:00
|
|
|
def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
|
2017-07-16 20:06:06 +08:00
|
|
|
let Latency = 2;
|
2018-03-18 21:05:09 +08:00
|
|
|
let ResourceCycles = [1, 4];
|
2017-07-16 20:06:06 +08:00
|
|
|
}
|
2018-03-13 01:07:08 +08:00
|
|
|
def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
|
2017-07-16 20:06:06 +08:00
|
|
|
|
2017-07-11 00:36:03 +08:00
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
// AVX instructions.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
2018-08-31 16:30:47 +08:00
|
|
|
def JWriteVecExtractF128: SchedWriteRes<[JFPU01, JFPX]>;
|
|
|
|
def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;
|
|
|
|
|
2018-03-24 00:17:56 +08:00
|
|
|
def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
|
2017-11-02 18:33:41 +08:00
|
|
|
let Latency = 6;
|
2018-03-26 21:15:20 +08:00
|
|
|
let ResourceCycles = [1, 2, 4];
|
2018-03-28 20:12:04 +08:00
|
|
|
let NumMicroOps = 2;
|
2017-11-02 18:33:41 +08:00
|
|
|
}
|
2018-09-01 00:05:48 +08:00
|
|
|
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
|
|
|
|
VBROADCASTSSYrm,
|
|
|
|
VBROADCASTF128)>;
|
2017-11-02 18:33:41 +08:00
|
|
|
|
2018-03-13 01:07:08 +08:00
|
|
|
def JWriteJVZEROALL: SchedWriteRes<[]> {
|
2017-07-27 21:12:08 +08:00
|
|
|
let Latency = 90;
|
|
|
|
let NumMicroOps = 73;
|
|
|
|
}
|
2018-03-13 01:07:08 +08:00
|
|
|
def : InstRW<[JWriteJVZEROALL], (instrs VZEROALL)>;
|
2017-07-27 21:12:08 +08:00
|
|
|
|
2018-03-13 01:07:08 +08:00
|
|
|
def JWriteJVZEROUPPER: SchedWriteRes<[]> {
|
2017-07-27 21:12:08 +08:00
|
|
|
let Latency = 46;
|
|
|
|
let NumMicroOps = 37;
|
|
|
|
}
|
2018-03-13 01:07:08 +08:00
|
|
|
def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;
|
2014-09-10 04:07:07 +08:00
|
|
|
|
2018-06-04 23:43:09 +08:00
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
// SchedWriteVariant definitions.
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
def JWriteZeroLatency : SchedWriteRes<[]> {
|
|
|
|
let Latency = 0;
|
|
|
|
}
|
|
|
|
|
2018-06-11 22:37:53 +08:00
|
|
|
// Certain instructions that use the same register for both source
|
2018-06-04 23:43:09 +08:00
|
|
|
// operands do not have a real dependency on the previous contents of the
|
|
|
|
// register, and thus, do not have to wait before completing. They can be
|
|
|
|
// optimized out at register renaming stage.
|
|
|
|
// Reference: Section 10.8 of the "Software Optimization Guide for AMD Family
|
|
|
|
// 15h Processors".
|
|
|
|
// Reference: Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
|
|
|
|
// Section 21.8 [Dependency-breaking instructions].
|
|
|
|
|
2018-06-09 01:00:45 +08:00
|
|
|
def JWriteZeroIdiom : SchedWriteVariant<[
|
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteALU]>
|
2018-06-09 01:00:45 +08:00
|
|
|
]>;
|
|
|
|
def : InstRW<[JWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
|
|
|
|
XOR32rr, XOR64rr)>;
|
|
|
|
|
2018-06-04 23:43:09 +08:00
|
|
|
def JWriteFZeroIdiom : SchedWriteVariant<[
|
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteFLogic]>
|
2018-06-04 23:43:09 +08:00
|
|
|
]>;
|
2018-06-07 03:06:09 +08:00
|
|
|
def : InstRW<[JWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, VXORPDrr,
|
|
|
|
ANDNPSrr, VANDNPSrr,
|
|
|
|
ANDNPDrr, VANDNPDrr)>;
|
2018-06-04 23:43:09 +08:00
|
|
|
|
2018-06-07 03:06:09 +08:00
|
|
|
def JWriteVZeroIdiomLogic : SchedWriteVariant<[
|
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteVecLogic]>
|
2018-06-07 03:06:09 +08:00
|
|
|
]>;
|
|
|
|
def : InstRW<[JWriteVZeroIdiomLogic], (instrs MMX_PXORirr, MMX_PANDNirr)>;
|
2018-06-04 23:43:09 +08:00
|
|
|
|
2018-06-07 03:06:09 +08:00
|
|
|
def JWriteVZeroIdiomLogicX : SchedWriteVariant<[
|
2018-06-04 23:43:09 +08:00
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteVecLogicX]>
|
2018-06-04 23:43:09 +08:00
|
|
|
]>;
|
2018-06-07 03:06:09 +08:00
|
|
|
def : InstRW<[JWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr,
|
|
|
|
PANDNrr, VPANDNrr)>;
|
2018-06-04 23:43:09 +08:00
|
|
|
|
2018-06-07 03:06:09 +08:00
|
|
|
def JWriteVZeroIdiomALU : SchedWriteVariant<[
|
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteVecALU]>
|
2018-06-07 03:06:09 +08:00
|
|
|
]>;
|
|
|
|
def : InstRW<[JWriteVZeroIdiomALU], (instrs MMX_PSUBBirr, MMX_PSUBDirr,
|
|
|
|
MMX_PSUBQirr, MMX_PSUBWirr,
|
|
|
|
MMX_PCMPGTBirr, MMX_PCMPGTDirr,
|
|
|
|
MMX_PCMPGTWirr)>;
|
2018-06-04 23:43:09 +08:00
|
|
|
|
2018-06-07 03:06:09 +08:00
|
|
|
def JWriteVZeroIdiomALUX : SchedWriteVariant<[
|
|
|
|
SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [JWriteZeroLatency]>,
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<NoSchedPred, [WriteVecALUX]>
|
2018-06-07 03:06:09 +08:00
|
|
|
]>;
|
|
|
|
def : InstRW<[JWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
|
|
|
|
PSUBDrr, VPSUBDrr,
|
|
|
|
PSUBQrr, VPSUBQrr,
|
|
|
|
PSUBWrr, VPSUBWrr,
|
|
|
|
PCMPGTBrr, VPCMPGTBrr,
|
|
|
|
PCMPGTDrr, VPCMPGTDrr,
|
|
|
|
PCMPGTQrr, VPCMPGTQrr,
|
|
|
|
PCMPGTWrr, VPCMPGTWrr)>;
|
2018-07-20 00:42:15 +08:00
|
|
|
|
|
|
|
// This write is used for slow LEA instructions.
|
|
|
|
def JWrite3OpsLEA : SchedWriteRes<[JALU1, JSAGU]> {
|
|
|
|
let Latency = 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
// On Jaguar, a slow LEA is either a 3Ops LEA (base, index, offset), or an LEA
|
|
|
|
// with a `Scale` value different than 1.
|
|
|
|
def JSlowLEAPredicate : MCSchedPredicate<
|
|
|
|
CheckAny<[
|
|
|
|
// A 3-operand LEA (base, index, offset).
|
|
|
|
IsThreeOperandsLEAFn,
|
|
|
|
// An LEA with a "Scale" different than 1.
|
|
|
|
CheckAll<[
|
|
|
|
CheckIsImmOperand<2>,
|
|
|
|
CheckNot<CheckImmOperand<2, 1>>
|
|
|
|
]>
|
|
|
|
]>
|
|
|
|
>;
|
|
|
|
|
|
|
|
def JWriteLEA : SchedWriteVariant<[
|
2018-08-14 01:52:39 +08:00
|
|
|
SchedVar<JSlowLEAPredicate, [JWrite3OpsLEA]>,
|
|
|
|
SchedVar<NoSchedPred, [WriteLEA]>
|
2018-07-20 00:42:15 +08:00
|
|
|
]>;
|
|
|
|
|
|
|
|
def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
|
|
|
|
|
|
|
|
def JSlowLEA16r : SchedWriteRes<[JALU01]> {
|
|
|
|
let Latency = 3;
|
|
|
|
let ResourceCycles = [4];
|
|
|
|
}
|
|
|
|
|
|
|
|
def : InstRW<[JSlowLEA16r], (instrs LEA16r)>;
|
|
|
|
|
[TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
This patch adds the ability for processor models to describe dependency breaking
instructions.
Different processors may specify a different set of dependency-breaking
instructions.
That means, we cannot assume that all processors of the same target would use
the same rules to classify dependency breaking instructions.
The main goal of this patch is to provide the means to describe dependency
breaking instructions directly via tablegen, and have the following
TargetSubtargetInfo hooks redefined in overrides by tabegen'd
XXXGenSubtargetInfo classes (here, XXX is a Target name).
```
virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
return false;
}
virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
return isZeroIdiom(MI);
}
```
An instruction MI is a dependency-breaking instruction if a call to method
isDependencyBreaking(MI) on the STI (TargetSubtargetInfo object) evaluates to
true. Similarly, an instruction MI is a special case of zero-idiom dependency
breaking instruction if a call to STI.isZeroIdiom(MI) returns true.
The extra APInt is used for those targets that may want to select which machine
operands have their dependency broken (see comments in code).
Note that by default, subtargets don't know about the existence of
dependency-breaking. In the absence of external information, those method calls
would always return false.
A new tablegen class named STIPredicate has been added by this patch to let
processor models classify instructions that have properties in common. The idea
is that, a MCInstrPredicate definition can be used to "generate" an instruction
equivalence class, with the idea that instructions of a same class all have a
property in common.
STIPredicate definitions are essentially a collection of instruction equivalence
classes.
Also, different processor models can specify a different variant of the same
STIPredicate with different rules (i.e. predicates) to classify instructions.
Tablegen backends (in this particular case, the SubtargetEmitter) will be able
to process STIPredicate definitions, and automatically generate functions in
XXXGenSubtargetInfo.
This patch introduces two special kind of STIPredicate classes named
IsZeroIdiomFunction and IsDepBreakingFunction in tablegen. It also adds a
definition for those in the BtVer2 scheduling model only.
This patch supersedes the one committed at r338372 (phabricator review: D49310).
The main advantages are:
- We can describe subtarget predicates via tablegen using STIPredicates.
- We can describe zero-idioms / dep-breaking instructions directly via
tablegen in the scheduling models.
In future, the STIPredicates framework can be used for solving other problems.
Examples of future developments are:
- Teach how to identify optimizable register-register moves
- Teach how to identify slow LEA instructions (each subtarget defining its own
concept of "slow" LEA).
- Teach how to identify instructions that have undocumented false dependencies
on the output registers on some processors only.
It is also (in my opinion) an elegant way to expose knowledge to both external
tools like llvm-mca, and codegen passes.
For example, machine schedulers in LLVM could reuse that information when
internally constructing the data dependency graph for a code region.
This new design feature is also an "opt-in" feature. Processor models don't have
to use the new STIPredicates. It has all been designed to be as unintrusive as
possible.
Differential Revision: https://reviews.llvm.org/D52174
llvm-svn: 342555
2018-09-19 23:57:45 +08:00
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Dependency breaking instructions.
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
|
|
|
|
def : IsZeroIdiomFunction<[
|
|
|
|
// GPR Zero-idioms.
|
|
|
|
DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,
|
|
|
|
|
|
|
|
// MMX Zero-idioms.
|
|
|
|
DepBreakingClass<[
|
|
|
|
MMX_PXORirr, MMX_PANDNirr, MMX_PSUBBirr,
|
|
|
|
MMX_PSUBDirr, MMX_PSUBQirr, MMX_PSUBWirr,
|
|
|
|
MMX_PCMPGTBirr, MMX_PCMPGTDirr, MMX_PCMPGTWirr
|
|
|
|
], ZeroIdiomPredicate>,
|
|
|
|
|
|
|
|
// SSE Zero-idioms.
|
|
|
|
DepBreakingClass<[
|
|
|
|
// fp variants.
|
|
|
|
XORPSrr, XORPDrr, ANDNPSrr, ANDNPDrr,
|
|
|
|
|
|
|
|
// int variants.
|
|
|
|
PXORrr, PANDNrr,
|
|
|
|
PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
|
|
|
|
PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr
|
|
|
|
], ZeroIdiomPredicate>,
|
|
|
|
|
|
|
|
// AVX Zero-idioms.
|
|
|
|
DepBreakingClass<[
|
|
|
|
// xmm fp variants.
|
|
|
|
VXORPSrr, VXORPDrr, VANDNPSrr, VANDNPDrr,
|
|
|
|
|
|
|
|
// xmm int variants.
|
|
|
|
VPXORrr, VPANDNrr,
|
|
|
|
VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
|
|
|
|
VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
|
|
|
|
|
|
|
|
// ymm variants.
|
|
|
|
VXORPSYrr, VXORPDYrr, VANDNPSYrr, VANDNPDYrr
|
|
|
|
], ZeroIdiomPredicate>
|
|
|
|
]>;
|
|
|
|
|
|
|
|
def : IsDepBreakingFunction<[
|
|
|
|
// GPR
|
|
|
|
DepBreakingClass<[ SBB32rr, SBB64rr ], ZeroIdiomPredicate>,
|
|
|
|
DepBreakingClass<[ CMP32rr, CMP64rr ], CheckSameRegOperand<0, 1> >,
|
|
|
|
|
|
|
|
// MMX
|
|
|
|
DepBreakingClass<[
|
|
|
|
MMX_PCMPEQBirr, MMX_PCMPEQDirr, MMX_PCMPEQWirr
|
|
|
|
], ZeroIdiomPredicate>,
|
|
|
|
|
|
|
|
// SSE
|
|
|
|
DepBreakingClass<[
|
|
|
|
PCMPEQBrr, PCMPEQWrr, PCMPEQDrr, PCMPEQQrr
|
|
|
|
], ZeroIdiomPredicate>,
|
|
|
|
|
|
|
|
// AVX
|
|
|
|
DepBreakingClass<[
|
|
|
|
VPCMPEQBrr, VPCMPEQWrr, VPCMPEQDrr, VPCMPEQQrr
|
|
|
|
], ZeroIdiomPredicate>
|
|
|
|
]>;
|
|
|
|
|
2018-06-04 23:43:09 +08:00
|
|
|
} // SchedModel
|