2015-08-25 02:44:37 +08:00
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//===-- WebAssemblyFastISel.cpp - WebAssembly FastISel implementation -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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2018-05-01 23:54:18 +08:00
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/// This file defines the WebAssembly-specific support for the FastISel
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2015-08-25 02:44:37 +08:00
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/// class. Some of the target-specific code is generated by tablegen in the file
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/// WebAssemblyGenFastISel.inc, which is #included here.
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///
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2016-05-12 12:19:09 +08:00
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/// TODO: kill flags
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///
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2015-08-25 02:44:37 +08:00
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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2017-06-06 19:49:48 +08:00
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#include "WebAssembly.h"
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2016-05-12 12:19:09 +08:00
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#include "WebAssemblyMachineFunctionInfo.h"
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2015-08-25 02:44:37 +08:00
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyTargetMachine.h"
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#include "llvm/Analysis/BranchProbabilityInfo.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/GetElementPtrTypeIterator.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Operator.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-fastisel"
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namespace {
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class WebAssemblyFastISel final : public FastISel {
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2016-05-11 01:39:48 +08:00
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// All possible address modes.
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class Address {
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public:
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typedef enum { RegBase, FrameIndexBase } BaseKind;
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private:
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BaseKind Kind;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int64_t Offset;
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const GlobalValue *GV;
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public:
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// Innocuous defaults for our address.
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Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
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2017-06-23 05:26:08 +08:00
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void setKind(BaseKind K) {
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assert(!isSet() && "Can't change kind with non-zero base");
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Kind = K;
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}
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2016-05-11 01:39:48 +08:00
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BaseKind getKind() const { return Kind; }
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bool isRegBase() const { return Kind == RegBase; }
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bool isFIBase() const { return Kind == FrameIndexBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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2017-06-23 05:26:08 +08:00
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assert(Base.Reg == 0 && "Overwriting non-zero register");
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2016-05-11 01:39:48 +08:00
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Base.Reg = Reg;
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}
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unsigned getReg() const {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setFI(unsigned FI) {
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assert(isFIBase() && "Invalid base frame index access!");
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2017-06-23 05:26:08 +08:00
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assert(Base.FI == 0 && "Overwriting non-zero frame index");
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2016-05-11 01:39:48 +08:00
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Base.FI = FI;
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}
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unsigned getFI() const {
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assert(isFIBase() && "Invalid base frame index access!");
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return Base.FI;
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}
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2016-12-22 23:15:10 +08:00
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void setOffset(int64_t Offset_) {
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assert(Offset_ >= 0 && "Offsets must be non-negative");
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Offset = Offset_;
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}
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2016-05-11 01:39:48 +08:00
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int64_t getOffset() const { return Offset; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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const GlobalValue *getGlobalValue() const { return GV; }
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2017-06-23 05:26:08 +08:00
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bool isSet() const {
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if (isRegBase()) {
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return Base.Reg != 0;
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} else {
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return Base.FI != 0;
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}
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}
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2016-05-11 01:39:48 +08:00
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};
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2015-08-25 02:44:37 +08:00
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/// Keep a pointer to the WebAssemblySubtarget around so that we can make the
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/// right decision when generating code for different targets.
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const WebAssemblySubtarget *Subtarget;
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LLVMContext *Context;
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private:
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2016-05-11 01:39:48 +08:00
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// Utility helper routines
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2016-05-12 00:32:42 +08:00
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MVT::SimpleValueType getSimpleType(Type *Ty) {
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EVT VT = TLI.getValueType(DL, Ty, /*HandleUnknown=*/true);
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2018-09-05 09:27:38 +08:00
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return VT.isSimple() ? VT.getSimpleVT().SimpleTy
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: MVT::INVALID_SIMPLE_VALUE_TYPE;
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2016-05-12 00:32:42 +08:00
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}
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MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) {
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switch (VT) {
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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return MVT::i32;
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2016-05-12 12:19:09 +08:00
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case MVT::i32:
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2016-05-12 00:32:42 +08:00
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case MVT::i64:
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2016-05-12 12:19:09 +08:00
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case MVT::f32:
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case MVT::f64:
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2018-03-08 12:05:37 +08:00
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case MVT::ExceptRef:
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2016-05-12 12:19:09 +08:00
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return VT;
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2017-02-25 05:05:35 +08:00
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case MVT::f16:
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return MVT::f32;
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2016-08-03 07:16:09 +08:00
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case MVT::v16i8:
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case MVT::v8i16:
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case MVT::v4i32:
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2018-08-08 05:24:01 +08:00
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case MVT::v2i64:
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2016-08-03 07:16:09 +08:00
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case MVT::v4f32:
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2018-08-08 05:24:01 +08:00
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case MVT::v2f64:
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2016-08-03 07:16:09 +08:00
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if (Subtarget->hasSIMD128())
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return VT;
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break;
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2016-05-12 00:32:42 +08:00
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default:
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break;
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}
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return MVT::INVALID_SIMPLE_VALUE_TYPE;
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}
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2016-05-11 01:39:48 +08:00
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bool computeAddress(const Value *Obj, Address &Addr);
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void materializeLoadStoreOperands(Address &Addr);
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void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
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MachineMemOperand *MMO);
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2016-05-12 00:32:42 +08:00
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unsigned maskI1Value(unsigned Reg, const Value *V);
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2016-05-12 12:19:09 +08:00
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unsigned getRegForI1Value(const Value *V, bool &Not);
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2016-05-12 00:32:42 +08:00
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unsigned zeroExtendToI32(unsigned Reg, const Value *V,
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MVT::SimpleValueType From);
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unsigned signExtendToI32(unsigned Reg, const Value *V,
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MVT::SimpleValueType From);
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2018-09-05 09:27:38 +08:00
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unsigned zeroExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
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2016-05-12 00:32:42 +08:00
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MVT::SimpleValueType To);
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2018-09-05 09:27:38 +08:00
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unsigned signExtend(unsigned Reg, const Value *V, MVT::SimpleValueType From,
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2016-05-12 00:32:42 +08:00
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MVT::SimpleValueType To);
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unsigned getRegForUnsignedValue(const Value *V);
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unsigned getRegForSignedValue(const Value *V);
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unsigned getRegForPromotedValue(const Value *V, bool IsSigned);
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unsigned notValue(unsigned Reg);
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2016-05-12 12:19:09 +08:00
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unsigned copyValue(unsigned Reg);
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2016-05-11 01:39:48 +08:00
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// Backend specific FastISel code.
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unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
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unsigned fastMaterializeConstant(const Constant *C) override;
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2016-05-12 12:19:09 +08:00
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bool fastLowerArguments() override;
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2016-05-11 01:39:48 +08:00
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// Selection routines.
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2016-05-12 12:19:09 +08:00
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bool selectCall(const Instruction *I);
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bool selectSelect(const Instruction *I);
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bool selectTrunc(const Instruction *I);
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2016-05-12 00:32:42 +08:00
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bool selectZExt(const Instruction *I);
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bool selectSExt(const Instruction *I);
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bool selectICmp(const Instruction *I);
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bool selectFCmp(const Instruction *I);
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2016-05-11 01:39:48 +08:00
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bool selectBitCast(const Instruction *I);
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bool selectLoad(const Instruction *I);
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bool selectStore(const Instruction *I);
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bool selectBr(const Instruction *I);
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bool selectRet(const Instruction *I);
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bool selectUnreachable(const Instruction *I);
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2015-08-25 02:44:37 +08:00
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public:
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// Backend specific FastISel code.
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WebAssemblyFastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo)
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: FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
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Subtarget = &FuncInfo.MF->getSubtarget<WebAssemblySubtarget>();
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Context = &FuncInfo.Fn->getContext();
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}
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bool fastSelectInstruction(const Instruction *I) override;
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#include "WebAssemblyGenFastISel.inc"
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};
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} // end anonymous namespace
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2016-05-11 01:39:48 +08:00
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bool WebAssemblyFastISel::computeAddress(const Value *Obj, Address &Addr) {
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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// Don't walk into other basic blocks unless the object is an alloca from
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// another block, otherwise it may not have a virtual register assigned.
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if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
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FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
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Opcode = I->getOpcode();
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U = I;
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}
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} else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
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Opcode = C->getOpcode();
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U = C;
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}
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if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
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if (Ty->getAddressSpace() > 255)
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// Fast instruction selection doesn't support the special
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// address spaces.
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return false;
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if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
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if (Addr.getGlobalValue())
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return false;
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Addr.setGlobalValue(GV);
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return true;
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}
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switch (Opcode) {
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2015-08-25 02:44:37 +08:00
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default:
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break;
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2016-05-11 01:39:48 +08:00
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case Instruction::BitCast: {
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// Look through bitcasts.
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return computeAddress(U->getOperand(0), Addr);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
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TLI.getPointerTy(DL))
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return computeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints.
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if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
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return computeAddress(U->getOperand(0), Addr);
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break;
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}
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case Instruction::GetElementPtr: {
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Address SavedAddr = Addr;
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uint64_t TmpOffset = Addr.getOffset();
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2016-12-22 23:15:10 +08:00
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// Non-inbounds geps can wrap; wasm's offsets can't.
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if (!cast<GEPOperator>(U)->isInBounds())
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goto unsupported_gep;
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2016-05-11 01:39:48 +08:00
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// Iterate through the GEP folding the constants into offsets where
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// we can.
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2016-05-12 12:19:09 +08:00
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for (gep_type_iterator GTI = gep_type_begin(U), E = gep_type_end(U);
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2016-05-11 01:39:48 +08:00
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GTI != E; ++GTI) {
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const Value *Op = GTI.getOperand();
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2016-12-02 10:24:42 +08:00
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if (StructType *STy = GTI.getStructTypeOrNull()) {
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2016-05-11 01:39:48 +08:00
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const StructLayout *SL = DL.getStructLayout(STy);
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unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
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TmpOffset += SL->getElementOffset(Idx);
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} else {
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uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
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for (;;) {
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
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// Constant-offset addressing.
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TmpOffset += CI->getSExtValue() * S;
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break;
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}
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2016-05-12 12:19:09 +08:00
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if (S == 1 && Addr.isRegBase() && Addr.getReg() == 0) {
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// An unscaled add of a register. Set it as the new base.
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2017-11-28 13:36:42 +08:00
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unsigned Reg = getRegForValue(Op);
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if (Reg == 0)
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return false;
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Addr.setReg(Reg);
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2016-05-12 12:19:09 +08:00
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break;
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}
|
2016-05-11 01:39:48 +08:00
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if (canFoldAddIntoGEP(U, Op)) {
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// A compatible add with a constant operand. Fold the constant.
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ConstantInt *CI =
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cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
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TmpOffset += CI->getSExtValue() * S;
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// Iterate on the other operand.
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Op = cast<AddOperator>(Op)->getOperand(0);
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continue;
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}
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// Unsupported
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goto unsupported_gep;
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}
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}
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}
|
2016-12-22 23:15:10 +08:00
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// Don't fold in negative offsets.
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if (int64_t(TmpOffset) >= 0) {
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (computeAddress(U->getOperand(0), Addr))
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return true;
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}
|
2016-05-11 01:39:48 +08:00
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// We failed, restore everything and try the other options.
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Addr = SavedAddr;
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unsupported_gep:
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break;
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}
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case Instruction::Alloca: {
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const AllocaInst *AI = cast<AllocaInst>(Obj);
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DenseMap<const AllocaInst *, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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2017-06-23 05:26:08 +08:00
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if (Addr.isSet()) {
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|
|
|
return false;
|
|
|
|
}
|
2016-05-11 01:39:48 +08:00
|
|
|
Addr.setKind(Address::FrameIndexBase);
|
|
|
|
Addr.setFI(SI->second);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Instruction::Add: {
|
|
|
|
// Adds of constants are common and easy enough.
|
|
|
|
const Value *LHS = U->getOperand(0);
|
|
|
|
const Value *RHS = U->getOperand(1);
|
|
|
|
|
|
|
|
if (isa<ConstantInt>(LHS))
|
|
|
|
std::swap(LHS, RHS);
|
|
|
|
|
|
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
|
2016-12-22 23:15:10 +08:00
|
|
|
uint64_t TmpOffset = Addr.getOffset() + CI->getSExtValue();
|
|
|
|
if (int64_t(TmpOffset) >= 0) {
|
|
|
|
Addr.setOffset(TmpOffset);
|
|
|
|
return computeAddress(LHS, Addr);
|
|
|
|
}
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
Address Backup = Addr;
|
|
|
|
if (computeAddress(LHS, Addr) && computeAddress(RHS, Addr))
|
|
|
|
return true;
|
|
|
|
Addr = Backup;
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case Instruction::Sub: {
|
|
|
|
// Subs of constants are common and easy enough.
|
|
|
|
const Value *LHS = U->getOperand(0);
|
|
|
|
const Value *RHS = U->getOperand(1);
|
|
|
|
|
|
|
|
if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
|
2016-12-22 23:15:10 +08:00
|
|
|
int64_t TmpOffset = Addr.getOffset() - CI->getSExtValue();
|
|
|
|
if (TmpOffset >= 0) {
|
|
|
|
Addr.setOffset(TmpOffset);
|
|
|
|
return computeAddress(LHS, Addr);
|
|
|
|
}
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-06-23 05:26:08 +08:00
|
|
|
if (Addr.isSet()) {
|
|
|
|
return false;
|
|
|
|
}
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned Reg = getRegForValue(Obj);
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
Addr.setReg(Reg);
|
2016-05-11 01:39:48 +08:00
|
|
|
return Addr.getReg() != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void WebAssemblyFastISel::materializeLoadStoreOperands(Address &Addr) {
|
|
|
|
if (Addr.isRegBase()) {
|
|
|
|
unsigned Reg = Addr.getReg();
|
|
|
|
if (Reg == 0) {
|
2018-09-05 09:27:38 +08:00
|
|
|
Reg = createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
|
|
|
|
: &WebAssembly::I32RegClass);
|
|
|
|
unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
|
|
|
|
: WebAssembly::CONST_I32;
|
2016-05-11 01:39:48 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addImm(0);
|
2016-05-11 01:39:48 +08:00
|
|
|
Addr.setReg(Reg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void WebAssemblyFastISel::addLoadStoreOperands(const Address &Addr,
|
|
|
|
const MachineInstrBuilder &MIB,
|
|
|
|
MachineMemOperand *MMO) {
|
2016-10-25 08:17:11 +08:00
|
|
|
// Set the alignment operand (this is rewritten in SetP2AlignOperands).
|
|
|
|
// TODO: Disable SetP2AlignOperands for FastISel and just do it here.
|
|
|
|
MIB.addImm(0);
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
if (const GlobalValue *GV = Addr.getGlobalValue())
|
|
|
|
MIB.addGlobalAddress(GV, Addr.getOffset());
|
|
|
|
else
|
|
|
|
MIB.addImm(Addr.getOffset());
|
|
|
|
|
|
|
|
if (Addr.isRegBase())
|
|
|
|
MIB.addReg(Addr.getReg());
|
|
|
|
else
|
|
|
|
MIB.addFrameIndex(Addr.getFI());
|
|
|
|
|
|
|
|
MIB.addMemOperand(MMO);
|
|
|
|
}
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
unsigned WebAssemblyFastISel::maskI1Value(unsigned Reg, const Value *V) {
|
|
|
|
return zeroExtendToI32(Reg, V, MVT::i1);
|
|
|
|
}
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
unsigned WebAssemblyFastISel::getRegForI1Value(const Value *V, bool &Not) {
|
|
|
|
if (const ICmpInst *ICmp = dyn_cast<ICmpInst>(V))
|
|
|
|
if (const ConstantInt *C = dyn_cast<ConstantInt>(ICmp->getOperand(1)))
|
|
|
|
if (ICmp->isEquality() && C->isZero() && C->getType()->isIntegerTy(32)) {
|
|
|
|
Not = ICmp->isTrueWhenEqual();
|
|
|
|
return getRegForValue(ICmp->getOperand(0));
|
|
|
|
}
|
|
|
|
|
2018-07-03 03:45:57 +08:00
|
|
|
if (BinaryOperator::isNot(V) && V->getType()->isIntegerTy(32)) {
|
2016-05-12 12:19:09 +08:00
|
|
|
Not = true;
|
|
|
|
return getRegForValue(BinaryOperator::getNotArgument(V));
|
|
|
|
}
|
|
|
|
|
|
|
|
Not = false;
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned Reg = getRegForValue(V);
|
|
|
|
if (Reg == 0)
|
|
|
|
return 0;
|
|
|
|
return maskI1Value(Reg, V);
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
|
|
|
|
MVT::SimpleValueType From) {
|
2016-08-05 02:01:52 +08:00
|
|
|
if (Reg == 0)
|
|
|
|
return 0;
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
switch (From) {
|
|
|
|
case MVT::i1:
|
|
|
|
// If the value is naturally an i1, we don't need to mask it.
|
|
|
|
// TODO: Recursively examine selects, phis, and, or, xor, constants.
|
2016-05-12 12:19:09 +08:00
|
|
|
if (From == MVT::i1 && V != nullptr) {
|
|
|
|
if (isa<CmpInst>(V) ||
|
|
|
|
(isa<Argument>(V) && cast<Argument>(V)->hasZExtAttr()))
|
|
|
|
return copyValue(Reg);
|
|
|
|
}
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
2016-05-12 00:32:42 +08:00
|
|
|
break;
|
|
|
|
case MVT::i32:
|
2016-05-12 12:19:09 +08:00
|
|
|
return copyValue(Reg);
|
2016-05-12 00:32:42 +08:00
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-11 01:39:48 +08:00
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
|
2016-05-11 01:39:48 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
2016-05-12 00:32:42 +08:00
|
|
|
TII.get(WebAssembly::CONST_I32), Imm)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addImm(~(~uint64_t(0) << MVT(From).getSizeInBits()));
|
2016-05-11 01:39:48 +08:00
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
unsigned Result = createResultReg(&WebAssembly::I32RegClass);
|
2016-05-11 01:39:48 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
2016-05-12 00:32:42 +08:00
|
|
|
TII.get(WebAssembly::AND_I32), Result)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addReg(Reg)
|
|
|
|
.addReg(Imm);
|
2016-05-11 01:39:48 +08:00
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
return Result;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
unsigned WebAssemblyFastISel::signExtendToI32(unsigned Reg, const Value *V,
|
|
|
|
MVT::SimpleValueType From) {
|
2016-08-05 02:01:52 +08:00
|
|
|
if (Reg == 0)
|
|
|
|
return 0;
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
switch (From) {
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
2016-05-12 12:19:09 +08:00
|
|
|
return copyValue(Reg);
|
2016-05-12 00:32:42 +08:00
|
|
|
default:
|
2016-05-12 12:19:09 +08:00
|
|
|
return 0;
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned Imm = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::CONST_I32), Imm)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addImm(32 - MVT(From).getSizeInBits());
|
2016-05-12 00:32:42 +08:00
|
|
|
|
|
|
|
unsigned Left = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::SHL_I32), Left)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addReg(Reg)
|
|
|
|
.addReg(Imm);
|
2016-05-12 00:32:42 +08:00
|
|
|
|
|
|
|
unsigned Right = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::SHR_S_I32), Right)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addReg(Left)
|
|
|
|
.addReg(Imm);
|
2016-05-12 00:32:42 +08:00
|
|
|
|
|
|
|
return Right;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::zeroExtend(unsigned Reg, const Value *V,
|
|
|
|
MVT::SimpleValueType From,
|
|
|
|
MVT::SimpleValueType To) {
|
|
|
|
if (To == MVT::i64) {
|
|
|
|
if (From == MVT::i64)
|
2016-05-12 12:19:09 +08:00
|
|
|
return copyValue(Reg);
|
2016-05-12 00:32:42 +08:00
|
|
|
|
|
|
|
Reg = zeroExtendToI32(Reg, V, From);
|
|
|
|
|
|
|
|
unsigned Result = createResultReg(&WebAssembly::I64RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::I64_EXTEND_U_I32), Result)
|
|
|
|
.addReg(Reg);
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
return zeroExtendToI32(Reg, V, From);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::signExtend(unsigned Reg, const Value *V,
|
|
|
|
MVT::SimpleValueType From,
|
|
|
|
MVT::SimpleValueType To) {
|
|
|
|
if (To == MVT::i64) {
|
|
|
|
if (From == MVT::i64)
|
2016-05-12 12:19:09 +08:00
|
|
|
return copyValue(Reg);
|
2016-05-12 00:32:42 +08:00
|
|
|
|
|
|
|
Reg = signExtendToI32(Reg, V, From);
|
|
|
|
|
|
|
|
unsigned Result = createResultReg(&WebAssembly::I64RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::I64_EXTEND_S_I32), Result)
|
|
|
|
.addReg(Reg);
|
|
|
|
return Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
return signExtendToI32(Reg, V, From);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) {
|
|
|
|
MVT::SimpleValueType From = getSimpleType(V->getType());
|
|
|
|
MVT::SimpleValueType To = getLegalType(From);
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned VReg = getRegForValue(V);
|
|
|
|
if (VReg == 0)
|
|
|
|
return 0;
|
|
|
|
return zeroExtend(VReg, V, From, To);
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) {
|
|
|
|
MVT::SimpleValueType From = getSimpleType(V->getType());
|
|
|
|
MVT::SimpleValueType To = getLegalType(From);
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned VReg = getRegForValue(V);
|
|
|
|
if (VReg == 0)
|
|
|
|
return 0;
|
|
|
|
return signExtend(VReg, V, From, To);
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::getRegForPromotedValue(const Value *V,
|
|
|
|
bool IsSigned) {
|
2018-09-05 09:27:38 +08:00
|
|
|
return IsSigned ? getRegForSignedValue(V) : getRegForUnsignedValue(V);
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::notValue(unsigned Reg) {
|
2016-05-12 12:19:09 +08:00
|
|
|
assert(MRI.getRegClass(Reg) == &WebAssembly::I32RegClass);
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
unsigned NotReg = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::EQZ_I32), NotReg)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addReg(Reg);
|
2016-05-12 00:32:42 +08:00
|
|
|
return NotReg;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
unsigned WebAssemblyFastISel::copyValue(unsigned Reg) {
|
|
|
|
unsigned ResultReg = createResultReg(MRI.getRegClass(Reg));
|
2018-09-05 09:27:38 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
|
|
|
|
ResultReg)
|
|
|
|
.addReg(Reg);
|
2016-05-12 12:19:09 +08:00
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
unsigned WebAssemblyFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
|
|
|
|
DenseMap<const AllocaInst *, int>::iterator SI =
|
|
|
|
FuncInfo.StaticAllocaMap.find(AI);
|
|
|
|
|
|
|
|
if (SI != FuncInfo.StaticAllocaMap.end()) {
|
2018-09-05 09:27:38 +08:00
|
|
|
unsigned ResultReg =
|
|
|
|
createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
|
|
|
|
: &WebAssembly::I32RegClass);
|
|
|
|
unsigned Opc =
|
|
|
|
Subtarget->hasAddr64() ? WebAssembly::COPY_I64 : WebAssembly::COPY_I32;
|
2016-05-11 01:39:48 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
|
|
.addFrameIndex(SI->second);
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned WebAssemblyFastISel::fastMaterializeConstant(const Constant *C) {
|
|
|
|
if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
|
2018-09-05 09:27:38 +08:00
|
|
|
unsigned ResultReg =
|
|
|
|
createResultReg(Subtarget->hasAddr64() ? &WebAssembly::I64RegClass
|
|
|
|
: &WebAssembly::I32RegClass);
|
|
|
|
unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64
|
|
|
|
: WebAssembly::CONST_I32;
|
2016-05-12 12:19:09 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addGlobalAddress(GV);
|
2016-05-12 12:19:09 +08:00
|
|
|
return ResultReg;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Let target-independent code handle it.
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
bool WebAssemblyFastISel::fastLowerArguments() {
|
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const Function *F = FuncInfo.Fn;
|
|
|
|
if (F->isVarArg())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned i = 0;
|
|
|
|
for (auto const &Arg : F->args()) {
|
Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.
Rename AttributeSetImpl to AttributeListImpl to follow suit.
It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.
Reviewers: sanjoy, javed.absar, chandlerc, pete
Reviewed By: pete
Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits
Differential Revision: https://reviews.llvm.org/D31102
llvm-svn: 298393
2017-03-22 00:57:19 +08:00
|
|
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const AttributeList &Attrs = F->getAttributes();
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2017-04-14 07:12:13 +08:00
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|
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if (Attrs.hasParamAttribute(i, Attribute::ByVal) ||
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|
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Attrs.hasParamAttribute(i, Attribute::SwiftSelf) ||
|
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Attrs.hasParamAttribute(i, Attribute::SwiftError) ||
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Attrs.hasParamAttribute(i, Attribute::InAlloca) ||
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Attrs.hasParamAttribute(i, Attribute::Nest))
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2016-05-12 12:19:09 +08:00
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return false;
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Type *ArgTy = Arg.getType();
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2016-08-03 07:16:09 +08:00
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if (ArgTy->isStructTy() || ArgTy->isArrayTy())
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return false;
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if (!Subtarget->hasSIMD128() && ArgTy->isVectorTy())
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2016-05-12 12:19:09 +08:00
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|
return false;
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unsigned Opc;
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const TargetRegisterClass *RC;
|
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|
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switch (getSimpleType(ArgTy)) {
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|
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case MVT::i1:
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|
case MVT::i8:
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case MVT::i16:
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|
case MVT::i32:
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Opc = WebAssembly::ARGUMENT_I32;
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RC = &WebAssembly::I32RegClass;
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|
break;
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case MVT::i64:
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Opc = WebAssembly::ARGUMENT_I64;
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RC = &WebAssembly::I64RegClass;
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break;
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case MVT::f32:
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Opc = WebAssembly::ARGUMENT_F32;
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RC = &WebAssembly::F32RegClass;
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|
break;
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case MVT::f64:
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Opc = WebAssembly::ARGUMENT_F64;
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RC = &WebAssembly::F64RegClass;
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|
break;
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2016-08-03 07:16:09 +08:00
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case MVT::v16i8:
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Opc = WebAssembly::ARGUMENT_v16i8;
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RC = &WebAssembly::V128RegClass;
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break;
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case MVT::v8i16:
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Opc = WebAssembly::ARGUMENT_v8i16;
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RC = &WebAssembly::V128RegClass;
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break;
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case MVT::v4i32:
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Opc = WebAssembly::ARGUMENT_v4i32;
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RC = &WebAssembly::V128RegClass;
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break;
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2018-08-08 05:24:01 +08:00
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case MVT::v2i64:
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Opc = WebAssembly::ARGUMENT_v2i64;
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RC = &WebAssembly::V128RegClass;
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break;
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2016-08-03 07:16:09 +08:00
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case MVT::v4f32:
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Opc = WebAssembly::ARGUMENT_v4f32;
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RC = &WebAssembly::V128RegClass;
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break;
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2018-08-08 05:24:01 +08:00
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case MVT::v2f64:
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Opc = WebAssembly::ARGUMENT_v2f64;
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RC = &WebAssembly::V128RegClass;
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break;
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2018-03-08 12:05:37 +08:00
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case MVT::ExceptRef:
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Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
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RC = &WebAssembly::EXCEPT_REFRegClass;
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break;
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2016-05-12 12:19:09 +08:00
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default:
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return false;
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}
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unsigned ResultReg = createResultReg(RC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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2018-09-05 09:27:38 +08:00
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.addImm(i);
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2016-05-12 12:19:09 +08:00
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updateValueMap(&Arg, ResultReg);
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++i;
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}
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MRI.addLiveIn(WebAssembly::ARGUMENTS);
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|
auto *MFI = MF->getInfo<WebAssemblyFunctionInfo>();
|
2018-05-22 12:58:36 +08:00
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|
|
for (auto const &Arg : F->args()) {
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|
|
|
MVT::SimpleValueType ArgTy = getLegalType(getSimpleType(Arg.getType()));
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|
|
|
if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
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|
|
MFI->clearParamsAndResults();
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|
return false;
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}
|
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MFI->addParam(ArgTy);
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}
|
2016-05-12 12:19:09 +08:00
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2018-04-18 04:46:42 +08:00
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if (!F->getReturnType()->isVoidTy()) {
|
2018-09-05 09:27:38 +08:00
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MVT::SimpleValueType RetTy =
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getLegalType(getSimpleType(F->getReturnType()));
|
2018-05-22 12:58:36 +08:00
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if (RetTy == MVT::INVALID_SIMPLE_VALUE_TYPE) {
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MFI->clearParamsAndResults();
|
2018-04-18 04:46:42 +08:00
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|
return false;
|
2018-05-22 12:58:36 +08:00
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|
}
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MFI->addResult(RetTy);
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2018-04-18 04:46:42 +08:00
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}
|
2017-01-10 07:09:38 +08:00
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2016-05-12 12:19:09 +08:00
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|
return true;
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}
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bool WebAssemblyFastISel::selectCall(const Instruction *I) {
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const CallInst *Call = cast<CallInst>(I);
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if (Call->isMustTailCall() || Call->isInlineAsm() ||
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Call->getFunctionType()->isVarArg())
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return false;
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Function *Func = Call->getCalledFunction();
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|
|
|
if (Func && Func->isIntrinsic())
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return false;
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2017-08-25 03:53:44 +08:00
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bool IsDirect = Func != nullptr;
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|
|
if (!IsDirect && isa<ConstantExpr>(Call->getCalledValue()))
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return false;
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|
2016-05-12 12:19:09 +08:00
|
|
|
FunctionType *FuncTy = Call->getFunctionType();
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unsigned Opc;
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bool IsVoid = FuncTy->getReturnType()->isVoidTy();
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unsigned ResultReg;
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|
if (IsVoid) {
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2016-10-22 00:38:07 +08:00
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|
Opc = IsDirect ? WebAssembly::CALL_VOID : WebAssembly::PCALL_INDIRECT_VOID;
|
2016-05-12 12:19:09 +08:00
|
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|
} else {
|
2016-08-03 07:16:09 +08:00
|
|
|
if (!Subtarget->hasSIMD128() && Call->getType()->isVectorTy())
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|
return false;
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|
2016-05-12 12:19:09 +08:00
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|
MVT::SimpleValueType RetTy = getSimpleType(Call->getType());
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|
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switch (RetTy) {
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
|
2016-10-22 00:38:07 +08:00
|
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Opc = IsDirect ? WebAssembly::CALL_I32 : WebAssembly::PCALL_INDIRECT_I32;
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2016-05-12 12:19:09 +08:00
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ResultReg = createResultReg(&WebAssembly::I32RegClass);
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break;
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case MVT::i64:
|
2016-10-22 00:38:07 +08:00
|
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|
Opc = IsDirect ? WebAssembly::CALL_I64 : WebAssembly::PCALL_INDIRECT_I64;
|
2016-05-12 12:19:09 +08:00
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|
ResultReg = createResultReg(&WebAssembly::I64RegClass);
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|
break;
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case MVT::f32:
|
2016-10-22 00:38:07 +08:00
|
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|
Opc = IsDirect ? WebAssembly::CALL_F32 : WebAssembly::PCALL_INDIRECT_F32;
|
2016-05-12 12:19:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::F32RegClass);
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|
break;
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case MVT::f64:
|
2016-10-22 00:38:07 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_F64 : WebAssembly::PCALL_INDIRECT_F64;
|
2016-05-12 12:19:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::F64RegClass);
|
|
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|
break;
|
2016-08-03 07:16:09 +08:00
|
|
|
case MVT::v16i8:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v16i8
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v16i8;
|
2016-08-03 07:16:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
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|
break;
|
|
|
|
case MVT::v8i16:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v8i16
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v8i16;
|
2016-08-03 07:16:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
|
|
break;
|
|
|
|
case MVT::v4i32:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v4i32
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v4i32;
|
2016-08-03 07:16:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
|
|
break;
|
2018-08-08 05:24:01 +08:00
|
|
|
case MVT::v2i64:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v2i64
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v2i64;
|
2018-08-08 05:24:01 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
|
|
break;
|
2016-08-03 07:16:09 +08:00
|
|
|
case MVT::v4f32:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v4f32
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v4f32;
|
2016-08-03 07:16:09 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
|
|
break;
|
2018-08-08 05:24:01 +08:00
|
|
|
case MVT::v2f64:
|
2018-09-05 09:27:38 +08:00
|
|
|
Opc = IsDirect ? WebAssembly::CALL_v2f64
|
|
|
|
: WebAssembly::PCALL_INDIRECT_v2f64;
|
2018-08-08 05:24:01 +08:00
|
|
|
ResultReg = createResultReg(&WebAssembly::V128RegClass);
|
|
|
|
break;
|
2018-03-08 12:05:37 +08:00
|
|
|
case MVT::ExceptRef:
|
|
|
|
Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
|
|
|
|
: WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
|
|
|
|
ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
|
|
|
|
break;
|
2016-05-12 12:19:09 +08:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
SmallVector<unsigned, 8> Args;
|
|
|
|
for (unsigned i = 0, e = Call->getNumArgOperands(); i < e; ++i) {
|
|
|
|
Value *V = Call->getArgOperand(i);
|
|
|
|
MVT::SimpleValueType ArgTy = getSimpleType(V->getType());
|
|
|
|
if (ArgTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
|
|
|
|
return false;
|
|
|
|
|
Rename AttributeSet to AttributeList
Summary:
This class is a list of AttributeSetNodes corresponding the function
prototype of a call or function declaration. This class used to be
called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
typically accessed by parameter and return value index, so
"AttributeList" seems like a more intuitive name.
Rename AttributeSetImpl to AttributeListImpl to follow suit.
It's useful to rename this class so that we can rename AttributeSetNode
to AttributeSet later. AttributeSet is the set of attributes that apply
to a single function, argument, or return value.
Reviewers: sanjoy, javed.absar, chandlerc, pete
Reviewed By: pete
Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits
Differential Revision: https://reviews.llvm.org/D31102
llvm-svn: 298393
2017-03-22 00:57:19 +08:00
|
|
|
const AttributeList &Attrs = Call->getAttributes();
|
2017-04-14 07:12:13 +08:00
|
|
|
if (Attrs.hasParamAttribute(i, Attribute::ByVal) ||
|
|
|
|
Attrs.hasParamAttribute(i, Attribute::SwiftSelf) ||
|
|
|
|
Attrs.hasParamAttribute(i, Attribute::SwiftError) ||
|
|
|
|
Attrs.hasParamAttribute(i, Attribute::InAlloca) ||
|
|
|
|
Attrs.hasParamAttribute(i, Attribute::Nest))
|
2016-05-12 12:19:09 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned Reg;
|
|
|
|
|
2017-04-14 07:12:13 +08:00
|
|
|
if (Attrs.hasParamAttribute(i, Attribute::SExt))
|
2016-05-12 12:19:09 +08:00
|
|
|
Reg = getRegForSignedValue(V);
|
2017-04-14 07:12:13 +08:00
|
|
|
else if (Attrs.hasParamAttribute(i, Attribute::ZExt))
|
2016-05-12 12:19:09 +08:00
|
|
|
Reg = getRegForUnsignedValue(V);
|
|
|
|
else
|
|
|
|
Reg = getRegForValue(V);
|
|
|
|
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Args.push_back(Reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
|
|
|
|
|
|
|
|
if (!IsVoid)
|
|
|
|
MIB.addReg(ResultReg, RegState::Define);
|
|
|
|
|
|
|
|
if (IsDirect)
|
|
|
|
MIB.addGlobalAddress(Func);
|
2017-11-28 13:36:42 +08:00
|
|
|
else {
|
|
|
|
unsigned Reg = getRegForValue(Call->getCalledValue());
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
MIB.addReg(Reg);
|
|
|
|
}
|
2016-05-12 12:19:09 +08:00
|
|
|
|
|
|
|
for (unsigned ArgReg : Args)
|
|
|
|
MIB.addReg(ArgReg);
|
|
|
|
|
|
|
|
if (!IsVoid)
|
|
|
|
updateValueMap(Call, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectSelect(const Instruction *I) {
|
|
|
|
const SelectInst *Select = cast<SelectInst>(I);
|
|
|
|
|
|
|
|
bool Not;
|
2018-09-05 09:27:38 +08:00
|
|
|
unsigned CondReg = getRegForI1Value(Select->getCondition(), Not);
|
2016-05-12 12:19:09 +08:00
|
|
|
if (CondReg == 0)
|
|
|
|
return false;
|
|
|
|
|
2018-09-05 09:27:38 +08:00
|
|
|
unsigned TrueReg = getRegForValue(Select->getTrueValue());
|
2016-05-12 12:19:09 +08:00
|
|
|
if (TrueReg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned FalseReg = getRegForValue(Select->getFalseValue());
|
|
|
|
if (FalseReg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (Not)
|
|
|
|
std::swap(TrueReg, FalseReg);
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
const TargetRegisterClass *RC;
|
|
|
|
switch (getSimpleType(Select->getType())) {
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
|
|
|
Opc = WebAssembly::SELECT_I32;
|
|
|
|
RC = &WebAssembly::I32RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Opc = WebAssembly::SELECT_I64;
|
|
|
|
RC = &WebAssembly::I64RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
|
|
|
Opc = WebAssembly::SELECT_F32;
|
|
|
|
RC = &WebAssembly::F32RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::f64:
|
|
|
|
Opc = WebAssembly::SELECT_F64;
|
|
|
|
RC = &WebAssembly::F64RegClass;
|
|
|
|
break;
|
2018-03-08 12:05:37 +08:00
|
|
|
case MVT::ExceptRef:
|
|
|
|
Opc = WebAssembly::SELECT_EXCEPT_REF;
|
|
|
|
RC = &WebAssembly::EXCEPT_REFRegClass;
|
|
|
|
break;
|
2016-05-12 12:19:09 +08:00
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
2018-09-05 09:27:38 +08:00
|
|
|
.addReg(TrueReg)
|
|
|
|
.addReg(FalseReg)
|
|
|
|
.addReg(CondReg);
|
2016-05-12 12:19:09 +08:00
|
|
|
|
|
|
|
updateValueMap(Select, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectTrunc(const Instruction *I) {
|
|
|
|
const TruncInst *Trunc = cast<TruncInst>(I);
|
|
|
|
|
|
|
|
unsigned Reg = getRegForValue(Trunc->getOperand(0));
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (Trunc->getOperand(0)->getType()->isIntegerTy(64)) {
|
|
|
|
unsigned Result = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::I32_WRAP_I64), Result)
|
|
|
|
.addReg(Reg);
|
|
|
|
Reg = Result;
|
|
|
|
}
|
|
|
|
|
|
|
|
updateValueMap(Trunc, Reg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-05-12 00:32:42 +08:00
|
|
|
bool WebAssemblyFastISel::selectZExt(const Instruction *I) {
|
|
|
|
const ZExtInst *ZExt = cast<ZExtInst>(I);
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
const Value *Op = ZExt->getOperand(0);
|
|
|
|
MVT::SimpleValueType From = getSimpleType(Op->getType());
|
|
|
|
MVT::SimpleValueType To = getLegalType(getSimpleType(ZExt->getType()));
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned In = getRegForValue(Op);
|
|
|
|
if (In == 0)
|
|
|
|
return false;
|
|
|
|
unsigned Reg = zeroExtend(In, Op, From, To);
|
2016-05-12 00:32:42 +08:00
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
updateValueMap(ZExt, Reg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectSExt(const Instruction *I) {
|
|
|
|
const SExtInst *SExt = cast<SExtInst>(I);
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
const Value *Op = SExt->getOperand(0);
|
|
|
|
MVT::SimpleValueType From = getSimpleType(Op->getType());
|
|
|
|
MVT::SimpleValueType To = getLegalType(getSimpleType(SExt->getType()));
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned In = getRegForValue(Op);
|
|
|
|
if (In == 0)
|
|
|
|
return false;
|
|
|
|
unsigned Reg = signExtend(In, Op, From, To);
|
2016-05-12 00:32:42 +08:00
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
updateValueMap(SExt, Reg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectICmp(const Instruction *I) {
|
|
|
|
const ICmpInst *ICmp = cast<ICmpInst>(I);
|
|
|
|
|
|
|
|
bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
|
|
|
|
unsigned Opc;
|
|
|
|
bool isSigned = false;
|
|
|
|
switch (ICmp->getPredicate()) {
|
|
|
|
case ICmpInst::ICMP_EQ:
|
|
|
|
Opc = I32 ? WebAssembly::EQ_I32 : WebAssembly::EQ_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_NE:
|
|
|
|
Opc = I32 ? WebAssembly::NE_I32 : WebAssembly::NE_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_UGT:
|
|
|
|
Opc = I32 ? WebAssembly::GT_U_I32 : WebAssembly::GT_U_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_UGE:
|
|
|
|
Opc = I32 ? WebAssembly::GE_U_I32 : WebAssembly::GE_U_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_ULT:
|
|
|
|
Opc = I32 ? WebAssembly::LT_U_I32 : WebAssembly::LT_U_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_ULE:
|
|
|
|
Opc = I32 ? WebAssembly::LE_U_I32 : WebAssembly::LE_U_I64;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_SGT:
|
|
|
|
Opc = I32 ? WebAssembly::GT_S_I32 : WebAssembly::GT_S_I64;
|
|
|
|
isSigned = true;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_SGE:
|
|
|
|
Opc = I32 ? WebAssembly::GE_S_I32 : WebAssembly::GE_S_I64;
|
|
|
|
isSigned = true;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_SLT:
|
|
|
|
Opc = I32 ? WebAssembly::LT_S_I32 : WebAssembly::LT_S_I64;
|
|
|
|
isSigned = true;
|
|
|
|
break;
|
|
|
|
case ICmpInst::ICMP_SLE:
|
|
|
|
Opc = I32 ? WebAssembly::LE_S_I32 : WebAssembly::LE_S_I64;
|
|
|
|
isSigned = true;
|
|
|
|
break;
|
2018-09-05 09:27:38 +08:00
|
|
|
default:
|
|
|
|
return false;
|
2016-05-12 00:32:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned LHS = getRegForPromotedValue(ICmp->getOperand(0), isSigned);
|
|
|
|
if (LHS == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned RHS = getRegForPromotedValue(ICmp->getOperand(1), isSigned);
|
|
|
|
if (RHS == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
|
|
.addReg(LHS)
|
|
|
|
.addReg(RHS);
|
|
|
|
updateValueMap(ICmp, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectFCmp(const Instruction *I) {
|
|
|
|
const FCmpInst *FCmp = cast<FCmpInst>(I);
|
|
|
|
|
|
|
|
unsigned LHS = getRegForValue(FCmp->getOperand(0));
|
|
|
|
if (LHS == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned RHS = getRegForValue(FCmp->getOperand(1));
|
|
|
|
if (RHS == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
bool F32 = getSimpleType(FCmp->getOperand(0)->getType()) != MVT::f64;
|
|
|
|
unsigned Opc;
|
|
|
|
bool Not = false;
|
|
|
|
switch (FCmp->getPredicate()) {
|
|
|
|
case FCmpInst::FCMP_OEQ:
|
|
|
|
Opc = F32 ? WebAssembly::EQ_F32 : WebAssembly::EQ_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_UNE:
|
|
|
|
Opc = F32 ? WebAssembly::NE_F32 : WebAssembly::NE_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_OGT:
|
|
|
|
Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_OGE:
|
|
|
|
Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_OLT:
|
|
|
|
Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_OLE:
|
|
|
|
Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_UGT:
|
|
|
|
Opc = F32 ? WebAssembly::LE_F32 : WebAssembly::LE_F64;
|
|
|
|
Not = true;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_UGE:
|
|
|
|
Opc = F32 ? WebAssembly::LT_F32 : WebAssembly::LT_F64;
|
|
|
|
Not = true;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_ULT:
|
|
|
|
Opc = F32 ? WebAssembly::GE_F32 : WebAssembly::GE_F64;
|
|
|
|
Not = true;
|
|
|
|
break;
|
|
|
|
case FCmpInst::FCMP_ULE:
|
|
|
|
Opc = F32 ? WebAssembly::GT_F32 : WebAssembly::GT_F64;
|
|
|
|
Not = true;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(&WebAssembly::I32RegClass);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
|
|
|
|
.addReg(LHS)
|
|
|
|
.addReg(RHS);
|
|
|
|
|
|
|
|
if (Not)
|
|
|
|
ResultReg = notValue(ResultReg);
|
|
|
|
|
|
|
|
updateValueMap(FCmp, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
bool WebAssemblyFastISel::selectBitCast(const Instruction *I) {
|
|
|
|
// Target-independent code can handle this, except it doesn't set the dead
|
|
|
|
// flag on the ARGUMENTS clobber, so we have to do that manually in order
|
|
|
|
// to satisfy code that expects this of isBitcast() instructions.
|
|
|
|
EVT VT = TLI.getValueType(DL, I->getOperand(0)->getType());
|
|
|
|
EVT RetVT = TLI.getValueType(DL, I->getType());
|
|
|
|
if (!VT.isSimple() || !RetVT.isSimple())
|
|
|
|
return false;
|
2016-05-12 12:19:09 +08:00
|
|
|
|
2017-11-28 13:36:42 +08:00
|
|
|
unsigned In = getRegForValue(I->getOperand(0));
|
|
|
|
if (In == 0)
|
|
|
|
return false;
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
if (VT == RetVT) {
|
|
|
|
// No-op bitcast.
|
2017-11-28 13:36:42 +08:00
|
|
|
updateValueMap(I, In);
|
2016-05-12 12:19:09 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
unsigned Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(),
|
2017-11-28 13:36:42 +08:00
|
|
|
In, I->getOperand(0)->hasOneUse());
|
2016-05-11 01:39:48 +08:00
|
|
|
if (!Reg)
|
|
|
|
return false;
|
|
|
|
MachineBasicBlock::iterator Iter = FuncInfo.InsertPt;
|
|
|
|
--Iter;
|
|
|
|
assert(Iter->isBitcast());
|
|
|
|
Iter->setPhysRegsDeadExcept(ArrayRef<unsigned>(), TRI);
|
|
|
|
updateValueMap(I, Reg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectLoad(const Instruction *I) {
|
|
|
|
const LoadInst *Load = cast<LoadInst>(I);
|
|
|
|
if (Load->isAtomic())
|
|
|
|
return false;
|
2016-08-03 07:16:09 +08:00
|
|
|
if (!Subtarget->hasSIMD128() && Load->getType()->isVectorTy())
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
|
|
|
|
Address Addr;
|
|
|
|
if (!computeAddress(Load->getPointerOperand(), Addr))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// TODO: Fold a following sign-/zero-extend into the load instruction.
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
const TargetRegisterClass *RC;
|
2016-05-12 00:32:42 +08:00
|
|
|
switch (getSimpleType(Load->getType())) {
|
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
Opc = WebAssembly::LOAD8_U_I32;
|
|
|
|
RC = &WebAssembly::I32RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
Opc = WebAssembly::LOAD16_U_I32;
|
|
|
|
RC = &WebAssembly::I32RegClass;
|
2016-05-11 01:39:48 +08:00
|
|
|
break;
|
2016-05-12 00:32:42 +08:00
|
|
|
case MVT::i32:
|
|
|
|
Opc = WebAssembly::LOAD_I32;
|
|
|
|
RC = &WebAssembly::I32RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Opc = WebAssembly::LOAD_I64;
|
|
|
|
RC = &WebAssembly::I64RegClass;
|
|
|
|
break;
|
|
|
|
case MVT::f32:
|
2016-05-11 01:39:48 +08:00
|
|
|
Opc = WebAssembly::LOAD_F32;
|
|
|
|
RC = &WebAssembly::F32RegClass;
|
|
|
|
break;
|
2016-05-12 00:32:42 +08:00
|
|
|
case MVT::f64:
|
2016-05-11 01:39:48 +08:00
|
|
|
Opc = WebAssembly::LOAD_F64;
|
|
|
|
RC = &WebAssembly::F64RegClass;
|
|
|
|
break;
|
2016-05-12 00:32:42 +08:00
|
|
|
default:
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
materializeLoadStoreOperands(Addr);
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
|
|
|
|
ResultReg);
|
|
|
|
|
|
|
|
addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Load));
|
|
|
|
|
|
|
|
updateValueMap(Load, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectStore(const Instruction *I) {
|
|
|
|
const StoreInst *Store = cast<StoreInst>(I);
|
|
|
|
if (Store->isAtomic())
|
|
|
|
return false;
|
2016-08-03 07:16:09 +08:00
|
|
|
if (!Subtarget->hasSIMD128() &&
|
|
|
|
Store->getValueOperand()->getType()->isVectorTy())
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
|
|
|
|
Address Addr;
|
|
|
|
if (!computeAddress(Store->getPointerOperand(), Addr))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned Opc;
|
|
|
|
bool VTIsi1 = false;
|
2016-05-12 00:32:42 +08:00
|
|
|
switch (getSimpleType(Store->getValueOperand()->getType())) {
|
|
|
|
case MVT::i1:
|
|
|
|
VTIsi1 = true;
|
2018-02-10 06:59:01 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
2016-05-12 00:32:42 +08:00
|
|
|
case MVT::i8:
|
|
|
|
Opc = WebAssembly::STORE8_I32;
|
|
|
|
break;
|
|
|
|
case MVT::i16:
|
|
|
|
Opc = WebAssembly::STORE16_I32;
|
|
|
|
break;
|
|
|
|
case MVT::i32:
|
|
|
|
Opc = WebAssembly::STORE_I32;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Opc = WebAssembly::STORE_I64;
|
2016-05-11 01:39:48 +08:00
|
|
|
break;
|
2016-05-12 00:32:42 +08:00
|
|
|
case MVT::f32:
|
2016-05-11 01:39:48 +08:00
|
|
|
Opc = WebAssembly::STORE_F32;
|
|
|
|
break;
|
2016-05-12 00:32:42 +08:00
|
|
|
case MVT::f64:
|
2016-05-11 01:39:48 +08:00
|
|
|
Opc = WebAssembly::STORE_F64;
|
|
|
|
break;
|
2018-09-05 09:27:38 +08:00
|
|
|
default:
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
materializeLoadStoreOperands(Addr);
|
|
|
|
|
|
|
|
unsigned ValueReg = getRegForValue(Store->getValueOperand());
|
2016-08-05 02:01:52 +08:00
|
|
|
if (ValueReg == 0)
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
if (VTIsi1)
|
2016-05-12 00:32:42 +08:00
|
|
|
ValueReg = maskI1Value(ValueReg, Store->getValueOperand());
|
2016-05-11 01:39:48 +08:00
|
|
|
|
2016-10-07 06:08:28 +08:00
|
|
|
auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
|
2016-05-11 01:39:48 +08:00
|
|
|
|
|
|
|
addLoadStoreOperands(Addr, MIB, createMachineMemOperandFor(Store));
|
|
|
|
|
|
|
|
MIB.addReg(ValueReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectBr(const Instruction *I) {
|
|
|
|
const BranchInst *Br = cast<BranchInst>(I);
|
|
|
|
if (Br->isUnconditional()) {
|
|
|
|
MachineBasicBlock *MSucc = FuncInfo.MBBMap[Br->getSuccessor(0)];
|
|
|
|
fastEmitBranch(MSucc, Br->getDebugLoc());
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineBasicBlock *TBB = FuncInfo.MBBMap[Br->getSuccessor(0)];
|
|
|
|
MachineBasicBlock *FBB = FuncInfo.MBBMap[Br->getSuccessor(1)];
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
bool Not;
|
|
|
|
unsigned CondReg = getRegForI1Value(Br->getCondition(), Not);
|
2016-08-05 02:01:52 +08:00
|
|
|
if (CondReg == 0)
|
|
|
|
return false;
|
2016-05-12 12:19:09 +08:00
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
unsigned Opc = WebAssembly::BR_IF;
|
2016-05-12 12:19:09 +08:00
|
|
|
if (Not)
|
2016-05-11 01:39:48 +08:00
|
|
|
Opc = WebAssembly::BR_UNLESS;
|
|
|
|
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
|
|
|
|
.addMBB(TBB)
|
|
|
|
.addReg(CondReg);
|
2016-08-03 07:16:09 +08:00
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
finishCondBranch(Br->getParent(), TBB, FBB);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectRet(const Instruction *I) {
|
|
|
|
if (!FuncInfo.CanLowerReturn)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
const ReturnInst *Ret = cast<ReturnInst>(I);
|
|
|
|
|
|
|
|
if (Ret->getNumOperands() == 0) {
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::RETURN_VOID));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
Value *RV = Ret->getOperand(0);
|
2016-08-03 07:16:09 +08:00
|
|
|
if (!Subtarget->hasSIMD128() && RV->getType()->isVectorTy())
|
|
|
|
return false;
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
unsigned Opc;
|
2016-05-12 00:32:42 +08:00
|
|
|
switch (getSimpleType(RV->getType())) {
|
2018-09-05 09:27:38 +08:00
|
|
|
case MVT::i1:
|
|
|
|
case MVT::i8:
|
|
|
|
case MVT::i16:
|
|
|
|
case MVT::i32:
|
2016-05-12 00:32:42 +08:00
|
|
|
Opc = WebAssembly::RETURN_I32;
|
|
|
|
break;
|
|
|
|
case MVT::i64:
|
|
|
|
Opc = WebAssembly::RETURN_I64;
|
2016-05-11 01:39:48 +08:00
|
|
|
break;
|
2016-08-03 07:16:09 +08:00
|
|
|
case MVT::f32:
|
|
|
|
Opc = WebAssembly::RETURN_F32;
|
|
|
|
break;
|
|
|
|
case MVT::f64:
|
|
|
|
Opc = WebAssembly::RETURN_F64;
|
|
|
|
break;
|
|
|
|
case MVT::v16i8:
|
|
|
|
Opc = WebAssembly::RETURN_v16i8;
|
|
|
|
break;
|
|
|
|
case MVT::v8i16:
|
|
|
|
Opc = WebAssembly::RETURN_v8i16;
|
|
|
|
break;
|
|
|
|
case MVT::v4i32:
|
|
|
|
Opc = WebAssembly::RETURN_v4i32;
|
|
|
|
break;
|
2018-08-08 05:24:01 +08:00
|
|
|
case MVT::v2i64:
|
|
|
|
Opc = WebAssembly::RETURN_v2i64;
|
|
|
|
break;
|
2016-08-03 07:16:09 +08:00
|
|
|
case MVT::v4f32:
|
|
|
|
Opc = WebAssembly::RETURN_v4f32;
|
|
|
|
break;
|
2018-08-08 05:24:01 +08:00
|
|
|
case MVT::v2f64:
|
|
|
|
Opc = WebAssembly::RETURN_v2f64;
|
|
|
|
break;
|
2018-03-08 12:05:37 +08:00
|
|
|
case MVT::ExceptRef:
|
|
|
|
Opc = WebAssembly::RETURN_EXCEPT_REF;
|
|
|
|
break;
|
2018-09-05 09:27:38 +08:00
|
|
|
default:
|
|
|
|
return false;
|
2016-05-11 01:39:48 +08:00
|
|
|
}
|
|
|
|
|
2016-05-12 12:19:09 +08:00
|
|
|
unsigned Reg;
|
|
|
|
if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::SExt))
|
|
|
|
Reg = getRegForSignedValue(RV);
|
|
|
|
else if (FuncInfo.Fn->getAttributes().hasAttribute(0, Attribute::ZExt))
|
|
|
|
Reg = getRegForUnsignedValue(RV);
|
|
|
|
else
|
|
|
|
Reg = getRegForValue(RV);
|
|
|
|
|
2016-08-05 02:01:52 +08:00
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
2016-05-11 01:39:48 +08:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)).addReg(Reg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::selectUnreachable(const Instruction *I) {
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
|
|
|
TII.get(WebAssembly::UNREACHABLE));
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WebAssemblyFastISel::fastSelectInstruction(const Instruction *I) {
|
|
|
|
switch (I->getOpcode()) {
|
2016-05-12 12:19:09 +08:00
|
|
|
case Instruction::Call:
|
|
|
|
if (selectCall(I))
|
|
|
|
return true;
|
|
|
|
break;
|
2018-09-05 09:27:38 +08:00
|
|
|
case Instruction::Select:
|
|
|
|
return selectSelect(I);
|
|
|
|
case Instruction::Trunc:
|
|
|
|
return selectTrunc(I);
|
|
|
|
case Instruction::ZExt:
|
|
|
|
return selectZExt(I);
|
|
|
|
case Instruction::SExt:
|
|
|
|
return selectSExt(I);
|
|
|
|
case Instruction::ICmp:
|
|
|
|
return selectICmp(I);
|
|
|
|
case Instruction::FCmp:
|
|
|
|
return selectFCmp(I);
|
|
|
|
case Instruction::BitCast:
|
|
|
|
return selectBitCast(I);
|
|
|
|
case Instruction::Load:
|
|
|
|
return selectLoad(I);
|
|
|
|
case Instruction::Store:
|
|
|
|
return selectStore(I);
|
|
|
|
case Instruction::Br:
|
|
|
|
return selectBr(I);
|
|
|
|
case Instruction::Ret:
|
|
|
|
return selectRet(I);
|
|
|
|
case Instruction::Unreachable:
|
|
|
|
return selectUnreachable(I);
|
|
|
|
default:
|
|
|
|
break;
|
2015-08-25 02:44:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Fall back to target-independent instruction selection.
|
|
|
|
return selectOperator(I, I->getOpcode());
|
|
|
|
}
|
|
|
|
|
|
|
|
FastISel *WebAssembly::createFastISel(FunctionLoweringInfo &FuncInfo,
|
|
|
|
const TargetLibraryInfo *LibInfo) {
|
|
|
|
return new WebAssemblyFastISel(FuncInfo, LibInfo);
|
|
|
|
}
|