2017-02-22 07:46:04 +08:00
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; RUN: llc -march=amdgcn -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=TOVGPR %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling,-mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
2013-11-28 05:23:29 +08:00
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; These tests check that the compiler won't crash when it needs to spill
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; SGPRs.
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2016-01-23 13:42:38 +08:00
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|
@ddxy_lds = external addrspace(3) global [64 x i32]
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|
2017-02-22 07:46:04 +08:00
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|
; GCN-LABEL: {{^}}main:
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; GCN: s_wqm
|
2015-12-01 05:15:53 +08:00
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; Make sure not emitting unused scratch resource descriptor setup
|
2017-02-22 07:46:04 +08:00
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; GCN-NOT: s_mov_b32
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; GCN-NOT: s_mov_b32
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; GCN-NOT: s_mov_b32
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; GCN-NOT: s_mov_b32
|
2015-12-01 05:15:53 +08:00
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2017-02-22 07:46:04 +08:00
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; GCN: s_mov_b32 m0
|
2015-12-01 05:15:53 +08:00
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2017-02-22 03:12:08 +08:00
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; Make sure scratch space isn't being used for SGPR->VGPR spills
|
2015-12-01 05:15:53 +08:00
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2013-11-28 05:23:29 +08:00
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; Writing to M0 from an SMRD instruction will hang the GPU.
|
2017-02-22 07:46:04 +08:00
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; GCN-NOT: s_buffer_load_dword m0
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; GCN: s_endpgm
|
2017-02-22 03:12:08 +08:00
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2017-02-23 06:23:32 +08:00
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; TOVGPR: ScratchSize: 0{{$}}
|
2018-02-14 02:00:25 +08:00
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define amdgpu_ps void @main([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
|
2013-11-28 05:23:29 +08:00
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main_body:
|
2018-02-14 02:00:25 +08:00
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%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
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%tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
|
2017-06-29 05:38:50 +08:00
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|
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 96)
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|
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 100)
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%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 104)
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|
%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 112)
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|
%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 116)
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|
%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 120)
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|
%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 128)
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|
%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 132)
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|
%tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 140)
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|
%tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 144)
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%tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 160)
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|
%tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 176)
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|
%tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 180)
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|
%tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 184)
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|
%tmp36 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 192)
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|
%tmp37 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 196)
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|
%tmp38 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 200)
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|
%tmp39 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 208)
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|
%tmp40 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 212)
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|
%tmp41 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 216)
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|
%tmp42 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 224)
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|
%tmp43 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 240)
|
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|
%tmp44 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 244)
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|
%tmp45 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 248)
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|
%tmp46 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 256)
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|
%tmp47 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 272)
|
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|
%tmp48 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 276)
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|
%tmp49 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 280)
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|
%tmp50 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 288)
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|
%tmp51 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 292)
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|
%tmp52 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 296)
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|
%tmp53 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 304)
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|
|
|
%tmp54 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 308)
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|
%tmp55 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 312)
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|
%tmp56 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 368)
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|
%tmp57 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 372)
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|
|
%tmp58 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 376)
|
|
|
|
|
%tmp59 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 384)
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp60 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
|
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|
%tmp61 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp60, !tbaa !0
|
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|
%tmp62 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
|
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|
%tmp63 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp62, !tbaa !0
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp63.bc = bitcast <4 x i32> %tmp63 to <4 x i32>
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp64 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 1
|
|
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|
|
%tmp65 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp64, !tbaa !0
|
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|
%tmp66 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 1
|
|
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|
%tmp67 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp66, !tbaa !0
|
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|
%tmp68 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 2
|
|
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|
%tmp69 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp68, !tbaa !0
|
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|
%tmp70 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 2
|
|
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|
%tmp71 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp70, !tbaa !0
|
|
|
|
|
%tmp72 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 3
|
|
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|
%tmp73 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp72, !tbaa !0
|
|
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|
|
%tmp74 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 3
|
|
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|
%tmp75 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp74, !tbaa !0
|
|
|
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|
%tmp76 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 4
|
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|
%tmp77 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp76, !tbaa !0
|
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|
%tmp78 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 4
|
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|
%tmp79 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp78, !tbaa !0
|
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|
%tmp80 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 5
|
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|
%tmp81 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp80, !tbaa !0
|
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|
%tmp82 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 5
|
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|
%tmp83 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp82, !tbaa !0
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|
%tmp84 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 6
|
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|
%tmp85 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp84, !tbaa !0
|
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|
%tmp86 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 6
|
|
|
|
|
%tmp87 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp86, !tbaa !0
|
|
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|
%tmp88 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 7
|
|
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|
%tmp89 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp88, !tbaa !0
|
|
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|
%tmp90 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 7
|
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|
|
|
%tmp91 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp90, !tbaa !0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i = extractelement <2 x i32> %arg6, i32 0
|
|
|
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|
%j.i = extractelement <2 x i32> %arg6, i32 1
|
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|
|
|
%i.f.i = bitcast i32 %i.i to float
|
|
|
|
|
%j.f.i = bitcast i32 %j.i to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
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|
|
|
|
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i91 = extractelement <2 x i32> %arg6, i32 0
|
|
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|
|
%j.i92 = extractelement <2 x i32> %arg6, i32 1
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|
%i.f.i93 = bitcast i32 %i.i91 to float
|
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|
|
%j.f.i94 = bitcast i32 %j.i92 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 1, i32 0, i32 %arg4) #0
|
|
|
|
|
%p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 1, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i85 = extractelement <2 x i32> %arg6, i32 0
|
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|
%j.i86 = extractelement <2 x i32> %arg6, i32 1
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|
%i.f.i87 = bitcast i32 %i.i85 to float
|
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|
%j.f.i88 = bitcast i32 %j.i86 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 0, i32 1, i32 %arg4) #0
|
|
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|
%p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 0, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i79 = extractelement <2 x i32> %arg6, i32 0
|
|
|
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|
%j.i80 = extractelement <2 x i32> %arg6, i32 1
|
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|
%i.f.i81 = bitcast i32 %i.i79 to float
|
|
|
|
|
%j.f.i82 = bitcast i32 %j.i80 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 1, i32 1, i32 %arg4) #0
|
|
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|
|
%p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 1, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i73 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i74 = extractelement <2 x i32> %arg6, i32 1
|
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|
|
|
%i.f.i75 = bitcast i32 %i.i73 to float
|
|
|
|
|
%j.f.i76 = bitcast i32 %j.i74 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 2, i32 1, i32 %arg4) #0
|
|
|
|
|
%p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 2, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i67 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i68 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i69 = bitcast i32 %i.i67 to float
|
|
|
|
|
%j.f.i70 = bitcast i32 %j.i68 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i61 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i62 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i63 = bitcast i32 %i.i61 to float
|
|
|
|
|
%j.f.i64 = bitcast i32 %j.i62 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i55 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i56 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i57 = bitcast i32 %i.i55 to float
|
|
|
|
|
%j.f.i58 = bitcast i32 %j.i56 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i49 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i50 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i51 = bitcast i32 %i.i49 to float
|
|
|
|
|
%j.f.i52 = bitcast i32 %j.i50 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 0, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 0, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i43 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i44 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i45 = bitcast i32 %i.i43 to float
|
|
|
|
|
%j.f.i46 = bitcast i32 %j.i44 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 1, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 1, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i37 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i38 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i39 = bitcast i32 %i.i37 to float
|
|
|
|
|
%j.f.i40 = bitcast i32 %j.i38 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 2, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 2, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i31 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i32 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i33 = bitcast i32 %i.i31 to float
|
|
|
|
|
%j.f.i34 = bitcast i32 %j.i32 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 0, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 0, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i25 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i26 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i27 = bitcast i32 %i.i25 to float
|
|
|
|
|
%j.f.i28 = bitcast i32 %j.i26 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 1, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 1, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i19 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i20 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i21 = bitcast i32 %i.i19 to float
|
|
|
|
|
%j.f.i22 = bitcast i32 %j.i20 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 2, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 2, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i13 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i14 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i15 = bitcast i32 %i.i13 to float
|
|
|
|
|
%j.f.i16 = bitcast i32 %j.i14 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 0, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 0, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i7 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i8 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i9 = bitcast i32 %i.i7 to float
|
|
|
|
|
%j.f.i10 = bitcast i32 %j.i8 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 1, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 1, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i1 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i2 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i3 = bitcast i32 %i.i1 to float
|
|
|
|
|
%j.f.i4 = bitcast i32 %j.i2 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 2, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 2, i32 5, i32 %arg4) #0
|
2016-06-18 05:18:41 +08:00
|
|
|
%mbcnt.lo.0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
|
|
|
|
%tmp109 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp110 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp109
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp111 = bitcast float %p2.i to i32
|
2016-01-23 13:42:43 +08:00
|
|
|
store i32 %tmp111, i32 addrspace(3)* %tmp110
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp112 = bitcast float %p2.i96 to i32
|
2016-01-23 13:42:43 +08:00
|
|
|
store i32 %tmp112, i32 addrspace(3)* %tmp110
|
2016-06-18 05:18:41 +08:00
|
|
|
%mbcnt.lo.1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
|
|
|
|
%tmp113 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.1)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp114 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp113
|
|
|
|
|
%tmp115 = and i32 %tmp113, -4
|
|
|
|
|
%tmp116 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp115
|
|
|
|
|
%tmp117 = add i32 %tmp115, 1
|
|
|
|
|
%tmp118 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp117
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp119 = bitcast float %p2.i to i32
|
2016-01-23 13:42:43 +08:00
|
|
|
store i32 %tmp119, i32 addrspace(3)* %tmp114
|
|
|
|
|
%tmp120 = load i32, i32 addrspace(3)* %tmp116
|
|
|
|
|
%tmp121 = bitcast i32 %tmp120 to float
|
|
|
|
|
%tmp122 = load i32, i32 addrspace(3)* %tmp118
|
|
|
|
|
%tmp123 = bitcast i32 %tmp122 to float
|
|
|
|
|
%tmp124 = fsub float %tmp123, %tmp121
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp125 = bitcast float %p2.i96 to i32
|
2016-01-23 13:42:43 +08:00
|
|
|
store i32 %tmp125, i32 addrspace(3)* %tmp114
|
|
|
|
|
%tmp126 = load i32, i32 addrspace(3)* %tmp116
|
|
|
|
|
%tmp127 = bitcast i32 %tmp126 to float
|
|
|
|
|
%tmp128 = load i32, i32 addrspace(3)* %tmp118
|
|
|
|
|
%tmp129 = bitcast i32 %tmp128 to float
|
|
|
|
|
%tmp130 = fsub float %tmp129, %tmp127
|
|
|
|
|
%tmp131 = insertelement <4 x float> undef, float %tmp124, i32 0
|
|
|
|
|
%tmp132 = insertelement <4 x float> %tmp131, float %tmp130, i32 1
|
|
|
|
|
%tmp133 = insertelement <4 x float> %tmp132, float %tmp130, i32 2
|
|
|
|
|
%tmp134 = insertelement <4 x float> %tmp133, float %tmp130, i32 3
|
|
|
|
|
%tmp135 = extractelement <4 x float> %tmp134, i32 0
|
|
|
|
|
%tmp136 = extractelement <4 x float> %tmp134, i32 1
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp137 = fmul float %tmp59, %p2.i
|
|
|
|
|
%tmp138 = fmul float %tmp59, %p2.i96
|
|
|
|
|
%tmp139 = fmul float %tmp59, %p2.i96
|
|
|
|
|
%tmp140 = fmul float %tmp59, %p2.i96
|
2016-06-18 05:18:41 +08:00
|
|
|
%mbcnt.lo.2 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
|
|
|
|
%tmp141 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.2)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp142 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp141
|
|
|
|
|
%tmp143 = bitcast float %tmp137 to i32
|
|
|
|
|
store i32 %tmp143, i32 addrspace(3)* %tmp142
|
|
|
|
|
%tmp144 = bitcast float %tmp138 to i32
|
|
|
|
|
store i32 %tmp144, i32 addrspace(3)* %tmp142
|
|
|
|
|
%tmp145 = bitcast float %tmp139 to i32
|
|
|
|
|
store i32 %tmp145, i32 addrspace(3)* %tmp142
|
|
|
|
|
%tmp146 = bitcast float %tmp140 to i32
|
|
|
|
|
store i32 %tmp146, i32 addrspace(3)* %tmp142
|
2016-06-18 05:18:41 +08:00
|
|
|
%mbcnt.lo.3 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
|
|
|
|
%tmp147 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.3)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp148 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp147
|
|
|
|
|
%tmp149 = and i32 %tmp147, -4
|
|
|
|
|
%tmp150 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp149
|
|
|
|
|
%tmp151 = add i32 %tmp149, 2
|
|
|
|
|
%tmp152 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp151
|
|
|
|
|
%tmp153 = bitcast float %tmp137 to i32
|
|
|
|
|
store i32 %tmp153, i32 addrspace(3)* %tmp148
|
|
|
|
|
%tmp154 = load i32, i32 addrspace(3)* %tmp150
|
|
|
|
|
%tmp155 = bitcast i32 %tmp154 to float
|
|
|
|
|
%tmp156 = load i32, i32 addrspace(3)* %tmp152
|
|
|
|
|
%tmp157 = bitcast i32 %tmp156 to float
|
|
|
|
|
%tmp158 = fsub float %tmp157, %tmp155
|
|
|
|
|
%tmp159 = bitcast float %tmp138 to i32
|
|
|
|
|
store i32 %tmp159, i32 addrspace(3)* %tmp148
|
|
|
|
|
%tmp160 = load i32, i32 addrspace(3)* %tmp150
|
|
|
|
|
%tmp161 = bitcast i32 %tmp160 to float
|
|
|
|
|
%tmp162 = load i32, i32 addrspace(3)* %tmp152
|
|
|
|
|
%tmp163 = bitcast i32 %tmp162 to float
|
|
|
|
|
%tmp164 = fsub float %tmp163, %tmp161
|
|
|
|
|
%tmp165 = bitcast float %tmp139 to i32
|
|
|
|
|
store i32 %tmp165, i32 addrspace(3)* %tmp148
|
|
|
|
|
%tmp166 = load i32, i32 addrspace(3)* %tmp150
|
|
|
|
|
%tmp167 = bitcast i32 %tmp166 to float
|
|
|
|
|
%tmp168 = load i32, i32 addrspace(3)* %tmp152
|
|
|
|
|
%tmp169 = bitcast i32 %tmp168 to float
|
|
|
|
|
%tmp170 = fsub float %tmp169, %tmp167
|
|
|
|
|
%tmp171 = bitcast float %tmp140 to i32
|
|
|
|
|
store i32 %tmp171, i32 addrspace(3)* %tmp148
|
|
|
|
|
%tmp172 = load i32, i32 addrspace(3)* %tmp150
|
|
|
|
|
%tmp173 = bitcast i32 %tmp172 to float
|
|
|
|
|
%tmp174 = load i32, i32 addrspace(3)* %tmp152
|
|
|
|
|
%tmp175 = bitcast i32 %tmp174 to float
|
|
|
|
|
%tmp176 = fsub float %tmp175, %tmp173
|
|
|
|
|
%tmp177 = insertelement <4 x float> undef, float %tmp158, i32 0
|
|
|
|
|
%tmp178 = insertelement <4 x float> %tmp177, float %tmp164, i32 1
|
|
|
|
|
%tmp179 = insertelement <4 x float> %tmp178, float %tmp170, i32 2
|
|
|
|
|
%tmp180 = insertelement <4 x float> %tmp179, float %tmp176, i32 3
|
|
|
|
|
%tmp181 = extractelement <4 x float> %tmp180, i32 0
|
|
|
|
|
%tmp182 = extractelement <4 x float> %tmp180, i32 1
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp183 = fdiv float 1.000000e+00, %p2.i78
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp184 = fmul float %tmp32, %tmp183
|
|
|
|
|
%tmp185 = fcmp uge float 1.000000e+00, %tmp184
|
|
|
|
|
%tmp186 = select i1 %tmp185, float %tmp184, float 1.000000e+00
|
|
|
|
|
%tmp187 = fmul float %tmp186, %tmp29
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp188 = call float @llvm.ceil.f32(float %tmp187)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp189 = fcmp uge float 3.000000e+00, %tmp188
|
|
|
|
|
%tmp190 = select i1 %tmp189, float 3.000000e+00, float %tmp188
|
|
|
|
|
%tmp191 = fdiv float 1.000000e+00, %tmp190
|
|
|
|
|
%tmp192 = fdiv float 1.000000e+00, %tmp29
|
|
|
|
|
%tmp193 = fmul float %tmp190, %tmp192
|
|
|
|
|
%tmp194 = fmul float %tmp30, %tmp193
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp195 = fmul float %p2.i90, %p2.i90
|
|
|
|
|
%tmp196 = fmul float %p2.i84, %p2.i84
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp197 = fadd float %tmp196, %tmp195
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp198 = fmul float %p2.i78, %p2.i78
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp199 = fadd float %tmp197, %tmp198
|
|
|
|
|
%tmp200 = call float @llvm.amdgcn.rsq.f32(float %tmp199)
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp201 = fmul float %p2.i90, %tmp200
|
|
|
|
|
%tmp202 = fmul float %p2.i84, %tmp200
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp203 = fmul float %tmp201, %tmp28
|
|
|
|
|
%tmp204 = fmul float %tmp202, %tmp28
|
|
|
|
|
%tmp205 = fmul float %tmp203, -1.000000e+00
|
|
|
|
|
%tmp206 = fmul float %tmp204, 1.000000e+00
|
|
|
|
|
%tmp207 = fmul float %tmp205, %tmp31
|
|
|
|
|
%tmp208 = fmul float %tmp206, %tmp31
|
|
|
|
|
%tmp209 = fsub float -0.000000e+00, %tmp207
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp210 = fadd float %p2.i, %tmp209
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp211 = fsub float -0.000000e+00, %tmp208
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp212 = fadd float %p2.i96, %tmp211
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp213 = fmul float %tmp205, %tmp191
|
|
|
|
|
%tmp214 = fmul float %tmp206, %tmp191
|
|
|
|
|
%tmp215 = fmul float -1.000000e+00, %tmp191
|
2013-11-28 05:23:29 +08:00
|
|
|
br label %LOOP
|
|
|
|
|
|
|
|
|
|
LOOP: ; preds = %ENDIF, %main_body
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp24.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp257, %ENDIF ]
|
|
|
|
|
%temp28.0 = phi float [ %tmp210, %main_body ], [ %tmp252, %ENDIF ]
|
|
|
|
|
%temp29.0 = phi float [ %tmp212, %main_body ], [ %tmp254, %ENDIF ]
|
|
|
|
|
%temp30.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp256, %ENDIF ]
|
|
|
|
|
%tmp224 = fcmp oge float %temp24.0, %tmp190
|
|
|
|
|
%tmp225 = sext i1 %tmp224 to i32
|
|
|
|
|
%tmp226 = bitcast i32 %tmp225 to float
|
|
|
|
|
%tmp227 = bitcast float %tmp226 to i32
|
|
|
|
|
%tmp228 = icmp ne i32 %tmp227, 0
|
|
|
|
|
br i1 %tmp228, label %IF, label %ENDIF
|
2013-11-28 05:23:29 +08:00
|
|
|
|
|
|
|
|
IF: ; preds = %LOOP
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp229 = bitcast float %tmp135 to i32
|
|
|
|
|
%tmp230 = bitcast float %tmp181 to i32
|
|
|
|
|
%tmp231 = bitcast float %tmp136 to i32
|
|
|
|
|
%tmp232 = bitcast float %tmp182 to i32
|
|
|
|
|
%tmp233 = insertelement <8 x i32> undef, i32 %tmp229, i32 0
|
|
|
|
|
%tmp234 = insertelement <8 x i32> %tmp233, i32 %tmp230, i32 1
|
|
|
|
|
%tmp235 = insertelement <8 x i32> %tmp234, i32 %tmp231, i32 2
|
|
|
|
|
%tmp236 = insertelement <8 x i32> %tmp235, i32 %tmp232, i32 3
|
2013-11-28 05:23:29 +08:00
|
|
|
br label %LOOP65
|
|
|
|
|
|
|
|
|
|
ENDIF: ; preds = %LOOP
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp243 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.0, float %temp29.0, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp244 = extractelement <4 x float> %tmp243, i32 3
|
|
|
|
|
%tmp245 = fcmp oge float %temp30.0, %tmp244
|
|
|
|
|
%tmp246 = sext i1 %tmp245 to i32
|
|
|
|
|
%tmp247 = bitcast i32 %tmp246 to float
|
|
|
|
|
%tmp248 = bitcast float %tmp247 to i32
|
|
|
|
|
%tmp249 = and i32 %tmp248, 1065353216
|
|
|
|
|
%tmp250 = bitcast i32 %tmp249 to float
|
|
|
|
|
%tmp251 = fmul float %tmp213, %tmp250
|
|
|
|
|
%tmp252 = fadd float %tmp251, %temp28.0
|
|
|
|
|
%tmp253 = fmul float %tmp214, %tmp250
|
|
|
|
|
%tmp254 = fadd float %tmp253, %temp29.0
|
|
|
|
|
%tmp255 = fmul float %tmp215, %tmp250
|
|
|
|
|
%tmp256 = fadd float %tmp255, %temp30.0
|
|
|
|
|
%tmp257 = fadd float %temp24.0, 1.000000e+00
|
2013-11-28 05:23:29 +08:00
|
|
|
br label %LOOP
|
|
|
|
|
|
|
|
|
|
LOOP65: ; preds = %ENDIF66, %IF
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp24.1 = phi float [ 0.000000e+00, %IF ], [ %tmp609, %ENDIF66 ]
|
|
|
|
|
%temp28.1 = phi float [ %temp28.0, %IF ], [ %tmp604, %ENDIF66 ]
|
|
|
|
|
%temp29.1 = phi float [ %temp29.0, %IF ], [ %tmp606, %ENDIF66 ]
|
|
|
|
|
%temp30.1 = phi float [ %temp30.0, %IF ], [ %tmp608, %ENDIF66 ]
|
|
|
|
|
%temp32.0 = phi float [ 1.000000e+00, %IF ], [ %tmp610, %ENDIF66 ]
|
|
|
|
|
%tmp258 = fcmp oge float %temp24.1, %tmp194
|
|
|
|
|
%tmp259 = sext i1 %tmp258 to i32
|
|
|
|
|
%tmp260 = bitcast i32 %tmp259 to float
|
|
|
|
|
%tmp261 = bitcast float %tmp260 to i32
|
|
|
|
|
%tmp262 = icmp ne i32 %tmp261, 0
|
|
|
|
|
br i1 %tmp262, label %IF67, label %ENDIF66
|
2013-11-28 05:23:29 +08:00
|
|
|
|
|
|
|
|
IF67: ; preds = %LOOP65
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp67.bc = bitcast <4 x i32> %tmp67 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp277 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp65, <4 x i32> %tmp67.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp278 = extractelement <4 x float> %tmp277, i32 0
|
|
|
|
|
%tmp279 = extractelement <4 x float> %tmp277, i32 1
|
|
|
|
|
%tmp280 = extractelement <4 x float> %tmp277, i32 2
|
|
|
|
|
%tmp281 = extractelement <4 x float> %tmp277, i32 3
|
|
|
|
|
%tmp282 = fmul float %tmp281, %tmp46
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp83.bc = bitcast <4 x i32> %tmp83 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp297 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp81, <4 x i32> %tmp83.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp298 = extractelement <4 x float> %tmp297, i32 0
|
|
|
|
|
%tmp299 = extractelement <4 x float> %tmp297, i32 1
|
|
|
|
|
%tmp300 = extractelement <4 x float> %tmp297, i32 2
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp79.bc = bitcast <4 x i32> %tmp79 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp315 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp77, <4 x i32> %tmp79.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp316 = extractelement <4 x float> %tmp315, i32 0
|
|
|
|
|
%tmp317 = extractelement <4 x float> %tmp315, i32 1
|
|
|
|
|
%tmp318 = extractelement <4 x float> %tmp315, i32 2
|
|
|
|
|
%tmp319 = fmul float %tmp316, %tmp22
|
|
|
|
|
%tmp320 = fmul float %tmp317, %tmp23
|
|
|
|
|
%tmp321 = fmul float %tmp318, %tmp24
|
|
|
|
|
%tmp322 = fmul float %tmp298, %tmp25
|
|
|
|
|
%tmp323 = fadd float %tmp322, %tmp319
|
|
|
|
|
%tmp324 = fmul float %tmp299, %tmp26
|
|
|
|
|
%tmp325 = fadd float %tmp324, %tmp320
|
|
|
|
|
%tmp326 = fmul float %tmp300, %tmp27
|
|
|
|
|
%tmp327 = fadd float %tmp326, %tmp321
|
|
|
|
|
%tmp328 = fadd float %tmp278, %tmp323
|
|
|
|
|
%tmp329 = fadd float %tmp279, %tmp325
|
|
|
|
|
%tmp330 = fadd float %tmp280, %tmp327
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp345 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp346 = extractelement <4 x float> %tmp345, i32 0
|
|
|
|
|
%tmp347 = extractelement <4 x float> %tmp345, i32 1
|
|
|
|
|
%tmp348 = extractelement <4 x float> %tmp345, i32 2
|
|
|
|
|
%tmp349 = fadd float %tmp346, -5.000000e-01
|
|
|
|
|
%tmp350 = fadd float %tmp347, -5.000000e-01
|
|
|
|
|
%tmp351 = fadd float %tmp348, -5.000000e-01
|
|
|
|
|
%tmp352 = fmul float %tmp349, %tmp349
|
|
|
|
|
%tmp353 = fmul float %tmp350, %tmp350
|
|
|
|
|
%tmp354 = fadd float %tmp353, %tmp352
|
|
|
|
|
%tmp355 = fmul float %tmp351, %tmp351
|
|
|
|
|
%tmp356 = fadd float %tmp354, %tmp355
|
|
|
|
|
%tmp357 = call float @llvm.amdgcn.rsq.f32(float %tmp356)
|
|
|
|
|
%tmp358 = fmul float %tmp349, %tmp357
|
|
|
|
|
%tmp359 = fmul float %tmp350, %tmp357
|
|
|
|
|
%tmp360 = fmul float %tmp351, %tmp357
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp71.bc = bitcast <4 x i32> %tmp71 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp375 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp69, <4 x i32> %tmp71.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp376 = extractelement <4 x float> %tmp375, i32 0
|
|
|
|
|
%tmp377 = extractelement <4 x float> %tmp375, i32 1
|
|
|
|
|
%tmp378 = extractelement <4 x float> %tmp375, i32 2
|
|
|
|
|
%tmp379 = extractelement <4 x float> %tmp375, i32 3
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp380 = fsub float -0.000000e+00, %p2.i90
|
|
|
|
|
%tmp381 = fsub float -0.000000e+00, %p2.i84
|
|
|
|
|
%tmp382 = fsub float -0.000000e+00, %p2.i78
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp383 = fmul float %tmp358, %tmp380
|
|
|
|
|
%tmp384 = fmul float %tmp359, %tmp381
|
|
|
|
|
%tmp385 = fadd float %tmp384, %tmp383
|
|
|
|
|
%tmp386 = fmul float %tmp360, %tmp382
|
|
|
|
|
%tmp387 = fadd float %tmp385, %tmp386
|
|
|
|
|
%tmp388 = fmul float %tmp387, %tmp358
|
|
|
|
|
%tmp389 = fmul float %tmp387, %tmp359
|
|
|
|
|
%tmp390 = fmul float %tmp387, %tmp360
|
|
|
|
|
%tmp391 = fmul float 2.000000e+00, %tmp388
|
|
|
|
|
%tmp392 = fmul float 2.000000e+00, %tmp389
|
|
|
|
|
%tmp393 = fmul float 2.000000e+00, %tmp390
|
|
|
|
|
%tmp394 = fsub float -0.000000e+00, %tmp391
|
|
|
|
|
%tmp395 = fadd float %tmp380, %tmp394
|
|
|
|
|
%tmp396 = fsub float -0.000000e+00, %tmp392
|
|
|
|
|
%tmp397 = fadd float %tmp381, %tmp396
|
|
|
|
|
%tmp398 = fsub float -0.000000e+00, %tmp393
|
|
|
|
|
%tmp399 = fadd float %tmp382, %tmp398
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp400 = fmul float %tmp395, %p2.i72
|
|
|
|
|
%tmp401 = fmul float %tmp395, %p2.i66
|
|
|
|
|
%tmp402 = fmul float %tmp395, %p2.i60
|
|
|
|
|
%tmp403 = fmul float %tmp397, %p2.i54
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp404 = fadd float %tmp403, %tmp400
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp405 = fmul float %tmp397, %p2.i48
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp406 = fadd float %tmp405, %tmp401
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp407 = fmul float %tmp397, %p2.i42
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp408 = fadd float %tmp407, %tmp402
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp409 = fmul float %tmp399, %p2.i36
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp410 = fadd float %tmp409, %tmp404
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp411 = fmul float %tmp399, %p2.i30
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp412 = fadd float %tmp411, %tmp406
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp413 = fmul float %tmp399, %p2.i24
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp414 = fadd float %tmp413, %tmp408
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp87.bc = bitcast <4 x i32> %tmp87 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp429 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp85, <4 x i32> %tmp87.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp430 = extractelement <4 x float> %tmp429, i32 0
|
|
|
|
|
%tmp431 = extractelement <4 x float> %tmp429, i32 1
|
|
|
|
|
%tmp432 = extractelement <4 x float> %tmp429, i32 2
|
|
|
|
|
%tmp433 = fmul float %tmp47, %tmp410
|
|
|
|
|
%tmp434 = fmul float %tmp48, %tmp410
|
|
|
|
|
%tmp435 = fmul float %tmp49, %tmp410
|
|
|
|
|
%tmp436 = fmul float %tmp50, %tmp412
|
|
|
|
|
%tmp437 = fadd float %tmp436, %tmp433
|
|
|
|
|
%tmp438 = fmul float %tmp51, %tmp412
|
|
|
|
|
%tmp439 = fadd float %tmp438, %tmp434
|
|
|
|
|
%tmp440 = fmul float %tmp52, %tmp412
|
|
|
|
|
%tmp441 = fadd float %tmp440, %tmp435
|
|
|
|
|
%tmp442 = fmul float %tmp53, %tmp414
|
|
|
|
|
%tmp443 = fadd float %tmp442, %tmp437
|
|
|
|
|
%tmp444 = fmul float %tmp54, %tmp414
|
|
|
|
|
%tmp445 = fadd float %tmp444, %tmp439
|
|
|
|
|
%tmp446 = fmul float %tmp55, %tmp414
|
|
|
|
|
%tmp447 = fadd float %tmp446, %tmp441
|
|
|
|
|
%tmp448 = insertelement <4 x float> undef, float %tmp443, i32 0
|
|
|
|
|
%tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1
|
|
|
|
|
%tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2
|
|
|
|
|
%tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3
|
2017-02-17 03:09:04 +08:00
|
|
|
%tmp451.x = extractelement <4 x float> %tmp451, i32 0
|
|
|
|
|
%tmp451.y = extractelement <4 x float> %tmp451, i32 1
|
|
|
|
|
%tmp451.z = extractelement <4 x float> %tmp451, i32 2
|
|
|
|
|
%cubetc = call float @llvm.amdgcn.cubetc(float %tmp451.x, float %tmp451.y, float %tmp451.z)
|
|
|
|
|
%cubesc = call float @llvm.amdgcn.cubesc(float %tmp451.x, float %tmp451.y, float %tmp451.z)
|
|
|
|
|
%cubema = call float @llvm.amdgcn.cubema(float %tmp451.x, float %tmp451.y, float %tmp451.z)
|
|
|
|
|
%cubeid = call float @llvm.amdgcn.cubeid(float %tmp451.x, float %tmp451.y, float %tmp451.z)
|
|
|
|
|
%tmp452.0 = insertelement <4 x float> undef, float %cubetc, i32 0
|
|
|
|
|
%tmp452.1 = insertelement <4 x float> %tmp452.0, float %cubesc, i32 1
|
|
|
|
|
%tmp452.2 = insertelement <4 x float> %tmp452.1, float %cubema, i32 2
|
|
|
|
|
%tmp452 = insertelement <4 x float> %tmp452.2, float %cubeid, i32 3
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp453 = extractelement <4 x float> %tmp452, i32 0
|
|
|
|
|
%tmp454 = extractelement <4 x float> %tmp452, i32 1
|
|
|
|
|
%tmp455 = extractelement <4 x float> %tmp452, i32 2
|
|
|
|
|
%tmp456 = extractelement <4 x float> %tmp452, i32 3
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp457 = call float @llvm.fabs.f32(float %tmp455)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp458 = fdiv float 1.000000e+00, %tmp457
|
|
|
|
|
%tmp459 = fmul float %tmp453, %tmp458
|
|
|
|
|
%tmp460 = fadd float %tmp459, 1.500000e+00
|
|
|
|
|
%tmp461 = fmul float %tmp454, %tmp458
|
|
|
|
|
%tmp462 = fadd float %tmp461, 1.500000e+00
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp91.bc = bitcast <4 x i32> %tmp91 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp470 = call <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32 15, float %tmp462, float %tmp460, float %tmp456, <8 x i32> %tmp89, <4 x i32> %tmp91.bc, i1 0, i32 0, i32 0) #0
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp471 = extractelement <4 x float> %tmp470, i32 0
|
|
|
|
|
%tmp472 = extractelement <4 x float> %tmp470, i32 1
|
|
|
|
|
%tmp473 = extractelement <4 x float> %tmp470, i32 2
|
|
|
|
|
%tmp474 = fmul float %tmp430, %tmp471
|
|
|
|
|
%tmp475 = fadd float %tmp474, %tmp328
|
|
|
|
|
%tmp476 = fmul float %tmp431, %tmp472
|
|
|
|
|
%tmp477 = fadd float %tmp476, %tmp329
|
|
|
|
|
%tmp478 = fmul float %tmp432, %tmp473
|
|
|
|
|
%tmp479 = fadd float %tmp478, %tmp330
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp480 = fmul float %p2.i18, %p2.i18
|
|
|
|
|
%tmp481 = fmul float %p2.i12, %p2.i12
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp482 = fadd float %tmp481, %tmp480
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp483 = fmul float %p2.i6, %p2.i6
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp484 = fadd float %tmp482, %tmp483
|
|
|
|
|
%tmp485 = call float @llvm.amdgcn.rsq.f32(float %tmp484)
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp486 = fmul float %p2.i18, %tmp485
|
|
|
|
|
%tmp487 = fmul float %p2.i12, %tmp485
|
|
|
|
|
%tmp488 = fmul float %p2.i6, %tmp485
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp489 = fmul float %tmp376, %tmp39
|
|
|
|
|
%tmp490 = fmul float %tmp377, %tmp40
|
|
|
|
|
%tmp491 = fmul float %tmp378, %tmp41
|
|
|
|
|
%tmp492 = fmul float %tmp358, %tmp486
|
|
|
|
|
%tmp493 = fmul float %tmp359, %tmp487
|
|
|
|
|
%tmp494 = fadd float %tmp493, %tmp492
|
|
|
|
|
%tmp495 = fmul float %tmp360, %tmp488
|
|
|
|
|
%tmp496 = fadd float %tmp494, %tmp495
|
|
|
|
|
%tmp497 = fmul float %tmp496, %tmp358
|
|
|
|
|
%tmp498 = fmul float %tmp496, %tmp359
|
|
|
|
|
%tmp499 = fmul float %tmp496, %tmp360
|
|
|
|
|
%tmp500 = fmul float 2.000000e+00, %tmp497
|
|
|
|
|
%tmp501 = fmul float 2.000000e+00, %tmp498
|
|
|
|
|
%tmp502 = fmul float 2.000000e+00, %tmp499
|
|
|
|
|
%tmp503 = fsub float -0.000000e+00, %tmp500
|
|
|
|
|
%tmp504 = fadd float %tmp486, %tmp503
|
|
|
|
|
%tmp505 = fsub float -0.000000e+00, %tmp501
|
|
|
|
|
%tmp506 = fadd float %tmp487, %tmp505
|
|
|
|
|
%tmp507 = fsub float -0.000000e+00, %tmp502
|
|
|
|
|
%tmp508 = fadd float %tmp488, %tmp507
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp509 = fmul float %p2.i90, %p2.i90
|
|
|
|
|
%tmp510 = fmul float %p2.i84, %p2.i84
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp511 = fadd float %tmp510, %tmp509
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp512 = fmul float %p2.i78, %p2.i78
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp513 = fadd float %tmp511, %tmp512
|
|
|
|
|
%tmp514 = call float @llvm.amdgcn.rsq.f32(float %tmp513)
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp515 = fmul float %p2.i90, %tmp514
|
|
|
|
|
%tmp516 = fmul float %p2.i84, %tmp514
|
|
|
|
|
%tmp517 = fmul float %p2.i78, %tmp514
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp518 = fmul float %tmp504, %tmp515
|
|
|
|
|
%tmp519 = fmul float %tmp506, %tmp516
|
|
|
|
|
%tmp520 = fadd float %tmp519, %tmp518
|
|
|
|
|
%tmp521 = fmul float %tmp508, %tmp517
|
|
|
|
|
%tmp522 = fadd float %tmp520, %tmp521
|
|
|
|
|
%tmp523 = fsub float -0.000000e+00, %tmp522
|
|
|
|
|
%tmp524 = fcmp uge float %tmp523, 0.000000e+00
|
|
|
|
|
%tmp525 = select i1 %tmp524, float %tmp523, float 0.000000e+00
|
|
|
|
|
%tmp526 = fmul float %tmp42, %tmp379
|
|
|
|
|
%tmp527 = fadd float %tmp526, 1.000000e+00
|
|
|
|
|
%tmp528 = call float @llvm.pow.f32(float %tmp525, float %tmp527)
|
|
|
|
|
%tmp529 = fmul float %tmp475, %tmp36
|
|
|
|
|
%tmp530 = fmul float %tmp477, %tmp37
|
|
|
|
|
%tmp531 = fmul float %tmp479, %tmp38
|
|
|
|
|
%tmp532 = fmul float %tmp358, %tmp486
|
|
|
|
|
%tmp533 = fmul float %tmp359, %tmp487
|
|
|
|
|
%tmp534 = fadd float %tmp533, %tmp532
|
|
|
|
|
%tmp535 = fmul float %tmp360, %tmp488
|
|
|
|
|
%tmp536 = fadd float %tmp534, %tmp535
|
|
|
|
|
%tmp537 = fcmp uge float %tmp536, 0.000000e+00
|
|
|
|
|
%tmp538 = select i1 %tmp537, float %tmp536, float 0.000000e+00
|
|
|
|
|
%tmp539 = fmul float %tmp529, %tmp538
|
|
|
|
|
%tmp540 = fmul float %tmp530, %tmp538
|
|
|
|
|
%tmp541 = fmul float %tmp531, %tmp538
|
|
|
|
|
%tmp542 = fmul float %tmp489, %tmp528
|
|
|
|
|
%tmp543 = fadd float %tmp542, %tmp539
|
|
|
|
|
%tmp544 = fmul float %tmp490, %tmp528
|
|
|
|
|
%tmp545 = fadd float %tmp544, %tmp540
|
|
|
|
|
%tmp546 = fmul float %tmp491, %tmp528
|
|
|
|
|
%tmp547 = fadd float %tmp546, %tmp541
|
|
|
|
|
%tmp548 = fmul float %tmp475, %tmp33
|
|
|
|
|
%tmp549 = fmul float %tmp477, %tmp34
|
|
|
|
|
%tmp550 = fmul float %tmp479, %tmp35
|
|
|
|
|
%tmp551 = fmul float %tmp543, %tmp56
|
|
|
|
|
%tmp552 = fadd float %tmp551, %tmp548
|
|
|
|
|
%tmp553 = fmul float %tmp545, %tmp57
|
|
|
|
|
%tmp554 = fadd float %tmp553, %tmp549
|
|
|
|
|
%tmp555 = fmul float %tmp547, %tmp58
|
|
|
|
|
%tmp556 = fadd float %tmp555, %tmp550
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp75.bc = bitcast <4 x i32> %tmp75 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp571 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp73, <4 x i32> %tmp75.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp572 = extractelement <4 x float> %tmp571, i32 0
|
|
|
|
|
%tmp573 = extractelement <4 x float> %tmp571, i32 1
|
|
|
|
|
%tmp574 = extractelement <4 x float> %tmp571, i32 2
|
|
|
|
|
%tmp575 = fmul float %tmp572, %tmp43
|
|
|
|
|
%tmp576 = fadd float %tmp575, %tmp552
|
|
|
|
|
%tmp577 = fmul float %tmp573, %tmp44
|
|
|
|
|
%tmp578 = fadd float %tmp577, %tmp554
|
|
|
|
|
%tmp579 = fmul float %tmp574, %tmp45
|
|
|
|
|
%tmp580 = fadd float %tmp579, %tmp556
|
2017-02-22 08:27:34 +08:00
|
|
|
%tmp581 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp576, float %tmp578)
|
|
|
|
|
%tmp583 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp580, float %tmp282)
|
|
|
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp581, <2 x half> %tmp583, i1 true, i1 true) #0
|
2013-11-28 05:23:29 +08:00
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
ENDIF66: ; preds = %LOOP65
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp591 = call <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32 15, float %tmp135, float %tmp181, float %tmp136, float %tmp182, float %temp28.1, float %temp29.1, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp592 = extractelement <4 x float> %tmp591, i32 3
|
|
|
|
|
%tmp593 = fcmp oge float %temp30.1, %tmp592
|
|
|
|
|
%tmp594 = sext i1 %tmp593 to i32
|
|
|
|
|
%tmp595 = bitcast i32 %tmp594 to float
|
|
|
|
|
%tmp596 = bitcast float %tmp595 to i32
|
|
|
|
|
%tmp597 = and i32 %tmp596, 1065353216
|
|
|
|
|
%tmp598 = bitcast i32 %tmp597 to float
|
|
|
|
|
%tmp599 = fmul float 5.000000e-01, %temp32.0
|
|
|
|
|
%tmp600 = fsub float -0.000000e+00, %tmp599
|
|
|
|
|
%tmp601 = fmul float %tmp598, %temp32.0
|
|
|
|
|
%tmp602 = fadd float %tmp601, %tmp600
|
|
|
|
|
%tmp603 = fmul float %tmp213, %tmp602
|
|
|
|
|
%tmp604 = fadd float %tmp603, %temp28.1
|
|
|
|
|
%tmp605 = fmul float %tmp214, %tmp602
|
|
|
|
|
%tmp606 = fadd float %tmp605, %temp29.1
|
|
|
|
|
%tmp607 = fmul float %tmp215, %tmp602
|
|
|
|
|
%tmp608 = fadd float %tmp607, %temp30.1
|
|
|
|
|
%tmp609 = fadd float %temp24.1, 1.000000e+00
|
|
|
|
|
%tmp610 = fmul float %temp32.0, 5.000000e-01
|
2013-11-28 05:23:29 +08:00
|
|
|
br label %LOOP65
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-22 07:46:04 +08:00
|
|
|
; GCN-LABEL: {{^}}main1:
|
|
|
|
|
; GCN: s_endpgm
|
2017-02-23 06:23:32 +08:00
|
|
|
; TOVGPR: ScratchSize: 0{{$}}
|
2018-02-14 02:00:25 +08:00
|
|
|
define amdgpu_ps void @main1([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
|
2013-11-28 05:23:35 +08:00
|
|
|
main_body:
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
|
|
|
|
|
%tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 0)
|
|
|
|
|
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 4)
|
|
|
|
|
%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 8)
|
|
|
|
|
%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 12)
|
|
|
|
|
%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 28)
|
|
|
|
|
%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 48)
|
|
|
|
|
%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 52)
|
|
|
|
|
%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 56)
|
|
|
|
|
%tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 64)
|
|
|
|
|
%tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 68)
|
|
|
|
|
%tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 72)
|
|
|
|
|
%tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 76)
|
|
|
|
|
%tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 128)
|
|
|
|
|
%tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 132)
|
|
|
|
|
%tmp36 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 144)
|
|
|
|
|
%tmp37 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 148)
|
|
|
|
|
%tmp38 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 152)
|
|
|
|
|
%tmp39 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 160)
|
|
|
|
|
%tmp40 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 164)
|
|
|
|
|
%tmp41 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 168)
|
|
|
|
|
%tmp42 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 172)
|
|
|
|
|
%tmp43 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 176)
|
|
|
|
|
%tmp44 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 180)
|
|
|
|
|
%tmp45 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 184)
|
|
|
|
|
%tmp46 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 192)
|
|
|
|
|
%tmp47 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 196)
|
|
|
|
|
%tmp48 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 200)
|
|
|
|
|
%tmp49 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 208)
|
|
|
|
|
%tmp50 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 212)
|
|
|
|
|
%tmp51 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 216)
|
|
|
|
|
%tmp52 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 220)
|
|
|
|
|
%tmp53 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 236)
|
|
|
|
|
%tmp54 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 240)
|
|
|
|
|
%tmp55 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 244)
|
|
|
|
|
%tmp56 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 248)
|
|
|
|
|
%tmp57 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 252)
|
|
|
|
|
%tmp58 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 256)
|
|
|
|
|
%tmp59 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 260)
|
|
|
|
|
%tmp60 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 264)
|
|
|
|
|
%tmp61 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 268)
|
|
|
|
|
%tmp62 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 272)
|
|
|
|
|
%tmp63 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 276)
|
|
|
|
|
%tmp64 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 280)
|
|
|
|
|
%tmp65 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 284)
|
|
|
|
|
%tmp66 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 288)
|
|
|
|
|
%tmp67 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 292)
|
|
|
|
|
%tmp68 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 464)
|
|
|
|
|
%tmp69 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 468)
|
|
|
|
|
%tmp70 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 472)
|
|
|
|
|
%tmp71 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 496)
|
|
|
|
|
%tmp72 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 500)
|
|
|
|
|
%tmp73 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 504)
|
|
|
|
|
%tmp74 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 512)
|
|
|
|
|
%tmp75 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 516)
|
|
|
|
|
%tmp76 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 524)
|
|
|
|
|
%tmp77 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 532)
|
|
|
|
|
%tmp78 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 536)
|
|
|
|
|
%tmp79 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 540)
|
|
|
|
|
%tmp80 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 544)
|
|
|
|
|
%tmp81 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 548)
|
|
|
|
|
%tmp82 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 552)
|
|
|
|
|
%tmp83 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 556)
|
|
|
|
|
%tmp84 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 560)
|
|
|
|
|
%tmp85 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 564)
|
|
|
|
|
%tmp86 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 568)
|
|
|
|
|
%tmp87 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 572)
|
|
|
|
|
%tmp88 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 576)
|
|
|
|
|
%tmp89 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 580)
|
|
|
|
|
%tmp90 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 584)
|
|
|
|
|
%tmp91 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 588)
|
|
|
|
|
%tmp92 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 592)
|
|
|
|
|
%tmp93 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 596)
|
|
|
|
|
%tmp94 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 600)
|
|
|
|
|
%tmp95 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 604)
|
|
|
|
|
%tmp96 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 608)
|
|
|
|
|
%tmp97 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 612)
|
|
|
|
|
%tmp98 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 616)
|
|
|
|
|
%tmp99 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 624)
|
|
|
|
|
%tmp100 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 628)
|
|
|
|
|
%tmp101 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 632)
|
|
|
|
|
%tmp102 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 636)
|
|
|
|
|
%tmp103 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 640)
|
|
|
|
|
%tmp104 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 644)
|
|
|
|
|
%tmp105 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 648)
|
|
|
|
|
%tmp106 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 652)
|
|
|
|
|
%tmp107 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 656)
|
|
|
|
|
%tmp108 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 660)
|
|
|
|
|
%tmp109 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 664)
|
|
|
|
|
%tmp110 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 668)
|
|
|
|
|
%tmp111 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 672)
|
|
|
|
|
%tmp112 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 676)
|
|
|
|
|
%tmp113 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 680)
|
|
|
|
|
%tmp114 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 684)
|
|
|
|
|
%tmp115 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 688)
|
|
|
|
|
%tmp116 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 692)
|
|
|
|
|
%tmp117 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 696)
|
|
|
|
|
%tmp118 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 700)
|
|
|
|
|
%tmp119 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 704)
|
|
|
|
|
%tmp120 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 708)
|
|
|
|
|
%tmp121 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 712)
|
|
|
|
|
%tmp122 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 716)
|
|
|
|
|
%tmp123 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 864)
|
|
|
|
|
%tmp124 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 868)
|
2018-02-14 02:00:25 +08:00
|
|
|
%tmp125 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
|
|
|
|
|
%tmp126 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp125, !tbaa !0
|
|
|
|
|
%tmp127 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
|
|
|
|
|
%tmp128 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp127, !tbaa !0
|
|
|
|
|
%tmp129 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 1
|
|
|
|
|
%tmp130 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp129, !tbaa !0
|
|
|
|
|
%tmp131 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 1
|
|
|
|
|
%tmp132 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp131, !tbaa !0
|
|
|
|
|
%tmp133 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 2
|
|
|
|
|
%tmp134 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp133, !tbaa !0
|
|
|
|
|
%tmp135 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 2
|
|
|
|
|
%tmp136 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp135, !tbaa !0
|
|
|
|
|
%tmp137 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 3
|
|
|
|
|
%tmp138 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp137, !tbaa !0
|
|
|
|
|
%tmp139 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 3
|
|
|
|
|
%tmp140 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp139, !tbaa !0
|
|
|
|
|
%tmp141 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 4
|
|
|
|
|
%tmp142 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp141, !tbaa !0
|
|
|
|
|
%tmp143 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 4
|
|
|
|
|
%tmp144 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp143, !tbaa !0
|
|
|
|
|
%tmp145 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 5
|
|
|
|
|
%tmp146 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp145, !tbaa !0
|
|
|
|
|
%tmp147 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 5
|
|
|
|
|
%tmp148 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp147, !tbaa !0
|
|
|
|
|
%tmp149 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 6
|
|
|
|
|
%tmp150 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp149, !tbaa !0
|
|
|
|
|
%tmp151 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 6
|
|
|
|
|
%tmp152 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp151, !tbaa !0
|
|
|
|
|
%tmp153 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 7
|
|
|
|
|
%tmp154 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp153, !tbaa !0
|
|
|
|
|
%tmp155 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 7
|
|
|
|
|
%tmp156 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp155, !tbaa !0
|
|
|
|
|
%tmp157 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 8
|
|
|
|
|
%tmp158 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp157, !tbaa !0
|
|
|
|
|
%tmp159 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 8
|
|
|
|
|
%tmp160 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp159, !tbaa !0
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp161 = fcmp ugt float %arg17, 0.000000e+00
|
|
|
|
|
%tmp162 = select i1 %tmp161, float 1.000000e+00, float 0.000000e+00
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i = bitcast i32 %i.i to float
|
|
|
|
|
%j.f.i = bitcast i32 %j.i to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
|
|
|
|
|
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i181 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i182 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i183 = bitcast i32 %i.i181 to float
|
|
|
|
|
%j.f.i184 = bitcast i32 %j.i182 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i185 = call float @llvm.amdgcn.interp.p1(float %i.f.i183, i32 1, i32 0, i32 %arg4) #0
|
|
|
|
|
%p2.i186 = call float @llvm.amdgcn.interp.p2(float %p1.i185, float %j.f.i184, i32 1, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i175 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i176 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i177 = bitcast i32 %i.i175 to float
|
|
|
|
|
%j.f.i178 = bitcast i32 %j.i176 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i179 = call float @llvm.amdgcn.interp.p1(float %i.f.i177, i32 2, i32 0, i32 %arg4) #0
|
|
|
|
|
%p2.i180 = call float @llvm.amdgcn.interp.p2(float %p1.i179, float %j.f.i178, i32 2, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i169 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i170 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i171 = bitcast i32 %i.i169 to float
|
|
|
|
|
%j.f.i172 = bitcast i32 %j.i170 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i173 = call float @llvm.amdgcn.interp.p1(float %i.f.i171, i32 3, i32 0, i32 %arg4) #0
|
|
|
|
|
%p2.i174 = call float @llvm.amdgcn.interp.p2(float %p1.i173, float %j.f.i172, i32 3, i32 0, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i163 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i164 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i165 = bitcast i32 %i.i163 to float
|
|
|
|
|
%j.f.i166 = bitcast i32 %j.i164 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i167 = call float @llvm.amdgcn.interp.p1(float %i.f.i165, i32 0, i32 1, i32 %arg4) #0
|
|
|
|
|
%p2.i168 = call float @llvm.amdgcn.interp.p2(float %p1.i167, float %j.f.i166, i32 0, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i157 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i158 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i159 = bitcast i32 %i.i157 to float
|
|
|
|
|
%j.f.i160 = bitcast i32 %j.i158 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i161 = call float @llvm.amdgcn.interp.p1(float %i.f.i159, i32 1, i32 1, i32 %arg4) #0
|
|
|
|
|
%p2.i162 = call float @llvm.amdgcn.interp.p2(float %p1.i161, float %j.f.i160, i32 1, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i151 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i152 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i153 = bitcast i32 %i.i151 to float
|
|
|
|
|
%j.f.i154 = bitcast i32 %j.i152 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i155 = call float @llvm.amdgcn.interp.p1(float %i.f.i153, i32 2, i32 1, i32 %arg4) #0
|
|
|
|
|
%p2.i156 = call float @llvm.amdgcn.interp.p2(float %p1.i155, float %j.f.i154, i32 2, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i145 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i146 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i147 = bitcast i32 %i.i145 to float
|
|
|
|
|
%j.f.i148 = bitcast i32 %j.i146 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i149 = call float @llvm.amdgcn.interp.p1(float %i.f.i147, i32 3, i32 1, i32 %arg4) #0
|
|
|
|
|
%p2.i150 = call float @llvm.amdgcn.interp.p2(float %p1.i149, float %j.f.i148, i32 3, i32 1, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i139 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i140 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i141 = bitcast i32 %i.i139 to float
|
|
|
|
|
%j.f.i142 = bitcast i32 %j.i140 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i143 = call float @llvm.amdgcn.interp.p1(float %i.f.i141, i32 0, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i144 = call float @llvm.amdgcn.interp.p2(float %p1.i143, float %j.f.i142, i32 0, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i133 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i134 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i135 = bitcast i32 %i.i133 to float
|
|
|
|
|
%j.f.i136 = bitcast i32 %j.i134 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i137 = call float @llvm.amdgcn.interp.p1(float %i.f.i135, i32 1, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i138 = call float @llvm.amdgcn.interp.p2(float %p1.i137, float %j.f.i136, i32 1, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i127 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i128 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i129 = bitcast i32 %i.i127 to float
|
|
|
|
|
%j.f.i130 = bitcast i32 %j.i128 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i131 = call float @llvm.amdgcn.interp.p1(float %i.f.i129, i32 2, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i132 = call float @llvm.amdgcn.interp.p2(float %p1.i131, float %j.f.i130, i32 2, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i121 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i122 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i123 = bitcast i32 %i.i121 to float
|
|
|
|
|
%j.f.i124 = bitcast i32 %j.i122 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i125 = call float @llvm.amdgcn.interp.p1(float %i.f.i123, i32 3, i32 2, i32 %arg4) #0
|
|
|
|
|
%p2.i126 = call float @llvm.amdgcn.interp.p2(float %p1.i125, float %j.f.i124, i32 3, i32 2, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i115 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i116 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i117 = bitcast i32 %i.i115 to float
|
|
|
|
|
%j.f.i118 = bitcast i32 %j.i116 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i119 = call float @llvm.amdgcn.interp.p1(float %i.f.i117, i32 0, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i120 = call float @llvm.amdgcn.interp.p2(float %p1.i119, float %j.f.i118, i32 0, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i109 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i110 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i111 = bitcast i32 %i.i109 to float
|
|
|
|
|
%j.f.i112 = bitcast i32 %j.i110 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i113 = call float @llvm.amdgcn.interp.p1(float %i.f.i111, i32 1, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i114 = call float @llvm.amdgcn.interp.p2(float %p1.i113, float %j.f.i112, i32 1, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i103 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i104 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i105 = bitcast i32 %i.i103 to float
|
|
|
|
|
%j.f.i106 = bitcast i32 %j.i104 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i107 = call float @llvm.amdgcn.interp.p1(float %i.f.i105, i32 2, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i108 = call float @llvm.amdgcn.interp.p2(float %p1.i107, float %j.f.i106, i32 2, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i97 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i98 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i99 = bitcast i32 %i.i97 to float
|
|
|
|
|
%j.f.i100 = bitcast i32 %j.i98 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i101 = call float @llvm.amdgcn.interp.p1(float %i.f.i99, i32 3, i32 3, i32 %arg4) #0
|
|
|
|
|
%p2.i102 = call float @llvm.amdgcn.interp.p2(float %p1.i101, float %j.f.i100, i32 3, i32 3, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i91 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i92 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i93 = bitcast i32 %i.i91 to float
|
|
|
|
|
%j.f.i94 = bitcast i32 %j.i92 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i95 = call float @llvm.amdgcn.interp.p1(float %i.f.i93, i32 0, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i96 = call float @llvm.amdgcn.interp.p2(float %p1.i95, float %j.f.i94, i32 0, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i85 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i86 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i87 = bitcast i32 %i.i85 to float
|
|
|
|
|
%j.f.i88 = bitcast i32 %j.i86 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i89 = call float @llvm.amdgcn.interp.p1(float %i.f.i87, i32 1, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i90 = call float @llvm.amdgcn.interp.p2(float %p1.i89, float %j.f.i88, i32 1, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i79 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i80 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i81 = bitcast i32 %i.i79 to float
|
|
|
|
|
%j.f.i82 = bitcast i32 %j.i80 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i83 = call float @llvm.amdgcn.interp.p1(float %i.f.i81, i32 2, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i84 = call float @llvm.amdgcn.interp.p2(float %p1.i83, float %j.f.i82, i32 2, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i73 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i74 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i75 = bitcast i32 %i.i73 to float
|
|
|
|
|
%j.f.i76 = bitcast i32 %j.i74 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i77 = call float @llvm.amdgcn.interp.p1(float %i.f.i75, i32 3, i32 4, i32 %arg4) #0
|
|
|
|
|
%p2.i78 = call float @llvm.amdgcn.interp.p2(float %p1.i77, float %j.f.i76, i32 3, i32 4, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i67 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i68 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i69 = bitcast i32 %i.i67 to float
|
|
|
|
|
%j.f.i70 = bitcast i32 %j.i68 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i71 = call float @llvm.amdgcn.interp.p1(float %i.f.i69, i32 0, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i72 = call float @llvm.amdgcn.interp.p2(float %p1.i71, float %j.f.i70, i32 0, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i61 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i62 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i63 = bitcast i32 %i.i61 to float
|
|
|
|
|
%j.f.i64 = bitcast i32 %j.i62 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i65 = call float @llvm.amdgcn.interp.p1(float %i.f.i63, i32 1, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i66 = call float @llvm.amdgcn.interp.p2(float %p1.i65, float %j.f.i64, i32 1, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i55 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i56 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i57 = bitcast i32 %i.i55 to float
|
|
|
|
|
%j.f.i58 = bitcast i32 %j.i56 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i59 = call float @llvm.amdgcn.interp.p1(float %i.f.i57, i32 2, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i60 = call float @llvm.amdgcn.interp.p2(float %p1.i59, float %j.f.i58, i32 2, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i49 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i50 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i51 = bitcast i32 %i.i49 to float
|
|
|
|
|
%j.f.i52 = bitcast i32 %j.i50 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i53 = call float @llvm.amdgcn.interp.p1(float %i.f.i51, i32 3, i32 5, i32 %arg4) #0
|
|
|
|
|
%p2.i54 = call float @llvm.amdgcn.interp.p2(float %p1.i53, float %j.f.i52, i32 3, i32 5, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i43 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i44 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i45 = bitcast i32 %i.i43 to float
|
|
|
|
|
%j.f.i46 = bitcast i32 %j.i44 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i47 = call float @llvm.amdgcn.interp.p1(float %i.f.i45, i32 0, i32 6, i32 %arg4) #0
|
|
|
|
|
%p2.i48 = call float @llvm.amdgcn.interp.p2(float %p1.i47, float %j.f.i46, i32 0, i32 6, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i37 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i38 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i39 = bitcast i32 %i.i37 to float
|
|
|
|
|
%j.f.i40 = bitcast i32 %j.i38 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i41 = call float @llvm.amdgcn.interp.p1(float %i.f.i39, i32 1, i32 6, i32 %arg4) #0
|
|
|
|
|
%p2.i42 = call float @llvm.amdgcn.interp.p2(float %p1.i41, float %j.f.i40, i32 1, i32 6, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i31 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i32 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i33 = bitcast i32 %i.i31 to float
|
|
|
|
|
%j.f.i34 = bitcast i32 %j.i32 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i35 = call float @llvm.amdgcn.interp.p1(float %i.f.i33, i32 2, i32 6, i32 %arg4) #0
|
|
|
|
|
%p2.i36 = call float @llvm.amdgcn.interp.p2(float %p1.i35, float %j.f.i34, i32 2, i32 6, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i25 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i26 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i27 = bitcast i32 %i.i25 to float
|
|
|
|
|
%j.f.i28 = bitcast i32 %j.i26 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i29 = call float @llvm.amdgcn.interp.p1(float %i.f.i27, i32 3, i32 6, i32 %arg4) #0
|
|
|
|
|
%p2.i30 = call float @llvm.amdgcn.interp.p2(float %p1.i29, float %j.f.i28, i32 3, i32 6, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i19 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i20 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i21 = bitcast i32 %i.i19 to float
|
|
|
|
|
%j.f.i22 = bitcast i32 %j.i20 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i23 = call float @llvm.amdgcn.interp.p1(float %i.f.i21, i32 0, i32 7, i32 %arg4) #0
|
|
|
|
|
%p2.i24 = call float @llvm.amdgcn.interp.p2(float %p1.i23, float %j.f.i22, i32 0, i32 7, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i13 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i14 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i15 = bitcast i32 %i.i13 to float
|
|
|
|
|
%j.f.i16 = bitcast i32 %j.i14 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i17 = call float @llvm.amdgcn.interp.p1(float %i.f.i15, i32 1, i32 7, i32 %arg4) #0
|
|
|
|
|
%p2.i18 = call float @llvm.amdgcn.interp.p2(float %p1.i17, float %j.f.i16, i32 1, i32 7, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i7 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i8 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i9 = bitcast i32 %i.i7 to float
|
|
|
|
|
%j.f.i10 = bitcast i32 %j.i8 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i11 = call float @llvm.amdgcn.interp.p1(float %i.f.i9, i32 2, i32 7, i32 %arg4) #0
|
|
|
|
|
%p2.i12 = call float @llvm.amdgcn.interp.p2(float %p1.i11, float %j.f.i10, i32 2, i32 7, i32 %arg4) #0
|
2017-02-16 10:01:13 +08:00
|
|
|
%i.i1 = extractelement <2 x i32> %arg6, i32 0
|
|
|
|
|
%j.i2 = extractelement <2 x i32> %arg6, i32 1
|
|
|
|
|
%i.f.i3 = bitcast i32 %i.i1 to float
|
|
|
|
|
%j.f.i4 = bitcast i32 %j.i2 to float
|
2017-02-22 07:46:04 +08:00
|
|
|
%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 3, i32 7, i32 %arg4) #0
|
|
|
|
|
%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 3, i32 7, i32 %arg4) #0
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp195 = fmul float %arg14, %tmp123
|
|
|
|
|
%tmp196 = fadd float %tmp195, %tmp124
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i = call float @llvm.maxnum.f32(float %tmp162, float 0.000000e+00)
|
|
|
|
|
%clamp.i = call float @llvm.minnum.f32(float %max.0.i, float 1.000000e+00)
|
|
|
|
|
%tmp201 = bitcast float %clamp.i to i32
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp202 = icmp ne i32 %tmp201, 0
|
|
|
|
|
%. = select i1 %tmp202, float -1.000000e+00, float 1.000000e+00
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp203 = fsub float -0.000000e+00, %p2.i
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp204 = fadd float %tmp43, %tmp203
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp205 = fsub float -0.000000e+00, %p2.i186
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp206 = fadd float %tmp44, %tmp205
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp207 = fsub float -0.000000e+00, %p2.i180
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp208 = fadd float %tmp45, %tmp207
|
|
|
|
|
%tmp209 = fmul float %tmp204, %tmp204
|
|
|
|
|
%tmp210 = fmul float %tmp206, %tmp206
|
|
|
|
|
%tmp211 = fadd float %tmp210, %tmp209
|
|
|
|
|
%tmp212 = fmul float %tmp208, %tmp208
|
|
|
|
|
%tmp213 = fadd float %tmp211, %tmp212
|
|
|
|
|
%tmp214 = call float @llvm.amdgcn.rsq.f32(float %tmp213)
|
|
|
|
|
%tmp215 = fmul float %tmp204, %tmp214
|
|
|
|
|
%tmp216 = fmul float %tmp206, %tmp214
|
|
|
|
|
%tmp217 = fmul float %tmp208, %tmp214
|
|
|
|
|
%tmp218 = fmul float %., %tmp53
|
|
|
|
|
%tmp219 = fmul float %arg13, %tmp46
|
|
|
|
|
%tmp220 = fmul float %tmp196, %tmp47
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp132.bc = bitcast <4 x i32> %tmp132 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp225 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i132, float %p2.i126, <8 x i32> %tmp130, <4 x i32> %tmp132.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp226 = extractelement <4 x float> %tmp225, i32 0
|
|
|
|
|
%tmp227 = extractelement <4 x float> %tmp225, i32 1
|
|
|
|
|
%tmp228 = extractelement <4 x float> %tmp225, i32 2
|
|
|
|
|
%tmp229 = extractelement <4 x float> %tmp225, i32 3
|
|
|
|
|
%tmp230 = fmul float %tmp226, 0x4012611180000000
|
|
|
|
|
%tmp231 = fmul float %tmp227, 0x4012611180000000
|
|
|
|
|
%tmp232 = fmul float %tmp228, 0x4012611180000000
|
|
|
|
|
%one.sub.a.i = fsub float 1.000000e+00, %tmp26
|
|
|
|
|
%result.i = fadd float %tmp230, %one.sub.a.i
|
|
|
|
|
%one.sub.a.i43 = fsub float 1.000000e+00, %tmp26
|
|
|
|
|
%result.i44 = fadd float %tmp231, %one.sub.a.i43
|
|
|
|
|
%one.sub.a.i41 = fsub float 1.000000e+00, %tmp26
|
|
|
|
|
%result.i42 = fadd float %tmp232, %one.sub.a.i41
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp233 = fmul float %tmp215, %p2.i72
|
|
|
|
|
%tmp234 = fmul float %tmp216, %p2.i66
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp235 = fadd float %tmp234, %tmp233
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp236 = fmul float %tmp217, %p2.i60
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp237 = fadd float %tmp235, %tmp236
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp238 = fmul float %tmp215, %p2.i54
|
|
|
|
|
%tmp239 = fmul float %tmp216, %p2.i48
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp240 = fadd float %tmp239, %tmp238
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp241 = fmul float %tmp217, %p2.i42
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp242 = fadd float %tmp240, %tmp241
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp243 = fmul float %tmp215, %p2.i36
|
|
|
|
|
%tmp244 = fmul float %tmp216, %p2.i30
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp245 = fadd float %tmp244, %tmp243
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp246 = fmul float %tmp217, %p2.i24
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp247 = fadd float %tmp245, %tmp246
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i19 = call float @llvm.maxnum.f32(float %tmp247, float 0.000000e+00)
|
|
|
|
|
%clamp.i20 = call float @llvm.minnum.f32(float %max.0.i19, float 1.000000e+00)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp249 = fmul float %tmp213, 0x3F5A36E2E0000000
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i17 = call float @llvm.maxnum.f32(float %tmp249, float 0.000000e+00)
|
|
|
|
|
%clamp.i18 = call float @llvm.minnum.f32(float %max.0.i17, float 1.000000e+00)
|
|
|
|
|
%tmp251 = fsub float -0.000000e+00, %clamp.i18
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp252 = fadd float 1.000000e+00, %tmp251
|
2017-02-22 07:46:04 +08:00
|
|
|
%tmp253 = call float @llvm.pow.f32(float %clamp.i20, float 2.500000e-01)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp254 = fmul float %tmp38, %tmp253
|
|
|
|
|
%tmp255 = fmul float %tmp237, %tmp254
|
|
|
|
|
%tmp256 = fmul float %tmp242, %tmp254
|
|
|
|
|
%tmp257 = fmul float %tmp255, %tmp229
|
|
|
|
|
%tmp258 = fmul float %tmp256, %tmp229
|
2017-02-22 07:46:04 +08:00
|
|
|
%tmp259 = fadd float %clamp.i20, 0x3EE4F8B580000000
|
|
|
|
|
%tmp260 = fsub float -0.000000e+00, %clamp.i20
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp261 = fadd float 1.000000e+00, %tmp260
|
|
|
|
|
%tmp262 = fmul float 1.200000e+01, %tmp261
|
|
|
|
|
%tmp263 = fadd float %tmp262, 4.000000e+00
|
|
|
|
|
%tmp264 = fsub float -0.000000e+00, %tmp263
|
|
|
|
|
%tmp265 = fmul float %tmp264, %tmp259
|
|
|
|
|
%tmp266 = fsub float -0.000000e+00, %tmp263
|
|
|
|
|
%tmp267 = fmul float %tmp266, %tmp259
|
|
|
|
|
%tmp268 = fsub float -0.000000e+00, %tmp263
|
|
|
|
|
%tmp269 = fmul float %tmp268, %tmp259
|
|
|
|
|
%tmp270 = fdiv float 1.000000e+00, %tmp265
|
|
|
|
|
%tmp271 = fdiv float 1.000000e+00, %tmp267
|
|
|
|
|
%tmp272 = fdiv float 1.000000e+00, %tmp269
|
|
|
|
|
%tmp273 = fmul float %tmp257, %tmp270
|
|
|
|
|
%tmp274 = fmul float %tmp258, %tmp271
|
|
|
|
|
%tmp275 = fmul float %tmp259, %tmp272
|
2013-11-28 05:23:35 +08:00
|
|
|
br label %LOOP
|
|
|
|
|
|
|
|
|
|
LOOP: ; preds = %LOOP, %main_body
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp144.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp288, %LOOP ]
|
2017-02-16 10:01:13 +08:00
|
|
|
%temp168.0 = phi float [ %p2.i120, %main_body ], [ %tmp284, %LOOP ]
|
|
|
|
|
%temp169.0 = phi float [ %p2.i114, %main_body ], [ %tmp285, %LOOP ]
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp170.0 = phi float [ %tmp252, %main_body ], [ %tmp286, %LOOP ]
|
|
|
|
|
%tmp276 = bitcast float %temp168.0 to i32
|
|
|
|
|
%tmp277 = bitcast float %temp169.0 to i32
|
|
|
|
|
%tmp278 = insertelement <4 x i32> undef, i32 %tmp276, i32 0
|
|
|
|
|
%tmp279 = insertelement <4 x i32> %tmp278, i32 %tmp277, i32 1
|
|
|
|
|
%tmp280 = insertelement <4 x i32> %tmp279, i32 0, i32 2
|
|
|
|
|
%tmp281 = insertelement <4 x i32> %tmp280, i32 undef, i32 3
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp148.bc = bitcast <4 x i32> %tmp148 to <4 x i32>
|
2017-03-22 00:24:12 +08:00
|
|
|
%tmp281.bc = bitcast <4 x i32> %tmp281 to <4 x float>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp282 = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %temp168.0, float %temp169.0, float 0.0, <8 x i32> %tmp146, <4 x i32> %tmp148.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp283 = extractelement <4 x float> %tmp282, i32 3
|
|
|
|
|
%tmp284 = fadd float %temp168.0, %tmp273
|
|
|
|
|
%tmp285 = fadd float %temp169.0, %tmp274
|
|
|
|
|
%tmp286 = fadd float %temp170.0, %tmp275
|
|
|
|
|
%tmp287 = fsub float -0.000000e+00, %tmp283
|
|
|
|
|
%tmp288 = fadd float %tmp286, %tmp287
|
|
|
|
|
%tmp289 = fcmp oge float 0.000000e+00, %tmp288
|
|
|
|
|
%tmp290 = sext i1 %tmp289 to i32
|
|
|
|
|
%tmp291 = bitcast i32 %tmp290 to float
|
|
|
|
|
%tmp292 = bitcast float %tmp291 to i32
|
|
|
|
|
%tmp293 = icmp ne i32 %tmp292, 0
|
|
|
|
|
br i1 %tmp293, label %IF189, label %LOOP
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
IF189: ; preds = %LOOP
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp294 = extractelement <4 x float> %tmp282, i32 0
|
|
|
|
|
%tmp295 = extractelement <4 x float> %tmp282, i32 1
|
|
|
|
|
%tmp296 = extractelement <4 x float> %tmp282, i32 2
|
|
|
|
|
%tmp297 = fsub float -0.000000e+00, %tmp288
|
|
|
|
|
%tmp298 = fadd float %temp144.0, %tmp297
|
|
|
|
|
%tmp299 = fdiv float 1.000000e+00, %tmp298
|
|
|
|
|
%tmp300 = fmul float %tmp288, %tmp299
|
|
|
|
|
%tmp301 = fadd float %tmp300, -1.000000e+00
|
|
|
|
|
%tmp302 = fmul float %tmp301, %tmp273
|
|
|
|
|
%tmp303 = fadd float %tmp302, %tmp284
|
|
|
|
|
%tmp304 = fmul float %tmp301, %tmp274
|
|
|
|
|
%tmp305 = fadd float %tmp304, %tmp285
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp306 = fsub float -0.000000e+00, %p2.i120
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp307 = fadd float %tmp303, %tmp306
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp308 = fsub float -0.000000e+00, %p2.i114
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp309 = fadd float %tmp305, %tmp308
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp310 = fadd float %p2.i120, %tmp307
|
|
|
|
|
%tmp311 = fadd float %p2.i114, %tmp309
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp312 = fmul float %tmp307, %tmp66
|
|
|
|
|
%tmp313 = fmul float %tmp309, %tmp67
|
|
|
|
|
%tmp314 = fmul float %tmp312, %tmp54
|
|
|
|
|
%tmp315 = fmul float %tmp312, %tmp55
|
|
|
|
|
%tmp316 = fmul float %tmp313, %tmp56
|
|
|
|
|
%tmp317 = fadd float %tmp316, %tmp314
|
|
|
|
|
%tmp318 = fmul float %tmp313, %tmp57
|
|
|
|
|
%tmp319 = fadd float %tmp318, %tmp315
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp320 = fadd float %p2.i108, %tmp317
|
|
|
|
|
%tmp321 = fadd float %p2.i102, %tmp319
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp322 = fmul float %tmp312, %tmp58
|
|
|
|
|
%tmp323 = fmul float %tmp312, %tmp59
|
|
|
|
|
%tmp324 = fmul float %tmp312, %tmp60
|
|
|
|
|
%tmp325 = fmul float %tmp312, %tmp61
|
|
|
|
|
%tmp326 = fmul float %tmp313, %tmp62
|
|
|
|
|
%tmp327 = fadd float %tmp326, %tmp322
|
|
|
|
|
%tmp328 = fmul float %tmp313, %tmp63
|
|
|
|
|
%tmp329 = fadd float %tmp328, %tmp323
|
|
|
|
|
%tmp330 = fmul float %tmp313, %tmp64
|
|
|
|
|
%tmp331 = fadd float %tmp330, %tmp324
|
|
|
|
|
%tmp332 = fmul float %tmp313, %tmp65
|
|
|
|
|
%tmp333 = fadd float %tmp332, %tmp325
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp334 = fadd float %p2.i168, %tmp327
|
|
|
|
|
%tmp335 = fadd float %p2.i162, %tmp329
|
|
|
|
|
%tmp336 = fadd float %p2.i156, %tmp331
|
|
|
|
|
%tmp337 = fadd float %p2.i150, %tmp333
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp136.bc = bitcast <4 x i32> %tmp136 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp0 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp334, float %tmp335, <8 x i32> %tmp134, <4 x i32> %tmp136.bc, i1 0, i32 0, i32 0)
|
2017-03-22 00:24:12 +08:00
|
|
|
%tmp343 = extractelement <4 x float> %tmp0, i32 0
|
|
|
|
|
%tmp344 = extractelement <4 x float> %tmp0, i32 1
|
|
|
|
|
%tmp345 = extractelement <4 x float> %tmp0, i32 2
|
|
|
|
|
%tmp346 = extractelement <4 x float> %tmp0, i32 3
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp347 = fmul float %tmp343, %tmp22
|
|
|
|
|
%tmp348 = fmul float %tmp344, %tmp23
|
|
|
|
|
%tmp349 = fmul float %tmp345, %tmp24
|
|
|
|
|
%tmp350 = fmul float %tmp346, %tmp25
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp351 = fmul float %tmp347, %p2.i96
|
|
|
|
|
%tmp352 = fmul float %tmp348, %p2.i90
|
|
|
|
|
%tmp353 = fmul float %tmp349, %p2.i84
|
|
|
|
|
%tmp354 = fmul float %tmp350, %p2.i78
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp355 = fsub float -0.000000e+00, %tmp346
|
|
|
|
|
%tmp356 = fadd float 1.000000e+00, %tmp355
|
|
|
|
|
%tmp357 = fmul float %tmp356, %tmp48
|
|
|
|
|
%one.sub.a.i37 = fsub float 1.000000e+00, %tmp357
|
|
|
|
|
%one.sub.ac.i38 = fmul float %one.sub.a.i37, %tmp351
|
|
|
|
|
%mul.i39 = fmul float %tmp343, %tmp351
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i40 = fadd float %mul.i39, %one.sub.ac.i38
|
2016-01-23 13:42:43 +08:00
|
|
|
%one.sub.a.i33 = fsub float 1.000000e+00, %tmp357
|
|
|
|
|
%one.sub.ac.i34 = fmul float %one.sub.a.i33, %tmp352
|
|
|
|
|
%mul.i35 = fmul float %tmp344, %tmp352
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i36 = fadd float %mul.i35, %one.sub.ac.i34
|
2016-01-23 13:42:43 +08:00
|
|
|
%one.sub.a.i29 = fsub float 1.000000e+00, %tmp357
|
|
|
|
|
%one.sub.ac.i30 = fmul float %one.sub.a.i29, %tmp353
|
|
|
|
|
%mul.i31 = fmul float %tmp345, %tmp353
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i32 = fadd float %mul.i31, %one.sub.ac.i30
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp152.bc = bitcast <4 x i32> %tmp152 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp1 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp336, float %tmp337, <8 x i32> %tmp150, <4 x i32> %tmp152.bc, i1 0, i32 0, i32 0)
|
2017-03-22 00:24:12 +08:00
|
|
|
%tmp363 = extractelement <4 x float> %tmp1, i32 2
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp364 = fmul float %result.i40, %result.i
|
|
|
|
|
%tmp365 = fmul float %result.i36, %result.i44
|
|
|
|
|
%tmp366 = fmul float %result.i32, %result.i42
|
|
|
|
|
%tmp367 = fmul float %tmp354, %tmp229
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp140.bc = bitcast <4 x i32> %tmp140 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp2 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp310, float %tmp311, <8 x i32> %tmp138, <4 x i32> %tmp140.bc, i1 0, i32 0, i32 0)
|
2017-03-22 00:24:12 +08:00
|
|
|
%tmp373 = extractelement <4 x float> %tmp2, i32 0
|
|
|
|
|
%tmp374 = extractelement <4 x float> %tmp2, i32 1
|
|
|
|
|
%tmp375 = extractelement <4 x float> %tmp2, i32 2
|
|
|
|
|
%tmp376 = extractelement <4 x float> %tmp2, i32 3
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp377 = fcmp olt float 0.000000e+00, %tmp375
|
|
|
|
|
%tmp378 = sext i1 %tmp377 to i32
|
|
|
|
|
%tmp379 = bitcast i32 %tmp378 to float
|
|
|
|
|
%tmp380 = bitcast float %tmp379 to i32
|
|
|
|
|
%tmp381 = icmp ne i32 %tmp380, 0
|
|
|
|
|
%.224 = select i1 %tmp381, float %tmp374, float %tmp373
|
|
|
|
|
%.225 = select i1 %tmp381, float %tmp376, float %tmp374
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp144.bc = bitcast <4 x i32> %tmp144 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp3 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp320, float %tmp321, <8 x i32> %tmp142, <4 x i32> %tmp144.bc, i1 0, i32 0, i32 0)
|
2017-03-22 00:24:12 +08:00
|
|
|
%tmp387 = extractelement <4 x float> %tmp3, i32 0
|
|
|
|
|
%tmp388 = extractelement <4 x float> %tmp3, i32 1
|
|
|
|
|
%tmp389 = extractelement <4 x float> %tmp3, i32 2
|
|
|
|
|
%tmp390 = extractelement <4 x float> %tmp3, i32 3
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp391 = fcmp olt float 0.000000e+00, %tmp389
|
|
|
|
|
%tmp392 = sext i1 %tmp391 to i32
|
|
|
|
|
%tmp393 = bitcast i32 %tmp392 to float
|
|
|
|
|
%tmp394 = bitcast float %tmp393 to i32
|
|
|
|
|
%tmp395 = icmp ne i32 %tmp394, 0
|
|
|
|
|
%temp112.1 = select i1 %tmp395, float %tmp388, float %tmp387
|
|
|
|
|
%temp113.1 = select i1 %tmp395, float %tmp390, float %tmp388
|
|
|
|
|
%tmp396 = fmul float %.224, 2.000000e+00
|
|
|
|
|
%tmp397 = fadd float %tmp396, -1.000000e+00
|
|
|
|
|
%tmp398 = fmul float %.225, 2.000000e+00
|
|
|
|
|
%tmp399 = fadd float %tmp398, -1.000000e+00
|
|
|
|
|
%tmp400 = fmul float %temp112.1, 2.000000e+00
|
|
|
|
|
%tmp401 = fadd float %tmp400, -1.000000e+00
|
|
|
|
|
%tmp402 = fmul float %temp113.1, 2.000000e+00
|
|
|
|
|
%tmp403 = fadd float %tmp402, -1.000000e+00
|
|
|
|
|
%tmp404 = fsub float -0.000000e+00, %tmp397
|
|
|
|
|
%tmp405 = fmul float %tmp404, %tmp34
|
|
|
|
|
%tmp406 = fsub float -0.000000e+00, %tmp399
|
|
|
|
|
%tmp407 = fmul float %tmp406, %tmp34
|
|
|
|
|
%tmp408 = fsub float -0.000000e+00, %tmp401
|
|
|
|
|
%tmp409 = fmul float %tmp408, %tmp35
|
|
|
|
|
%tmp410 = fsub float -0.000000e+00, %tmp403
|
|
|
|
|
%tmp411 = fmul float %tmp410, %tmp35
|
|
|
|
|
%tmp412 = fmul float %tmp409, %tmp363
|
|
|
|
|
%tmp413 = fmul float %tmp411, %tmp363
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp414 = call float @llvm.fabs.f32(float %tmp405)
|
|
|
|
|
%tmp415 = call float @llvm.fabs.f32(float %tmp407)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp416 = fsub float -0.000000e+00, %tmp414
|
|
|
|
|
%tmp417 = fadd float 1.000000e+00, %tmp416
|
|
|
|
|
%tmp418 = fsub float -0.000000e+00, %tmp415
|
|
|
|
|
%tmp419 = fadd float 1.000000e+00, %tmp418
|
|
|
|
|
%tmp420 = fmul float %tmp417, %tmp412
|
|
|
|
|
%tmp421 = fadd float %tmp420, %tmp405
|
|
|
|
|
%tmp422 = fmul float %tmp419, %tmp413
|
|
|
|
|
%tmp423 = fadd float %tmp422, %tmp407
|
|
|
|
|
%tmp424 = fmul float %tmp421, %tmp421
|
|
|
|
|
%tmp425 = fmul float %tmp423, %tmp423
|
|
|
|
|
%tmp426 = fadd float %tmp424, %tmp425
|
|
|
|
|
%tmp427 = fsub float -0.000000e+00, %tmp426
|
|
|
|
|
%tmp428 = fadd float 0x3FF00068E0000000, %tmp427
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i15 = call float @llvm.maxnum.f32(float %tmp428, float 0.000000e+00)
|
|
|
|
|
%clamp.i16 = call float @llvm.minnum.f32(float %max.0.i15, float 1.000000e+00)
|
|
|
|
|
%tmp430 = call float @llvm.amdgcn.rsq.f32(float %clamp.i16)
|
|
|
|
|
%tmp431 = fmul float %tmp430, %clamp.i16
|
|
|
|
|
%tmp432 = fsub float -0.000000e+00, %clamp.i16
|
2016-01-23 13:42:43 +08:00
|
|
|
%cmp = fcmp ogt float 0.000000e+00, %tmp432
|
|
|
|
|
%tmp433 = select i1 %cmp, float %tmp431, float 0.000000e+00
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp434 = fmul float %p2.i72, %tmp421
|
|
|
|
|
%tmp435 = fmul float %p2.i66, %tmp421
|
|
|
|
|
%tmp436 = fmul float %p2.i60, %tmp421
|
|
|
|
|
%tmp437 = fmul float %p2.i54, %tmp423
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp438 = fadd float %tmp437, %tmp434
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp439 = fmul float %p2.i48, %tmp423
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp440 = fadd float %tmp439, %tmp435
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp441 = fmul float %p2.i42, %tmp423
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp442 = fadd float %tmp441, %tmp436
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp443 = fmul float %p2.i36, %tmp433
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp444 = fadd float %tmp443, %tmp438
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp445 = fmul float %p2.i30, %tmp433
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp446 = fadd float %tmp445, %tmp440
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp447 = fmul float %p2.i24, %tmp433
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp448 = fadd float %tmp447, %tmp442
|
|
|
|
|
%tmp449 = fmul float %tmp444, %tmp444
|
|
|
|
|
%tmp450 = fmul float %tmp446, %tmp446
|
|
|
|
|
%tmp451 = fadd float %tmp450, %tmp449
|
|
|
|
|
%tmp452 = fmul float %tmp448, %tmp448
|
|
|
|
|
%tmp453 = fadd float %tmp451, %tmp452
|
|
|
|
|
%tmp454 = call float @llvm.amdgcn.rsq.f32(float %tmp453)
|
|
|
|
|
%tmp455 = fmul float %tmp444, %tmp454
|
|
|
|
|
%tmp456 = fmul float %tmp446, %tmp454
|
|
|
|
|
%tmp457 = fmul float %tmp448, %tmp454
|
|
|
|
|
%tmp458 = fcmp olt float 0.000000e+00, %tmp218
|
|
|
|
|
%tmp459 = sext i1 %tmp458 to i32
|
|
|
|
|
%tmp460 = bitcast i32 %tmp459 to float
|
|
|
|
|
%tmp461 = bitcast float %tmp460 to i32
|
|
|
|
|
%tmp462 = icmp ne i32 %tmp461, 0
|
|
|
|
|
br i1 %tmp462, label %IF198, label %ENDIF197
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
IF198: ; preds = %IF189
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp463 = fsub float -0.000000e+00, %tmp455
|
|
|
|
|
%tmp464 = fsub float -0.000000e+00, %tmp456
|
|
|
|
|
%tmp465 = fsub float -0.000000e+00, %tmp457
|
2013-11-28 05:23:35 +08:00
|
|
|
br label %ENDIF197
|
|
|
|
|
|
2016-01-23 13:42:38 +08:00
|
|
|
ENDIF197: ; preds = %IF198, %IF189
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp14.0 = phi float [ %tmp465, %IF198 ], [ %tmp457, %IF189 ]
|
|
|
|
|
%temp13.0 = phi float [ %tmp464, %IF198 ], [ %tmp456, %IF189 ]
|
|
|
|
|
%temp12.0 = phi float [ %tmp463, %IF198 ], [ %tmp455, %IF189 ]
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp160.bc = bitcast <4 x i32> %tmp160 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp470 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %tmp219, float %tmp220, <8 x i32> %tmp158, <4 x i32> %tmp160.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp471 = extractelement <4 x float> %tmp470, i32 0
|
|
|
|
|
%tmp472 = extractelement <4 x float> %tmp470, i32 1
|
|
|
|
|
%tmp473 = extractelement <4 x float> %tmp470, i32 2
|
|
|
|
|
%tmp474 = extractelement <4 x float> %tmp470, i32 3
|
|
|
|
|
%tmp475 = fmul float %tmp471, %tmp39
|
|
|
|
|
%tmp476 = fadd float %tmp475, %tmp40
|
|
|
|
|
%tmp477 = fmul float %tmp472, %tmp39
|
|
|
|
|
%tmp478 = fadd float %tmp477, %tmp40
|
|
|
|
|
%tmp479 = fmul float %tmp473, %tmp39
|
|
|
|
|
%tmp480 = fadd float %tmp479, %tmp40
|
|
|
|
|
%tmp481 = fmul float %tmp474, %tmp41
|
|
|
|
|
%tmp482 = fadd float %tmp481, %tmp42
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp156.bc = bitcast <4 x i32> %tmp156 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp487 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i144, float %p2.i138, <8 x i32> %tmp154, <4 x i32> %tmp156.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp488 = extractelement <4 x float> %tmp487, i32 0
|
|
|
|
|
%tmp489 = extractelement <4 x float> %tmp487, i32 1
|
|
|
|
|
%tmp490 = extractelement <4 x float> %tmp487, i32 2
|
|
|
|
|
%tmp491 = extractelement <4 x float> %tmp487, i32 3
|
|
|
|
|
%tmp492 = fmul float %tmp491, 3.200000e+01
|
|
|
|
|
%tmp493 = fadd float %tmp492, -1.600000e+01
|
2016-01-23 13:42:49 +08:00
|
|
|
%tmp494 = call float @llvm.exp2.f32(float %tmp493)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp495 = fmul float %tmp488, %tmp494
|
|
|
|
|
%tmp496 = fmul float %tmp489, %tmp494
|
|
|
|
|
%tmp497 = fmul float %tmp490, %tmp494
|
|
|
|
|
%tmp498 = fmul float %tmp27, %tmp495
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp499 = fadd float %tmp498, %p2.i18
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp500 = fmul float %tmp28, %tmp496
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp501 = fadd float %tmp500, %p2.i12
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp502 = fmul float %tmp29, %tmp497
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp503 = fadd float %tmp502, %p2.i6
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp504 = fmul float %tmp499, %tmp482
|
|
|
|
|
%tmp505 = fmul float %tmp501, %tmp482
|
|
|
|
|
%tmp506 = fmul float %tmp503, %tmp482
|
|
|
|
|
%tmp507 = fmul float %tmp482, 5.000000e-01
|
|
|
|
|
%tmp508 = fadd float %tmp507, 5.000000e-01
|
|
|
|
|
%tmp509 = fmul float %tmp476, %tmp508
|
|
|
|
|
%tmp510 = fadd float %tmp509, %tmp504
|
|
|
|
|
%tmp511 = fmul float %tmp478, %tmp508
|
|
|
|
|
%tmp512 = fadd float %tmp511, %tmp505
|
|
|
|
|
%tmp513 = fmul float %tmp480, %tmp508
|
|
|
|
|
%tmp514 = fadd float %tmp513, %tmp506
|
|
|
|
|
%tmp515 = fmul float %tmp510, %tmp364
|
|
|
|
|
%tmp516 = fmul float %tmp512, %tmp365
|
|
|
|
|
%tmp517 = fmul float %tmp514, %tmp366
|
|
|
|
|
%tmp518 = fmul float %tmp421, 0x3FDB272440000000
|
|
|
|
|
%tmp519 = fmul float %tmp423, 0xBFDB272440000000
|
|
|
|
|
%tmp520 = fadd float %tmp519, %tmp518
|
|
|
|
|
%tmp521 = fmul float %tmp433, 0x3FE99999A0000000
|
|
|
|
|
%tmp522 = fadd float %tmp520, %tmp521
|
|
|
|
|
%tmp523 = fmul float %tmp522, 5.000000e-01
|
|
|
|
|
%tmp524 = fadd float %tmp523, 0x3FE3333340000000
|
|
|
|
|
%tmp525 = fmul float %tmp524, %tmp524
|
|
|
|
|
%tmp526 = fmul float %tmp515, %tmp525
|
|
|
|
|
%tmp527 = fmul float %tmp516, %tmp525
|
|
|
|
|
%tmp528 = fmul float %tmp517, %tmp525
|
|
|
|
|
%tmp529 = fsub float -0.000000e+00, %tmp71
|
|
|
|
|
%tmp530 = fsub float -0.000000e+00, %tmp72
|
|
|
|
|
%tmp531 = fsub float -0.000000e+00, %tmp73
|
|
|
|
|
%tmp532 = fmul float %temp12.0, %tmp529
|
|
|
|
|
%tmp533 = fmul float %temp13.0, %tmp530
|
|
|
|
|
%tmp534 = fadd float %tmp533, %tmp532
|
|
|
|
|
%tmp535 = fmul float %temp14.0, %tmp531
|
|
|
|
|
%tmp536 = fadd float %tmp534, %tmp535
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i13 = call float @llvm.maxnum.f32(float %tmp536, float 0.000000e+00)
|
|
|
|
|
%clamp.i14 = call float @llvm.minnum.f32(float %max.0.i13, float 1.000000e+00)
|
|
|
|
|
%tmp538 = fmul float %tmp364, %clamp.i14
|
|
|
|
|
%tmp539 = fmul float %tmp365, %clamp.i14
|
|
|
|
|
%tmp540 = fmul float %tmp366, %clamp.i14
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp541 = fmul float %tmp538, %tmp68
|
|
|
|
|
%tmp542 = fmul float %tmp539, %tmp69
|
|
|
|
|
%tmp543 = fmul float %tmp540, %tmp70
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp544 = fsub float -0.000000e+00, %p2.i
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp545 = fadd float %tmp96, %tmp544
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp546 = fsub float -0.000000e+00, %p2.i186
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp547 = fadd float %tmp97, %tmp546
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp548 = fsub float -0.000000e+00, %p2.i180
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp549 = fadd float %tmp98, %tmp548
|
|
|
|
|
%tmp550 = fmul float %tmp545, %tmp545
|
|
|
|
|
%tmp551 = fmul float %tmp547, %tmp547
|
|
|
|
|
%tmp552 = fadd float %tmp551, %tmp550
|
|
|
|
|
%tmp553 = fmul float %tmp549, %tmp549
|
|
|
|
|
%tmp554 = fadd float %tmp552, %tmp553
|
|
|
|
|
%tmp555 = call float @llvm.amdgcn.rsq.f32(float %tmp554)
|
|
|
|
|
%tmp556 = fmul float %tmp555, %tmp554
|
|
|
|
|
%tmp557 = fsub float -0.000000e+00, %tmp554
|
|
|
|
|
%cmp1 = fcmp ogt float %tmp557, 0.000000e+00
|
|
|
|
|
%tmp558 = select i1 %cmp1, float %tmp556, float 0.000000e+00
|
|
|
|
|
%tmp559 = fsub float -0.000000e+00, %tmp83
|
|
|
|
|
%tmp560 = fadd float %tmp558, %tmp559
|
|
|
|
|
%tmp561 = fsub float -0.000000e+00, %tmp82
|
|
|
|
|
%tmp562 = fadd float %tmp558, %tmp561
|
|
|
|
|
%tmp563 = fsub float -0.000000e+00, %tmp81
|
|
|
|
|
%tmp564 = fadd float %tmp558, %tmp563
|
|
|
|
|
%tmp565 = fsub float -0.000000e+00, %tmp83
|
|
|
|
|
%tmp566 = fadd float %tmp82, %tmp565
|
|
|
|
|
%tmp567 = fsub float -0.000000e+00, %tmp82
|
|
|
|
|
%tmp568 = fadd float %tmp81, %tmp567
|
|
|
|
|
%tmp569 = fsub float -0.000000e+00, %tmp81
|
|
|
|
|
%tmp570 = fadd float %tmp80, %tmp569
|
|
|
|
|
%tmp571 = fdiv float 1.000000e+00, %tmp566
|
|
|
|
|
%tmp572 = fdiv float 1.000000e+00, %tmp568
|
|
|
|
|
%tmp573 = fdiv float 1.000000e+00, %tmp570
|
|
|
|
|
%tmp574 = fmul float %tmp560, %tmp571
|
|
|
|
|
%tmp575 = fmul float %tmp562, %tmp572
|
|
|
|
|
%tmp576 = fmul float %tmp564, %tmp573
|
|
|
|
|
%tmp577 = fcmp olt float %tmp558, %tmp82
|
|
|
|
|
%tmp578 = sext i1 %tmp577 to i32
|
|
|
|
|
%tmp579 = bitcast i32 %tmp578 to float
|
|
|
|
|
%tmp580 = bitcast float %tmp579 to i32
|
|
|
|
|
%tmp581 = icmp ne i32 %tmp580, 0
|
|
|
|
|
br i1 %tmp581, label %ENDIF200, label %ELSE202
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
ELSE202: ; preds = %ENDIF197
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp582 = fcmp olt float %tmp558, %tmp81
|
|
|
|
|
%tmp583 = sext i1 %tmp582 to i32
|
|
|
|
|
%tmp584 = bitcast i32 %tmp583 to float
|
|
|
|
|
%tmp585 = bitcast float %tmp584 to i32
|
|
|
|
|
%tmp586 = icmp ne i32 %tmp585, 0
|
|
|
|
|
br i1 %tmp586, label %ENDIF200, label %ELSE205
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
ENDIF200: ; preds = %ELSE205, %ELSE202, %ENDIF197
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp80.0 = phi float [ %tmp574, %ENDIF197 ], [ %.226, %ELSE205 ], [ %tmp575, %ELSE202 ]
|
|
|
|
|
%temp88.0 = phi float [ %tmp121, %ENDIF197 ], [ %.227, %ELSE205 ], [ %tmp119, %ELSE202 ]
|
|
|
|
|
%temp89.0 = phi float [ %tmp122, %ENDIF197 ], [ %.228, %ELSE205 ], [ %tmp120, %ELSE202 ]
|
|
|
|
|
%temp90.0 = phi float [ %tmp119, %ENDIF197 ], [ %tmp115, %ELSE205 ], [ %tmp117, %ELSE202 ]
|
|
|
|
|
%temp91.0 = phi float [ %tmp120, %ENDIF197 ], [ %tmp116, %ELSE205 ], [ %tmp118, %ELSE202 ]
|
|
|
|
|
%tmp587 = fcmp olt float %tmp558, %tmp82
|
|
|
|
|
%tmp588 = sext i1 %tmp587 to i32
|
|
|
|
|
%tmp589 = bitcast i32 %tmp588 to float
|
|
|
|
|
%tmp590 = bitcast float %tmp589 to i32
|
|
|
|
|
%tmp591 = icmp ne i32 %tmp590, 0
|
|
|
|
|
br i1 %tmp591, label %ENDIF209, label %ELSE211
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
ELSE205: ; preds = %ELSE202
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp592 = fcmp olt float %tmp558, %tmp80
|
|
|
|
|
%tmp593 = sext i1 %tmp592 to i32
|
|
|
|
|
%tmp594 = bitcast i32 %tmp593 to float
|
|
|
|
|
%tmp595 = bitcast float %tmp594 to i32
|
|
|
|
|
%tmp596 = icmp ne i32 %tmp595, 0
|
|
|
|
|
%.226 = select i1 %tmp596, float %tmp576, float 1.000000e+00
|
|
|
|
|
%.227 = select i1 %tmp596, float %tmp117, float %tmp115
|
|
|
|
|
%.228 = select i1 %tmp596, float %tmp118, float %tmp116
|
2013-11-28 05:23:35 +08:00
|
|
|
br label %ENDIF200
|
|
|
|
|
|
|
|
|
|
ELSE211: ; preds = %ENDIF200
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp597 = fcmp olt float %tmp558, %tmp81
|
|
|
|
|
%tmp598 = sext i1 %tmp597 to i32
|
|
|
|
|
%tmp599 = bitcast i32 %tmp598 to float
|
|
|
|
|
%tmp600 = bitcast float %tmp599 to i32
|
|
|
|
|
%tmp601 = icmp ne i32 %tmp600, 0
|
|
|
|
|
br i1 %tmp601, label %ENDIF209, label %ELSE214
|
2013-11-28 05:23:35 +08:00
|
|
|
|
|
|
|
|
ENDIF209: ; preds = %ELSE214, %ELSE211, %ENDIF200
|
2016-01-23 13:42:43 +08:00
|
|
|
%temp52.0 = phi float [ %tmp107, %ENDIF200 ], [ %tmp99, %ELSE214 ], [ %tmp103, %ELSE211 ]
|
|
|
|
|
%temp53.0 = phi float [ %tmp108, %ENDIF200 ], [ %tmp100, %ELSE214 ], [ %tmp104, %ELSE211 ]
|
|
|
|
|
%temp54.0 = phi float [ %tmp109, %ENDIF200 ], [ %tmp101, %ELSE214 ], [ %tmp105, %ELSE211 ]
|
|
|
|
|
%temp55.0 = phi float [ %tmp110, %ENDIF200 ], [ %tmp102, %ELSE214 ], [ %tmp106, %ELSE211 ]
|
|
|
|
|
%temp68.0 = phi float [ %tmp111, %ENDIF200 ], [ %.230, %ELSE214 ], [ %tmp107, %ELSE211 ]
|
|
|
|
|
%temp69.0 = phi float [ %tmp112, %ENDIF200 ], [ %.231, %ELSE214 ], [ %tmp108, %ELSE211 ]
|
|
|
|
|
%temp70.0 = phi float [ %tmp113, %ENDIF200 ], [ %.232, %ELSE214 ], [ %tmp109, %ELSE211 ]
|
|
|
|
|
%temp71.0 = phi float [ %tmp114, %ENDIF200 ], [ %.233, %ELSE214 ], [ %tmp110, %ELSE211 ]
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp602 = fmul float %p2.i, %tmp84
|
|
|
|
|
%tmp603 = fmul float %p2.i186, %tmp85
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp604 = fadd float %tmp602, %tmp603
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp605 = fmul float %p2.i180, %tmp86
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp606 = fadd float %tmp604, %tmp605
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp607 = fmul float %p2.i174, %tmp87
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp608 = fadd float %tmp606, %tmp607
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp609 = fmul float %p2.i, %tmp88
|
|
|
|
|
%tmp610 = fmul float %p2.i186, %tmp89
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp611 = fadd float %tmp609, %tmp610
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp612 = fmul float %p2.i180, %tmp90
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp613 = fadd float %tmp611, %tmp612
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp614 = fmul float %p2.i174, %tmp91
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp615 = fadd float %tmp613, %tmp614
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp616 = fmul float %p2.i, %tmp92
|
|
|
|
|
%tmp617 = fmul float %p2.i186, %tmp93
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp618 = fadd float %tmp616, %tmp617
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp619 = fmul float %p2.i180, %tmp94
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp620 = fadd float %tmp618, %tmp619
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp621 = fmul float %p2.i174, %tmp95
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp622 = fadd float %tmp620, %tmp621
|
|
|
|
|
%tmp623 = fsub float -0.000000e+00, %tmp77
|
|
|
|
|
%tmp624 = fadd float 1.000000e+00, %tmp623
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp625 = call float @llvm.fabs.f32(float %tmp608)
|
|
|
|
|
%tmp626 = call float @llvm.fabs.f32(float %tmp615)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp627 = fcmp oge float %tmp624, %tmp625
|
|
|
|
|
%tmp628 = sext i1 %tmp627 to i32
|
|
|
|
|
%tmp629 = bitcast i32 %tmp628 to float
|
|
|
|
|
%tmp630 = bitcast float %tmp629 to i32
|
|
|
|
|
%tmp631 = and i32 %tmp630, 1065353216
|
|
|
|
|
%tmp632 = bitcast i32 %tmp631 to float
|
|
|
|
|
%tmp633 = fcmp oge float %tmp624, %tmp626
|
|
|
|
|
%tmp634 = sext i1 %tmp633 to i32
|
|
|
|
|
%tmp635 = bitcast i32 %tmp634 to float
|
|
|
|
|
%tmp636 = bitcast float %tmp635 to i32
|
|
|
|
|
%tmp637 = and i32 %tmp636, 1065353216
|
|
|
|
|
%tmp638 = bitcast i32 %tmp637 to float
|
|
|
|
|
%tmp639 = fmul float %tmp632, %tmp638
|
|
|
|
|
%tmp640 = fmul float %tmp622, %tmp639
|
|
|
|
|
%tmp641 = fmul float %tmp608, %temp68.0
|
|
|
|
|
%tmp642 = fadd float %tmp641, %temp70.0
|
|
|
|
|
%tmp643 = fmul float %tmp615, %temp69.0
|
|
|
|
|
%tmp644 = fadd float %tmp643, %temp71.0
|
|
|
|
|
%tmp645 = fmul float %tmp608, %temp52.0
|
|
|
|
|
%tmp646 = fadd float %tmp645, %temp54.0
|
|
|
|
|
%tmp647 = fmul float %tmp615, %temp53.0
|
|
|
|
|
%tmp648 = fadd float %tmp647, %temp55.0
|
|
|
|
|
%tmp649 = fadd float %temp80.0, -1.000000e+00
|
|
|
|
|
%tmp650 = fmul float %tmp649, %tmp76
|
|
|
|
|
%tmp651 = fadd float %tmp650, 1.000000e+00
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i11 = call float @llvm.maxnum.f32(float %tmp651, float 0.000000e+00)
|
|
|
|
|
%clamp.i12 = call float @llvm.minnum.f32(float %max.0.i11, float 1.000000e+00)
|
2017-06-29 05:38:50 +08:00
|
|
|
%tmp128.bc = bitcast <4 x i32> %tmp128 to <4 x i32>
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp660 = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %tmp642, float %tmp644, float 0.0, <8 x i32> %tmp126, <4 x i32> %tmp128.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp661 = extractelement <4 x float> %tmp660, i32 0
|
|
|
|
|
%tmp662 = extractelement <4 x float> %tmp660, i32 1
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
%tmp670 = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %tmp646, float %tmp648, float 0.0, <8 x i32> %tmp126, <4 x i32> %tmp128.bc, i1 0, i32 0, i32 0)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp671 = extractelement <4 x float> %tmp670, i32 0
|
|
|
|
|
%tmp672 = extractelement <4 x float> %tmp670, i32 1
|
|
|
|
|
%tmp673 = fsub float -0.000000e+00, %tmp662
|
|
|
|
|
%tmp674 = fadd float 1.000000e+00, %tmp673
|
|
|
|
|
%tmp675 = fsub float -0.000000e+00, %tmp672
|
|
|
|
|
%tmp676 = fadd float 1.000000e+00, %tmp675
|
|
|
|
|
%tmp677 = fmul float %tmp674, 2.500000e-01
|
|
|
|
|
%tmp678 = fmul float %tmp676, 2.500000e-01
|
|
|
|
|
%tmp679 = fsub float -0.000000e+00, %tmp677
|
|
|
|
|
%tmp680 = fadd float %tmp661, %tmp679
|
|
|
|
|
%tmp681 = fsub float -0.000000e+00, %tmp678
|
|
|
|
|
%tmp682 = fadd float %tmp671, %tmp681
|
|
|
|
|
%tmp683 = fmul float %tmp640, %temp88.0
|
|
|
|
|
%tmp684 = fadd float %tmp683, %temp89.0
|
|
|
|
|
%tmp685 = fmul float %tmp640, %temp90.0
|
|
|
|
|
%tmp686 = fadd float %tmp685, %temp91.0
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i9 = call float @llvm.maxnum.f32(float %tmp684, float 0.000000e+00)
|
|
|
|
|
%clamp.i10 = call float @llvm.minnum.f32(float %max.0.i9, float 1.000000e+00)
|
|
|
|
|
%max.0.i7 = call float @llvm.maxnum.f32(float %tmp686, float 0.000000e+00)
|
|
|
|
|
%clamp.i8 = call float @llvm.minnum.f32(float %max.0.i7, float 1.000000e+00)
|
|
|
|
|
%tmp689 = fsub float -0.000000e+00, %clamp.i10
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp690 = fadd float %tmp661, %tmp689
|
2017-02-22 07:46:04 +08:00
|
|
|
%tmp691 = fsub float -0.000000e+00, %clamp.i8
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp692 = fadd float %tmp671, %tmp691
|
|
|
|
|
%tmp693 = fmul float %tmp661, %tmp661
|
|
|
|
|
%tmp694 = fmul float %tmp671, %tmp671
|
|
|
|
|
%tmp695 = fsub float -0.000000e+00, %tmp693
|
|
|
|
|
%tmp696 = fadd float %tmp680, %tmp695
|
|
|
|
|
%tmp697 = fsub float -0.000000e+00, %tmp694
|
|
|
|
|
%tmp698 = fadd float %tmp682, %tmp697
|
|
|
|
|
%tmp699 = fcmp uge float %tmp696, %tmp74
|
|
|
|
|
%tmp700 = select i1 %tmp699, float %tmp696, float %tmp74
|
|
|
|
|
%tmp701 = fcmp uge float %tmp698, %tmp74
|
|
|
|
|
%tmp702 = select i1 %tmp701, float %tmp698, float %tmp74
|
|
|
|
|
%tmp703 = fmul float %tmp690, %tmp690
|
|
|
|
|
%tmp704 = fadd float %tmp703, %tmp700
|
|
|
|
|
%tmp705 = fmul float %tmp692, %tmp692
|
|
|
|
|
%tmp706 = fadd float %tmp705, %tmp702
|
|
|
|
|
%tmp707 = fdiv float 1.000000e+00, %tmp704
|
|
|
|
|
%tmp708 = fdiv float 1.000000e+00, %tmp706
|
|
|
|
|
%tmp709 = fmul float %tmp700, %tmp707
|
|
|
|
|
%tmp710 = fmul float %tmp702, %tmp708
|
|
|
|
|
%tmp711 = fcmp oge float %tmp690, 0.000000e+00
|
|
|
|
|
%tmp712 = sext i1 %tmp711 to i32
|
|
|
|
|
%tmp713 = bitcast i32 %tmp712 to float
|
|
|
|
|
%tmp714 = bitcast float %tmp713 to i32
|
|
|
|
|
%tmp715 = icmp ne i32 %tmp714, 0
|
|
|
|
|
%.229 = select i1 %tmp715, float 1.000000e+00, float %tmp709
|
|
|
|
|
%tmp716 = fcmp oge float %tmp692, 0.000000e+00
|
|
|
|
|
%tmp717 = sext i1 %tmp716 to i32
|
|
|
|
|
%tmp718 = bitcast i32 %tmp717 to float
|
|
|
|
|
%tmp719 = bitcast float %tmp718 to i32
|
|
|
|
|
%tmp720 = icmp ne i32 %tmp719, 0
|
|
|
|
|
%temp28.0 = select i1 %tmp720, float 1.000000e+00, float %tmp710
|
2017-02-22 07:46:04 +08:00
|
|
|
%one.sub.a.i25 = fsub float 1.000000e+00, %clamp.i12
|
2016-01-23 13:42:38 +08:00
|
|
|
%one.sub.ac.i26 = fmul float %one.sub.a.i25, %.229
|
|
|
|
|
%mul.i27 = fmul float %temp28.0, %.229
|
|
|
|
|
%result.i28 = fadd float %mul.i27, %one.sub.ac.i26
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp721 = call float @llvm.pow.f32(float %result.i28, float %tmp75)
|
|
|
|
|
%tmp722 = fmul float %tmp721, %tmp78
|
|
|
|
|
%tmp723 = fadd float %tmp722, %tmp79
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i5 = call float @llvm.maxnum.f32(float %tmp723, float 0.000000e+00)
|
|
|
|
|
%clamp.i6 = call float @llvm.minnum.f32(float %max.0.i5, float 1.000000e+00)
|
|
|
|
|
%tmp725 = fmul float %clamp.i6, %clamp.i6
|
|
|
|
|
%tmp726 = fmul float 2.000000e+00, %clamp.i6
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp727 = fsub float -0.000000e+00, %tmp726
|
|
|
|
|
%tmp728 = fadd float 3.000000e+00, %tmp727
|
|
|
|
|
%tmp729 = fmul float %tmp725, %tmp728
|
|
|
|
|
%tmp730 = fmul float %tmp541, %tmp729
|
|
|
|
|
%tmp731 = fmul float %tmp542, %tmp729
|
|
|
|
|
%tmp732 = fmul float %tmp543, %tmp729
|
|
|
|
|
%tmp733 = fmul float %tmp730, %tmp508
|
|
|
|
|
%tmp734 = fadd float %tmp733, %tmp526
|
|
|
|
|
%tmp735 = fmul float %tmp731, %tmp508
|
|
|
|
|
%tmp736 = fadd float %tmp735, %tmp527
|
|
|
|
|
%tmp737 = fmul float %tmp732, %tmp508
|
|
|
|
|
%tmp738 = fadd float %tmp737, %tmp528
|
|
|
|
|
%one.sub.a.i23 = fsub float 1.000000e+00, %tmp229
|
|
|
|
|
%result.i24 = fadd float %tmp283, %one.sub.a.i23
|
|
|
|
|
%one.sub.a.i21 = fsub float 1.000000e+00, %tmp36
|
|
|
|
|
%result.i22 = fadd float %tmp294, %one.sub.a.i21
|
|
|
|
|
%one.sub.a.i19 = fsub float 1.000000e+00, %tmp36
|
|
|
|
|
%result.i20 = fadd float %tmp295, %one.sub.a.i19
|
|
|
|
|
%one.sub.a.i17 = fsub float 1.000000e+00, %tmp36
|
|
|
|
|
%result.i18 = fadd float %tmp296, %one.sub.a.i17
|
|
|
|
|
%one.sub.a.i15 = fsub float 1.000000e+00, %tmp37
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i16 = fadd float %result.i24, %one.sub.a.i15
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp739 = fmul float %result.i22, %result.i16
|
|
|
|
|
%tmp740 = fmul float %result.i20, %result.i16
|
|
|
|
|
%tmp741 = fmul float %result.i18, %result.i16
|
|
|
|
|
%tmp742 = fmul float %tmp734, %tmp739
|
|
|
|
|
%tmp743 = fmul float %tmp736, %tmp740
|
|
|
|
|
%tmp744 = fmul float %tmp738, %tmp741
|
|
|
|
|
%tmp745 = fmul float %temp12.0, %tmp215
|
|
|
|
|
%tmp746 = fmul float %temp13.0, %tmp216
|
|
|
|
|
%tmp747 = fadd float %tmp746, %tmp745
|
|
|
|
|
%tmp748 = fmul float %temp14.0, %tmp217
|
|
|
|
|
%tmp749 = fadd float %tmp747, %tmp748
|
2017-02-16 10:01:13 +08:00
|
|
|
%tmp750 = call float @llvm.fabs.f32(float %tmp749)
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp751 = fmul float %tmp750, %tmp750
|
|
|
|
|
%tmp752 = fmul float %tmp751, %tmp49
|
|
|
|
|
%tmp753 = fadd float %tmp752, %tmp50
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i3 = call float @llvm.maxnum.f32(float %tmp753, float 0.000000e+00)
|
|
|
|
|
%clamp.i4 = call float @llvm.minnum.f32(float %max.0.i3, float 1.000000e+00)
|
|
|
|
|
%tmp755 = fsub float -0.000000e+00, %clamp.i4
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp756 = fadd float 1.000000e+00, %tmp755
|
|
|
|
|
%tmp757 = fmul float %tmp32, %tmp756
|
|
|
|
|
%tmp758 = fmul float %tmp32, %tmp756
|
|
|
|
|
%tmp759 = fmul float %tmp32, %tmp756
|
|
|
|
|
%tmp760 = fmul float %tmp33, %tmp756
|
|
|
|
|
%one.sub.a.i11 = fsub float 1.000000e+00, %tmp757
|
|
|
|
|
%one.sub.ac.i12 = fmul float %one.sub.a.i11, %tmp742
|
|
|
|
|
%mul.i13 = fmul float %tmp30, %tmp742
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i14 = fadd float %mul.i13, %one.sub.ac.i12
|
2016-01-23 13:42:43 +08:00
|
|
|
%one.sub.a.i7 = fsub float 1.000000e+00, %tmp758
|
|
|
|
|
%one.sub.ac.i8 = fmul float %one.sub.a.i7, %tmp743
|
|
|
|
|
%mul.i9 = fmul float %tmp30, %tmp743
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i10 = fadd float %mul.i9, %one.sub.ac.i8
|
2016-01-23 13:42:43 +08:00
|
|
|
%one.sub.a.i3 = fsub float 1.000000e+00, %tmp759
|
|
|
|
|
%one.sub.ac.i4 = fmul float %one.sub.a.i3, %tmp744
|
|
|
|
|
%mul.i5 = fmul float %tmp30, %tmp744
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i6 = fadd float %mul.i5, %one.sub.ac.i4
|
2016-01-23 13:42:43 +08:00
|
|
|
%one.sub.a.i1 = fsub float 1.000000e+00, %tmp760
|
|
|
|
|
%one.sub.ac.i = fmul float %one.sub.a.i1, %tmp367
|
|
|
|
|
%mul.i = fmul float %tmp31, %tmp367
|
2016-01-23 13:42:38 +08:00
|
|
|
%result.i2 = fadd float %mul.i, %one.sub.ac.i
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp761 = fcmp uge float %result.i14, 0x3E6FFFFE60000000
|
|
|
|
|
%tmp762 = select i1 %tmp761, float %result.i14, float 0x3E6FFFFE60000000
|
|
|
|
|
%tmp763 = fcmp uge float %result.i10, 0x3E6FFFFE60000000
|
|
|
|
|
%tmp764 = select i1 %tmp763, float %result.i10, float 0x3E6FFFFE60000000
|
|
|
|
|
%tmp765 = fcmp uge float %result.i6, 0x3E6FFFFE60000000
|
|
|
|
|
%tmp766 = select i1 %tmp765, float %result.i6, float 0x3E6FFFFE60000000
|
|
|
|
|
%tmp767 = fcmp uge float %tmp762, 6.550400e+04
|
|
|
|
|
%tmp768 = select i1 %tmp767, float 6.550400e+04, float %tmp762
|
|
|
|
|
%tmp769 = fcmp uge float %tmp764, 6.550400e+04
|
|
|
|
|
%tmp770 = select i1 %tmp769, float 6.550400e+04, float %tmp764
|
|
|
|
|
%tmp771 = fcmp uge float %tmp766, 6.550400e+04
|
|
|
|
|
%tmp772 = select i1 %tmp771, float 6.550400e+04, float %tmp766
|
|
|
|
|
%tmp773 = fmul float %result.i2, %tmp51
|
|
|
|
|
%tmp774 = fadd float %tmp773, %tmp52
|
2017-02-22 07:46:04 +08:00
|
|
|
%max.0.i1 = call float @llvm.maxnum.f32(float %tmp774, float 0.000000e+00)
|
|
|
|
|
%clamp.i2 = call float @llvm.minnum.f32(float %max.0.i1, float 1.000000e+00)
|
2017-02-22 08:27:34 +08:00
|
|
|
%tmp776 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp768, float %tmp770)
|
|
|
|
|
%tmp778 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp772, float %clamp.i2)
|
|
|
|
|
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp776, <2 x half> %tmp778, i1 true, i1 true) #0
|
2013-11-28 05:23:35 +08:00
|
|
|
ret void
|
|
|
|
|
|
|
|
|
|
ELSE214: ; preds = %ELSE211
|
2016-01-23 13:42:43 +08:00
|
|
|
%tmp780 = fcmp olt float %tmp558, %tmp80
|
|
|
|
|
%tmp781 = sext i1 %tmp780 to i32
|
|
|
|
|
%tmp782 = bitcast i32 %tmp781 to float
|
|
|
|
|
%tmp783 = bitcast float %tmp782 to i32
|
|
|
|
|
%tmp784 = icmp ne i32 %tmp783, 0
|
|
|
|
|
%.230 = select i1 %tmp784, float %tmp103, float %tmp99
|
|
|
|
|
%.231 = select i1 %tmp784, float %tmp104, float %tmp100
|
|
|
|
|
%.232 = select i1 %tmp784, float %tmp105, float %tmp101
|
|
|
|
|
%.233 = select i1 %tmp784, float %tmp106, float %tmp102
|
2013-11-28 05:23:35 +08:00
|
|
|
br label %ENDIF209
|
|
|
|
|
}
|
|
|
|
|
|
2017-02-22 07:46:04 +08:00
|
|
|
declare float @llvm.exp2.f32(float) #1
|
|
|
|
|
declare float @llvm.ceil.f32(float) #1
|
|
|
|
|
declare float @llvm.fabs.f32(float) #1
|
|
|
|
|
declare float @llvm.pow.f32(float, float) #1
|
|
|
|
|
declare float @llvm.minnum.f32(float, float) #1
|
|
|
|
|
declare float @llvm.maxnum.f32(float, float) #1
|
2017-02-22 08:02:21 +08:00
|
|
|
declare float @llvm.amdgcn.rsq.f32(float) #1
|
2017-02-22 07:46:04 +08:00
|
|
|
declare float @llvm.amdgcn.cubeid(float, float, float) #1
|
|
|
|
|
declare float @llvm.amdgcn.cubesc(float, float, float) #1
|
|
|
|
|
declare float @llvm.amdgcn.cubetc(float, float, float) #1
|
|
|
|
|
declare float @llvm.amdgcn.cubema(float, float, float) #1
|
|
|
|
|
declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
|
|
|
|
|
declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
|
|
|
|
|
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
|
|
|
|
|
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
|
2017-02-22 08:02:21 +08:00
|
|
|
declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
|
2017-02-22 08:27:34 +08:00
|
|
|
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
|
AMDGPU: Convert test cases to the dimension-aware intrinsics
Summary:
Also explicitly port over some tests in llvm.amdgcn.image.* that were
missing. Some tests are removed because they no longer apply (i.e.
explicitly testing building an address vector via insertelement).
This is in preparation for the eventual removal of the old-style
intrinsics.
Some additional notes:
- constant-address-space-32bit.ll: change some GCN-NEXT to GCN because
the instruction schedule was subtly altered
- insert_vector_elt.ll: the old test didn't actually test anything,
because %tmp1 was not used; remove the load, because it doesn't work
(Because of the amdgpu_ps calling convention? In any case, it's
orthogonal to what the test claims to be testing.)
Change-Id: Idfa99b6512ad139e755e82b8b89548ab08f0afcf
Reviewers: arsenm, rampitec
Subscribers: MatzeB, qcolombet, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D48018
llvm-svn: 335229
2018-06-21 21:37:19 +08:00
|
|
|
declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
|
|
|
|
|
declare <4 x float> @llvm.amdgcn.image.sample.cube.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
|
|
|
|
|
declare <4 x float> @llvm.amdgcn.image.sample.d.2d.v4f32.f32.f32(i32, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
|
|
|
|
|
declare <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
|
2017-06-29 05:38:50 +08:00
|
|
|
declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
|
2016-01-23 13:42:38 +08:00
|
|
|
|
2017-02-22 07:46:04 +08:00
|
|
|
attributes #0 = { nounwind }
|
|
|
|
|
attributes #1 = { nounwind readnone }
|
2017-03-22 00:24:12 +08:00
|
|
|
attributes #2 = { nounwind readonly }
|
2013-11-28 05:23:35 +08:00
|
|
|
|
2016-01-23 13:42:38 +08:00
|
|
|
!0 = !{!1, !1, i64 0, i32 1}
|
[Verifier] Add verification for TBAA metadata
Summary:
This change adds some verification in the IR verifier around struct path
TBAA metadata.
Other than some basic sanity checks (e.g. we get constant integers where
we expect constant integers), this checks:
- That by the time an struct access tuple `(base-type, offset)` is
"reduced" to a scalar base type, the offset is `0`. For instance, in
C++ you can't start from, say `("struct-a", 16)`, and end up with
`("int", 4)` -- by the time the base type is `"int"`, the offset
better be zero. In particular, a variant of this invariant is needed
for `llvm::getMostGenericTBAA` to be correct.
- That there are no cycles in a struct path.
- That struct type nodes have their offsets listed in an ascending
order.
- That when generating the struct access path, you eventually reach the
access type listed in the tbaa tag node.
Reviewers: dexonsmith, chandlerc, reames, mehdi_amini, manmanren
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D26438
llvm-svn: 289402
2016-12-12 04:07:15 +08:00
|
|
|
!1 = !{!"const", !2}
|
|
|
|
|
!2 = !{!"tbaa root"}
|