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llvm-project/llvm/test/MC/Disassembler/X86/x86-64.txt

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Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s
# Coverage
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_usps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_uspd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_usss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmptrue_ussd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x1f
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeq_uqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x08
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x04 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x05 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x06 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: vcmpeqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xc5 0x07 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x66 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf3 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpeqsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf2 0x0f 0xc2 0xc7 0x00
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordps
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordpd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0x66 0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordss
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf3 0x0f 0xc2 0xc7 0x07
death to extra whitespace llvm-svn: 175200
2013-02-15 03:15:14 +08:00
# CHECK: cmpordsd
Add the tests that were supposed to go with r153935 that I forgot svn add llvm-svn: 154165
2012-04-06 15:09:59 +08:00
0xf2 0x0f 0xc2 0xc7 0x07
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. llvm-svn: 157634
2012-05-30 03:05:25 +08:00
# CHECK: extrq $2, $3, %xmm0
0x66 0x0f 0x78 0xc0 0x03 0x02
# CHECK: extrq %xmm1, %xmm0
0x66 0x0f 0x79 0xc1
# CHECK: insertq $6, $5, %xmm1, %xmm0
0xf2 0x0f 0x78 0xc1 0x05 0x06
# CHECK: insertq %xmm1, %xmm0
0xf2 0x0f 0x79 0xc1
# CHECK: movntsd %xmm0, (%rdi)
0xf2 0x0f 0x2b 0x07
# CHECK: movntss %xmm0, (%rdi)
0xf3 0x0f 0x2b 0x07
added basic support for Intel ADX instructions -feature flag, instructions definitions, test cases llvm-svn: 175196
2013-02-15 03:08:21 +08:00
# CHECK: adcxl %eax, %eax
0x66 0x0f 0x38 0xf6 0xc0
# CHECK: adcxl (%rax), %eax
0x66 0x0f 0x38 0xf6 0x00
# CHECK: adcxq %rax, %rax
0x66 0x48 0x0f 0x38 0xf6 0xc0
# CHECK: adcxq (%rax), %rax
0x66 0x48 0x0f 0x38 0xf6 0x00
# CHECK: adoxl %eax, %eax
0xf3 0x0f 0x38 0xf6 0xc0
# CHECK: adoxl (%rax), %eax
0xf3 0x0f 0x38 0xf6 0x00
# CHECK: adoxq %rax, %rax
0xf3 0x48 0x0f 0x38 0xf6 0xc0
# CHECK: adoxq (%rax), %rax
0xf3 0x48 0x0f 0x38 0xf6 0x00
Fixes disassembler crashes on 2013 Haswell RTM instructions. rdar://13318048 llvm-svn: 176828
2013-03-12 05:17:13 +08:00
# CHECK: xbegin 53
0xc7 0xf8 0x35 0x00 0x00 0x00
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
2015-01-06 16:59:30 +08:00
# CHECK: xbegin 53
0x66 0xc7 0xf8 0x35 0x00
Fixes disassembler crashes on 2013 Haswell RTM instructions. rdar://13318048 llvm-svn: 176828
2013-03-12 05:17:13 +08:00
# CHECK: xend
0x0f 0x01 0xd5
# CHECK: xabort $13
0xc6 0xf8 0x0d
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xsave64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x20
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xrstor64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x28
[X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. llvm-svn: 227963
2015-02-03 19:03:57 +08:00
# CHECK: xsaveopt64 (%rax)
fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases llvm-svn: 179223
2013-04-11 05:52:25 +08:00
0x48 0x0f 0xae 0x30
Add CLAC/STAC instruction encoding/decoding support As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. llvm-svn: 179266
2013-04-11 12:52:28 +08:00
# CHECK: clac
0x0f 0x01 0xca
# CHECK: stac
0x0f 0x01 0xcb
Fix the move to/from accumulator register instructions that use a full 64-bit absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 llvm-svn: 186878
2013-07-23 05:25:31 +08:00
# CHECK: movabsb -6066930261531658096, %al
0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb -6066930261531658096, %al
0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw -6066930261531658096, %ax
0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl -6066930261531658096, %eax
0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq -6066930261531658096, %rax
0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw %ax, -6066930261531658096
0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl %eax, -6066930261531658096
0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq %rax, -6066930261531658096
0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
Partial support for Intel SHA Extensions (sha1rnds4) Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. llvm-svn: 190611
2013-09-12 23:51:31 +08:00
# CHECK: sha1rnds4 $1, %xmm1, %xmm2
0x0f 0x3a 0xcc 0xd1 0x01
# CHECK: sha1rnds4 $1, (%rax), %xmm2
Add the remaining Intel SHA instructions Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. llvm-svn: 190754
2013-09-14 23:03:21 +08:00
0x0f 0x3a 0xcc 0x10 0x01
# CHECK: sha1nexte %xmm1, %xmm2
0x0f 0x38 0xc8 0xd1
# CHECK: sha1nexte (%rax), %xmm2
0x0f 0x38 0xc8 0x10
# CHECK: sha1msg1 %xmm1, %xmm2
0x0f 0x38 0xc9 0xd1
# CHECK: sha1msg1 (%rax), %xmm2
0x0f 0x38 0xc9 0x10
# CHECK: sha1msg2 %xmm1, %xmm2
0x0f 0x38 0xca 0xd1
# CHECK: sha1msg2 (%rax), %xmm2
0x0f 0x38 0xca 0x10
# CHECK: sha256rnds2 (%rax), %xmm2
0x0f 0x38 0xcb 0x10
# CHECK: sha256rnds2 %xmm1, %xmm2
0x0f 0x38 0xcb 0xd1
# CHECK: sha256msg1 %xmm1, %xmm2
0x0f 0x38 0xcc 0xd1
# CHECK: sha256msg1 (%rax), %xmm2
0x0f 0x38 0xcc 0x10
# CHECK: sha256msg2 %xmm1, %xmm2
0x0f 0x38 0xcd 0xd1
# CHECK: sha256msg2 (%rax), %xmm2
Add disassembler support for long encodings for INC/DEC in 32-bit mode. llvm-svn: 192086
2013-10-07 12:28:06 +08:00
0x0f 0x38 0xcd 0x10
# CHECK: incl %ecx
0xff 0xc1
# CHECK: decl %ecx
0xff 0xc9
# CHECK: incw %cx
0x66 0xff 0xc1
# CHECK: decw %cx
0x66 0xff 0xc9
# CHECK: incb %cl
0xfe 0xc1
# CHECK: decb %cl
0xfe 0xc9
# CHECK: incq %rcx
0x48 0xff 0xc1
# CHECK: decq %rcx
0x48 0xff 0xc9
Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
2013-10-07 15:19:47 +08:00
# CHECK: movq %xmm0, %xmm0
0xf3 0x0f 0x7e 0xc0
# CHECK: vmovq %xmm0, %xmm0
0xc5 0xfa 0x7e 0xc0
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
2013-10-08 13:53:50 +08:00
# CHECK: vmovq %xmm0, %rax
0xc4 0xe1 0xf9 0x7e 0xc0
[X86] Add some missing redundant MMX and SSE encodings for disassembler. llvm-svn: 230165
2015-02-22 15:50:41 +08:00
# CHECK: movd (%rax), %mm0
0x48 0x0f 0x6e 0x00
# CHECK: movd %rax, %mm0
0x48 0x0f 0x6e 0xc0
# CHECK: movd %mm0, (%rax)
0x48 0x0f 0x7e 0x00
# CHECK: movd %mm0, %rax
0x48 0x0f 0x7e 0xc0
# CHECK: movd (%rax), %xmm0
0x66 0x48 0x0f 0x6e 0x00
# CHECK: movd %rax, %xmm0
0x66 0x48 0x0f 0x6e 0xc0
# CHECK: movd %xmm0, (%rax)
0x66 0x48 0x0f 0x7e 0x00
Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. llvm-svn: 192171
2013-10-08 13:53:50 +08:00
# CHECK: movd %xmm0, %rax
0x66 0x48 0x0f 0x7e 0xc0
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. llvm-svn: 192566
2013-10-14 09:42:32 +08:00
# CHECK: pextrw $3, %xmm3, %ecx
0x66 0x0f 0x3a 0x15 0xd9 0x03
# CHECK: pextrw $3, %xmm3, (%rax)
0x66 0x0f 0x3a 0x15 0x18 0x03
Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. llvm-svn: 201507
2014-02-17 18:03:43 +08:00
# CHECK: $0, 305419896(,%r8)
0x43 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%r13,%r8)
0x43 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r8)
0x42 0x80 0x04 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r8)
0x42 0x80 0x84 0x05 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(,%r12)
0x42 0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp,%r12)
0x42 0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896
0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
# CHECK: $0, 305419896(%rbp)
0x80 0x84 0x25 0x78 0x56 0x34 0x12 0x00
[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. llvm-svn: 225099
2015-01-03 08:00:20 +08:00
# CHECK: movabsq 6510615555426900570, %rax
0x48 0xa1 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
# CHECK: movq 1515870810, %rax
0x67, 0x48 0xa1 0x5a 0x5a 0x5a 0x5a
# CHECK: movabsq %rax, 6510615555426900570
0x48 0xa3 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a 0x5a
# CHECK: movq %rax, 1515870810
0x67, 0x48 0xa3 0x5a 0x5a 0x5a 0x5a