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llvm-project/llvm/test/CodeGen/X86/slow-incdec.ll

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[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=INCDEC %s
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @inc(i32 %x) {
; INCDEC-LABEL: inc:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl %eax
; INCDEC-NEXT: retl
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
;
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; ADD-LABEL: inc:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, %eax
; ADD-NEXT: retl
%r = add i32 %x, 1
ret i32 %r
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
}
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @dec(i32 %x) {
; INCDEC-LABEL: dec:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: decl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: dec:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $-1, %eax
; ADD-NEXT: retl
%r = add i32 %x, -1
ret i32 %r
}
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @inc_size(i32 %x) optsize {
; INCDEC-LABEL: inc_size:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: inc_size:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, %eax
; ADD-NEXT: retl
%r = add i32 %x, 1
ret i32 %r
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
}
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @dec_size(i32 %x) optsize {
; INCDEC-LABEL: dec_size:
; INCDEC: # BB#0:
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: decl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: dec_size:
; ADD: # BB#0:
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $-1, %eax
; ADD-NEXT: retl
%r = add i32 %x, -1
ret i32 %r
}