maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Hexagon/rotl-i64.ll

24 lines
603 B
LLVM
Raw Normal View History

[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
; RUN: llc -march=hexagon < %s | FileCheck %s
[SelectionDAG] Provide default expansion for rotates Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
2018-06-12 20:49:36 +08:00
; CHECK: rol
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
; Function Attrs: nounwind
[Hexagon] Simplify CFG after atomic expansion This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
2018-08-03 06:17:53 +08:00
define fastcc void @f0(i64* %a0) #0 {
b0: ; preds = %b3, %b2
%v0 = load i64, i64* %a0, align 8, !tbaa !0
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
%v1 = lshr i64 %v0, 8
%v2 = shl i64 %v0, 56
%v3 = or i64 %v2, %v1
%v4 = xor i64 %v3, 0
%v5 = xor i64 %v4, 0
%v6 = add i64 0, %v5
[Hexagon] Simplify CFG after atomic expansion This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
2018-08-03 06:17:53 +08:00
store i64 %v6, i64* %a0, align 8, !tbaa !0
ret void
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
}
[SelectionDAG] Provide default expansion for rotates Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
2018-06-12 20:49:36 +08:00
attributes #0 = { nounwind "target-cpu"="hexagonv60" }
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
!0 = !{!1, !1, i64 0}
!1 = !{!"long long", !2}
!2 = !{!"omnipotent char", !3}
!3 = !{!"Simple C/C++ TBAA"}