forked from OSchip/llvm-project
97 lines
3.1 KiB
LLVM
97 lines
3.1 KiB
LLVM
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; RUN: llc -O3 -march=hexagon -hexagon-small-data-threshold=0 -disable-packetizer < %s | FileCheck %s
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; This test was orignally written to test that we don't save an entire double
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; register if only one of the integer registers needs to be saved. The problem
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; occurs in exception handling, which only emit information for the registers
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; in the callee saved list (and not complete double registers unless both
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; parts of the double registers are used).
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; Overtime, we evolved in to saving the double register and updating the debug
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; information to cover the entire double register.
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; Disable the packetizer to avoid complications caused by potentially
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; packetizing one of the stores with allocframe, which would change the
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; relative order of the stores with the CFI instructions.
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; CHECK: cfi_startproc
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; CHECK-DAG: cfi_offset r16
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; CHECK-DAG: cfi_offset r17
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; CHECK-DAG: cfi_offset r18
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; CHECK-DAG: cfi_offset r19
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; CHECK: memd(r29+{{.*}}) = r17:16
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; CHECK: memd(r29+{{.*}}) = r19:18
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%s.0 = type { i32 }
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@g0 = global i32 0, align 4
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@g1 = external constant i8*
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; Function Attrs: noreturn
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define void @f0(i64 %a0) #0 personality i8* bitcast (i32 (...)* @f2 to i8*) {
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b0:
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%v0 = alloca %s.0, align 4
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%v1 = trunc i64 %a0 to i32
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%v2 = lshr i64 %a0, 32
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%v3 = trunc i64 %v2 to i32
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%v4 = getelementptr inbounds %s.0, %s.0* %v0, i32 0, i32 0
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store i32 0, i32* %v4, align 4, !tbaa !0
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%v5 = load i32, i32* @g0, align 4, !tbaa !5
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%v6 = or i32 %v5, 1
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store i32 %v6, i32* @g0, align 4, !tbaa !5
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%v7 = call i8* @f1(i32 4) #1
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%v8 = bitcast i8* %v7 to i32*
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%v9 = bitcast %s.0* %v0 to i8*
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%v10 = getelementptr inbounds i8, i8* %v9, i32 %v3
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%v11 = bitcast i8* %v10 to %s.0*
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%v12 = and i32 %v1, 1
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%v13 = icmp eq i32 %v12, 0
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br i1 %v13, label %b2, label %b1
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b1: ; preds = %b0
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%v14 = bitcast i8* %v10 to i8**
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%v15 = load i8*, i8** %v14, align 4
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%v16 = add i32 %v1, -1
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%v17 = getelementptr i8, i8* %v15, i32 %v16
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%v18 = bitcast i8* %v17 to i32 (%s.0*)**
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%v19 = load i32 (%s.0*)*, i32 (%s.0*)** %v18, align 4
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br label %b3
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b2: ; preds = %b0
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%v20 = inttoptr i32 %v1 to i32 (%s.0*)*
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br label %b3
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b3: ; preds = %b2, %b1
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%v21 = phi i32 (%s.0*)* [ %v19, %b1 ], [ %v20, %b2 ]
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%v22 = invoke i32 %v21(%s.0* %v11)
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to label %b4 unwind label %b5
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b4: ; preds = %b3
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store i32 %v22, i32* %v8, align 4, !tbaa !5
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call void @f4(i8* %v7, i8* bitcast (i8** @g1 to i8*), i8* null) #2
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unreachable
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b5: ; preds = %b3
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%v23 = landingpad { i8*, i32 }
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cleanup
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call void @f3(i8* %v7) #1
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resume { i8*, i32 } %v23
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}
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declare i8* @f1(i32)
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declare i32 @f2(...)
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declare void @f3(i8*)
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declare void @f4(i8*, i8*, i8*)
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attributes #0 = { noreturn "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind }
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attributes #2 = { noreturn }
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!0 = !{!1, !2, i64 0}
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!1 = !{!"_ZTS1A", !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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!5 = !{!2, !2, i64 0}
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