forked from OSchip/llvm-project
48 lines
1.5 KiB
LLVM
48 lines
1.5 KiB
LLVM
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; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; r2 = round(r1:0):sat
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; r3 = cmpyiwh(r1:0, r2):<<1:rnd:sat
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; r0 = cmpyiwh(r1:0, r2*):<<1:rnd:sat
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; CHECK: round(r{{[0-9]*}}:{{[0-9]*}}):sat
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; CHECK: cmpyiwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}):<<1:rnd:sat
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; CHECK: cmpyrwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}*):<<1:rnd:sat
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; CHECK: cmpyiwh(r{{[0-9]*}}:{{[0-9]*}},r{{[0-9]*}}*):<<1:rnd:sat
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target triple = "hexagon"
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@g0 = global i32 0, align 4
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@g1 = global i32 0, align 4
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@g2 = global i32 0, align 4
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = alloca i32, align 4
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%v1 = alloca i32, align 4
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store i32 0, i32* %v0
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store i32 0, i32* %v1, align 4
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%v2 = call i32 @llvm.hexagon.A2.roundsat(i64 1)
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store i32 %v2, i32* @g1, align 4
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%v3 = call i32 @llvm.hexagon.M4.cmpyi.wh(i64 -2147483648, i32 -2147483648)
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store i32 %v3, i32* @g0, align 4
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%v4 = call i32 @llvm.hexagon.M4.cmpyr.whc(i64 2147483647, i32 2147483647)
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store i32 %v4, i32* @g2, align 4
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%v5 = call i32 @llvm.hexagon.M4.cmpyi.whc(i64 -2147483648, i32 -2147483648)
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ret i32 %v5
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.roundsat(i64) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.cmpyi.wh(i64, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.cmpyr.whc(i64, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.cmpyi.whc(i64, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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