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llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

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First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Remove trailing whitespace llvm-svn: 21422
2005-04-22 06:55:34 +08:00
//
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Remove trailing whitespace llvm-svn: 21422
2005-04-22 06:55:34 +08:00
//
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
//===----------------------------------------------------------------------===//
//
// This implements the TargetLowering class.
//
//===----------------------------------------------------------------------===//
#include "llvm/Target/TargetLowering.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
#include "llvm/CodeGen/Analysis.h"
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
#include "llvm/CodeGen/MachineFrameInfo.h"
Move getJTISymbol from MachineJumpTableInfo to MachineFunction, which is more convenient, and change getPICJumpTableRelocBaseExpr to take a MachineFunction to match. Next, move the X86 code that create a PICBase symbol to X86TargetLowering::getPICBaseSymbol from X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific library. This eliminates a 'gross hack', and allows us to implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now calls it. This in turn allows us to eliminate the X86AsmPrinter::printPICJumpTableSetLabel method, which was the only overload of printPICJumpTableSetLabel. llvm-svn: 94526
2010-01-26 14:28:43 +08:00
#include "llvm/CodeGen/MachineFunction.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/CodeGen/MachineJumpTableInfo.h"
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
#include "llvm/CodeGen/SelectionDAG.h"
Move all of the header files which are involved in modelling the LLVM IR into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
2013-01-02 19:36:10 +08:00
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/GlobalVariable.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
This patch is another step in the direction of adding vector select. In this patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
2011-06-01 20:51:46 +08:00
#include "llvm/Support/CommandLine.h"
assert(0) -> LLVM_UNREACHABLE. Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
2009-07-12 04:10:48 +08:00
#include "llvm/Support/ErrorHandling.h"
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. llvm-svn: 25803
2006-01-30 12:09:27 +08:00
#include "llvm/Support/MathExtras.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
Add missing standard headers. Patch by Joerg Sonnenberger! llvm-svn: 122193
2010-12-20 04:43:38 +08:00
#include <cctype>
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
using namespace llvm;
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
/// InitLibcallNames - Set default libcall names.
///
Minor fix. llvm-svn: 33149
2007-01-13 06:51:10 +08:00
static void InitLibcallNames(const char **Names) {
Proper name 16 bit libcalls llvm-svn: 70750
2009-05-03 21:14:08 +08:00
Names[RTLIB::SHL_I16] = "__ashlhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SHL_I32] = "__ashlsi3";
Names[RTLIB::SHL_I64] = "__ashldi3";
Add support for 128 bit shifts and 32 bit shifts on 16 bit machines. llvm-svn: 53458
2008-07-12 00:52:29 +08:00
Names[RTLIB::SHL_I128] = "__ashlti3";
Proper name 16 bit libcalls llvm-svn: 70750
2009-05-03 21:14:08 +08:00
Names[RTLIB::SRL_I16] = "__lshrhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SRL_I32] = "__lshrsi3";
Names[RTLIB::SRL_I64] = "__lshrdi3";
Add support for 128 bit shifts and 32 bit shifts on 16 bit machines. llvm-svn: 53458
2008-07-12 00:52:29 +08:00
Names[RTLIB::SRL_I128] = "__lshrti3";
Proper name 16 bit libcalls llvm-svn: 70750
2009-05-03 21:14:08 +08:00
Names[RTLIB::SRA_I16] = "__ashrhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SRA_I32] = "__ashrsi3";
Names[RTLIB::SRA_I64] = "__ashrdi3";
Add support for 128 bit shifts and 32 bit shifts on 16 bit machines. llvm-svn: 53458
2008-07-12 00:52:29 +08:00
Names[RTLIB::SRA_I128] = "__ashrti3";
Add 8 bit libcalls and make use of them for msp430 llvm-svn: 86384
2009-11-08 01:14:39 +08:00
Names[RTLIB::MUL_I8] = "__mulqi3";
Proper name 16 bit libcalls llvm-svn: 70750
2009-05-03 21:14:08 +08:00
Names[RTLIB::MUL_I16] = "__mulhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::MUL_I32] = "__mulsi3";
Names[RTLIB::MUL_I64] = "__muldi3";
Add support for 128 bit multiplicative operations. Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
2008-07-10 23:35:05 +08:00
Names[RTLIB::MUL_I128] = "__multi3";
Lower multiply with overflow checking to __mulo<mode> calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
2011-06-18 04:41:29 +08:00
Names[RTLIB::MULO_I32] = "__mulosi4";
Names[RTLIB::MULO_I64] = "__mulodi4";
Names[RTLIB::MULO_I128] = "__muloti4";
Add 8 bit libcalls and make use of them for msp430 llvm-svn: 86384
2009-11-08 01:14:39 +08:00
Names[RTLIB::SDIV_I8] = "__divqi3";
Properly handle sdiv / udiv / srem / urem libcalls llvm-svn: 70764
2009-05-03 21:18:16 +08:00
Names[RTLIB::SDIV_I16] = "__divhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SDIV_I32] = "__divsi3";
Names[RTLIB::SDIV_I64] = "__divdi3";
Add support for 128 bit multiplicative operations. Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
2008-07-10 23:35:05 +08:00
Names[RTLIB::SDIV_I128] = "__divti3";
Add 8 bit libcalls and make use of them for msp430 llvm-svn: 86384
2009-11-08 01:14:39 +08:00
Names[RTLIB::UDIV_I8] = "__udivqi3";
Typo llvm-svn: 71237
2009-05-09 02:50:54 +08:00
Names[RTLIB::UDIV_I16] = "__udivhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::UDIV_I32] = "__udivsi3";
Names[RTLIB::UDIV_I64] = "__udivdi3";
Add support for 128 bit multiplicative operations. Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
2008-07-10 23:35:05 +08:00
Names[RTLIB::UDIV_I128] = "__udivti3";
Add 8 bit libcalls and make use of them for msp430 llvm-svn: 86384
2009-11-08 01:14:39 +08:00
Names[RTLIB::SREM_I8] = "__modqi3";
Properly handle sdiv / udiv / srem / urem libcalls llvm-svn: 70764
2009-05-03 21:18:16 +08:00
Names[RTLIB::SREM_I16] = "__modhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SREM_I32] = "__modsi3";
Names[RTLIB::SREM_I64] = "__moddi3";
Add support for 128 bit multiplicative operations. Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
2008-07-10 23:35:05 +08:00
Names[RTLIB::SREM_I128] = "__modti3";
Add 8 bit libcalls and make use of them for msp430 llvm-svn: 86384
2009-11-08 01:14:39 +08:00
Names[RTLIB::UREM_I8] = "__umodqi3";
Fix typo llvm-svn: 70770
2009-05-03 21:19:57 +08:00
Names[RTLIB::UREM_I16] = "__umodhi3";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::UREM_I32] = "__umodsi3";
Names[RTLIB::UREM_I64] = "__umoddi3";
Add support for 128 bit multiplicative operations. Lack of these caused a bootstrap failure with Fortran on x86-64 with LegalizeTypes turned on. While there, be nice to 16 bit machines and support expansion of i32 too. llvm-svn: 53408
2008-07-10 23:35:05 +08:00
Names[RTLIB::UREM_I128] = "__umodti3";
Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs. rdar://8911343 llvm-svn: 128696
2011-04-01 08:42:02 +08:00
// These are generally not available.
Names[RTLIB::SDIVREM_I8] = 0;
Names[RTLIB::SDIVREM_I16] = 0;
Names[RTLIB::SDIVREM_I32] = 0;
Names[RTLIB::SDIVREM_I64] = 0;
Names[RTLIB::SDIVREM_I128] = 0;
Names[RTLIB::UDIVREM_I8] = 0;
Names[RTLIB::UDIVREM_I16] = 0;
Names[RTLIB::UDIVREM_I32] = 0;
Names[RTLIB::UDIVREM_I64] = 0;
Names[RTLIB::UDIVREM_I128] = 0;
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::NEG_I32] = "__negsi2";
Names[RTLIB::NEG_I64] = "__negdi2";
Names[RTLIB::ADD_F32] = "__addsf3";
Names[RTLIB::ADD_F64] = "__adddf3";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::ADD_F80] = "__addxf3";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SUB_F32] = "__subsf3";
Names[RTLIB::SUB_F64] = "__subdf3";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::SUB_F80] = "__subxf3";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::MUL_F32] = "__mulsf3";
Names[RTLIB::MUL_F64] = "__muldf3";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::MUL_F80] = "__mulxf3";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::DIV_F32] = "__divsf3";
Names[RTLIB::DIV_F64] = "__divdf3";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::DIV_F80] = "__divxf3";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::REM_F32] = "fmodf";
Names[RTLIB::REM_F64] = "fmod";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::REM_F80] = "fmodl";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::REM_PPCF128] = "fmodl";
Add an intrinsic and codegen support for fused multiply-accumulate. The intent is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
2011-07-09 05:39:21 +08:00
Names[RTLIB::FMA_F32] = "fmaf";
Names[RTLIB::FMA_F64] = "fma";
Names[RTLIB::FMA_F80] = "fmal";
Names[RTLIB::FMA_PPCF128] = "fmal";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::POWI_F32] = "__powisf2";
Names[RTLIB::POWI_F64] = "__powidf2";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::POWI_F80] = "__powixf2";
Names[RTLIB::POWI_PPCF128] = "__powitf2";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SQRT_F32] = "sqrtf";
Names[RTLIB::SQRT_F64] = "sqrt";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::SQRT_F80] = "sqrtl";
Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Add intrinsics for log, log2, log10, exp, exp2. No functional change (and no FE change to generate them). llvm-svn: 55753
2008-09-04 08:47:13 +08:00
Names[RTLIB::LOG_F32] = "logf";
Names[RTLIB::LOG_F64] = "log";
Names[RTLIB::LOG_F80] = "logl";
Names[RTLIB::LOG_PPCF128] = "logl";
Names[RTLIB::LOG2_F32] = "log2f";
Names[RTLIB::LOG2_F64] = "log2";
Names[RTLIB::LOG2_F80] = "log2l";
Names[RTLIB::LOG2_PPCF128] = "log2l";
Names[RTLIB::LOG10_F32] = "log10f";
Names[RTLIB::LOG10_F64] = "log10";
Names[RTLIB::LOG10_F80] = "log10l";
Names[RTLIB::LOG10_PPCF128] = "log10l";
Names[RTLIB::EXP_F32] = "expf";
Names[RTLIB::EXP_F64] = "exp";
Names[RTLIB::EXP_F80] = "expl";
Names[RTLIB::EXP_PPCF128] = "expl";
Names[RTLIB::EXP2_F32] = "exp2f";
Names[RTLIB::EXP2_F64] = "exp2";
Names[RTLIB::EXP2_F80] = "exp2l";
Names[RTLIB::EXP2_PPCF128] = "exp2l";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SIN_F32] = "sinf";
Names[RTLIB::SIN_F64] = "sin";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::SIN_F80] = "sinl";
Names[RTLIB::SIN_PPCF128] = "sinl";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::COS_F32] = "cosf";
Names[RTLIB::COS_F64] = "cos";
Output sinl for a long double FSIN node, not sin. Likewise fix up a bunch of other libcalls. While there I remove NEG_F32 and NEG_F64 since they are not used anywhere. This fixes 9 Ada ACATS failures. llvm-svn: 45833
2008-01-10 18:28:30 +08:00
Names[RTLIB::COS_F80] = "cosl";
Names[RTLIB::COS_PPCF128] = "cosl";
Add runtime library names for pow. llvm-svn: 42880
2007-10-12 07:09:10 +08:00
Names[RTLIB::POW_F32] = "powf";
Names[RTLIB::POW_F64] = "pow";
Names[RTLIB::POW_F80] = "powl";
Names[RTLIB::POW_PPCF128] = "powl";
Add libcalls for the new rounding opcodes. llvm-svn: 55133
2008-08-22 02:38:14 +08:00
Names[RTLIB::CEIL_F32] = "ceilf";
Names[RTLIB::CEIL_F64] = "ceil";
Names[RTLIB::CEIL_F80] = "ceill";
Names[RTLIB::CEIL_PPCF128] = "ceill";
Names[RTLIB::TRUNC_F32] = "truncf";
Names[RTLIB::TRUNC_F64] = "trunc";
Names[RTLIB::TRUNC_F80] = "truncl";
Names[RTLIB::TRUNC_PPCF128] = "truncl";
Names[RTLIB::RINT_F32] = "rintf";
Names[RTLIB::RINT_F64] = "rint";
Names[RTLIB::RINT_F80] = "rintl";
Names[RTLIB::RINT_PPCF128] = "rintl";
Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
Names[RTLIB::NEARBYINT_F64] = "nearbyint";
Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Names[RTLIB::FLOOR_F32] = "floorf";
Names[RTLIB::FLOOR_F64] = "floor";
Names[RTLIB::FLOOR_F80] = "floorl";
Names[RTLIB::FLOOR_PPCF128] = "floorl";
Turn calls to copysignl into an FCOPYSIGN node. Handle FCOPYSIGN nodes with ppc_f128 type by having the type legalizer turn these back into a call to copysignl. llvm-svn: 98514
2010-03-15 05:08:40 +08:00
Names[RTLIB::COPYSIGN_F32] = "copysignf";
Names[RTLIB::COPYSIGN_F64] = "copysign";
Names[RTLIB::COPYSIGN_F80] = "copysignl";
Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Make default expansion for FP16 <-> FP32 nodes into libcalls llvm-svn: 98501
2010-03-15 02:42:24 +08:00
Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Add the remaining fp_round libcalls: FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
2008-08-08 03:01:24 +08:00
Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Add a mysteriously missing libcall, FPTOSINT_F80_I32. Be nice to 16 bit machines by supporting FP_TO_XINT expansion for these. llvm-svn: 53407
2008-07-10 23:33:02 +08:00
Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Add support for expanding PPC 128 bit floats. For this it is convenient to permit floats to be used with EXTRACT_ELEMENT, so I tweaked things to allow that. I also added libcalls for ppcf128 to i32 forms of FP_TO_XINT, since they exist in libgcc and this case can certainly occur (and does occur in the testsuite) - before the i64 libcall was being used. Also, the XINT_TO_FP result seemed to be wrong when the argument is an i128: the wrong fudge factor was added (the i32 and i64 cases were handled directly, but the i128 code fell through to some generic softening code which seemed to think it was i64 to f32!). So I fixed it by adding a fudge factor that I found in my breakfast cereal. llvm-svn: 52739
2008-06-26 04:24:48 +08:00
Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Add support for expanding PPC 128 bit floats. For this it is convenient to permit floats to be used with EXTRACT_ELEMENT, so I tweaked things to allow that. I also added libcalls for ppcf128 to i32 forms of FP_TO_XINT, since they exist in libgcc and this case can certainly occur (and does occur in the testsuite) - before the i64 libcall was being used. Also, the XINT_TO_FP result seemed to be wrong when the argument is an i128: the wrong fudge factor was added (the i32 and i64 cases were handled directly, but the i128 code fell through to some generic softening code which seemed to think it was i64 to f32!). So I fixed it by adding a fudge factor that I found in my breakfast cereal. llvm-svn: 52739
2008-06-26 04:24:48 +08:00
Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Implement more support for fp-to-i128 and i128-to-fp conversions. llvm-svn: 48189
2008-03-11 07:03:31 +08:00
Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Add two missing SINT_TO_FP libcalls. llvm-svn: 53460
2008-07-12 00:57:02 +08:00
Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Codegen support for i128 SINT_TO_FP. llvm-svn: 47928
2008-03-05 09:08:17 +08:00
Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
It is pointless to turn a UINT_TO_FP into an SINT_TO_FP libcall plus additional operations: it might as well be a direct UINT_TO_FP libcall. So only turn it into an SINT_TO_FP if the target has special handling for SINT_TO_FP. llvm-svn: 53461
2008-07-12 01:00:14 +08:00
Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
It is pointless to turn a UINT_TO_FP into an SINT_TO_FP libcall plus additional operations: it might as well be a direct UINT_TO_FP libcall. So only turn it into an SINT_TO_FP if the target has special handling for SINT_TO_FP. llvm-svn: 53461
2008-07-12 01:00:14 +08:00
Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
Names[RTLIB::OEQ_F32] = "__eqsf2";
Names[RTLIB::OEQ_F64] = "__eqdf2";
Names[RTLIB::UNE_F32] = "__nesf2";
Names[RTLIB::UNE_F64] = "__nedf2";
Names[RTLIB::OGE_F32] = "__gesf2";
Names[RTLIB::OGE_F64] = "__gedf2";
Names[RTLIB::OLT_F32] = "__ltsf2";
Names[RTLIB::OLT_F64] = "__ltdf2";
Names[RTLIB::OLE_F32] = "__lesf2";
Names[RTLIB::OLE_F64] = "__ledf2";
Names[RTLIB::OGT_F32] = "__gtsf2";
Names[RTLIB::OGT_F64] = "__gtdf2";
Names[RTLIB::UO_F32] = "__unordsf2";
Names[RTLIB::UO_F64] = "__unorddf2";
Allow the target to override the ISD::CondCode that's to be used to test the result of the comparison libcall against zero. llvm-svn: 33701
2007-01-31 17:29:11 +08:00
Names[RTLIB::O_F32] = "__unordsf2";
Names[RTLIB::O_F64] = "__unorddf2";
Allow targets to define libcall names for mem(cpy,set,move) intrinsics, rather than hardcoding them in DAG lowering. llvm-svn: 77586
2009-07-30 17:12:56 +08:00
Names[RTLIB::MEMCPY] = "memcpy";
Names[RTLIB::MEMMOVE] = "memmove";
Names[RTLIB::MEMSET] = "memset";
Add a new codegen pass that normalizes dwarf exception handling code in preparation for code generation. The main thing it does is handle the case when eh.exception calls (and, in a future patch, eh.selector calls) are far away from landing pads. Right now in practice you only find eh.exception calls close to landing pads: either in a landing pad (the common case) or in a landing pad successor, due to loop passes shifting them about. However future exception handling improvements will result in calls far from landing pads: (1) Inlining of rewinds. Consider the following case: In function @f: ... invoke @g to label %normal unwind label %unwinds ... unwinds: %ex = call i8* @llvm.eh.exception() ... In function @g: ... invoke @something to label %continue unwind label %handler ... handler: %ex = call i8* @llvm.eh.exception() ... perform cleanups ... "rethrow exception" Now inline @g into @f. Currently this is turned into: In function @f: ... invoke @something to label %continue unwind label %handler ... handler: %ex = call i8* @llvm.eh.exception() ... perform cleanups ... invoke "rethrow exception" to label %normal unwind label %unwinds unwinds: %ex = call i8* @llvm.eh.exception() ... However we would like to simplify invoke of "rethrow exception" into a branch to the %unwinds label. Then %unwinds is no longer a landing pad, and the eh.exception call there is then far away from any landing pads. (2) Using the unwind instruction for cleanups. It would be nice to have codegen handle the following case: invoke @something to label %continue unwind label %run_cleanups ... handler: ... perform cleanups ... unwind This requires turning "unwind" into a library call, which necessarily takes a pointer to the exception as an argument (this patch also does this unwind lowering). But that means you are using eh.exception again far from a landing pad. (3) Bugpoint simplifications. When bugpoint is simplifying exception handling code it often generates eh.exception calls far from a landing pad, which then causes codegen to assert. Bugpoint then latches on to this assertion and loses sight of the original problem. Note that it is currently rare for this pass to actually do anything. And in fact it normally shouldn't do anything at all given the code coming out of llvm-gcc! But it does fire a few times in the testsuite. As far as I can see this is almost always due to the LoopStrengthReduce codegen pass introducing pointless loop preheader blocks which are landing pads and only contain a branch to another block. This other block contains an eh.exception call. So probably by tweaking LoopStrengthReduce a bit this can be avoided. llvm-svn: 72276
2009-05-23 04:36:31 +08:00
Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Add Expand-to-libcall support for additional atomics. This covers the usual entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
2010-06-19 05:43:38 +08:00
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) llvm-svn: 106342
2010-06-19 07:03:10 +08:00
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Add Expand-to-libcall support for additional atomics. This covers the usual entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
2010-06-19 05:43:38 +08:00
Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
Fix typo. "__sync_fetch_and-xor_4" should be "__sync_fetch_and_xor_4". Pointed out by George Russell. llvm-svn: 141956
2011-10-14 23:53:48 +08:00
Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
Add Expand-to-libcall support for additional atomics. This covers the usual entries used by llvm-gcc. *_[U]MIN and such can be added later if needed. This enables the front ends to simplify handling of the atomic intrinsics by removing the target-specific decision about which targets can handle the intrinsics. llvm-svn: 106321
2010-06-19 05:43:38 +08:00
Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Allow the target to override the ISD::CondCode that's to be used to test the result of the comparison libcall against zero. llvm-svn: 33701
2007-01-31 17:29:11 +08:00
}
Allow targets to specify their choice of calling conventions per libcall. Take advantage of this in the ARM backend to rectify broken choice of CC when hard float is in effect. PIC16 may want to see if it could be of use in MakePIC16Libcall, which works unchanged. Patch by Sandeep! llvm-svn: 79033
2009-08-15 04:10:52 +08:00
/// InitLibcallCallingConvs - Set default libcall CallingConvs.
///
static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
CCs[i] = CallingConv::C;
}
}
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::f32) {
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPEXT_F32_F64;
}
Make default expansion for FP16 <-> FP32 nodes into libcalls llvm-svn: 98501
2010-03-15 02:42:24 +08:00
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UNKNOWN_LIBCALL;
}
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::f32) {
if (OpVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPROUND_F64_F32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::f80)
Add the remaining fp_round libcalls: FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
2008-08-08 03:01:24 +08:00
return FPROUND_F80_F32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::ppcf128)
Add the remaining fp_round libcalls: FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
2008-08-08 03:01:24 +08:00
return FPROUND_PPCF128_F32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (RetVT == MVT::f64) {
if (OpVT == MVT::f80)
Add the remaining fp_round libcalls: FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
2008-08-08 03:01:24 +08:00
return FPROUND_F80_F64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::ppcf128)
Add the remaining fp_round libcalls: FPROUND_F80_F32, FPROUND_PPCF128_F32, FPROUND_F80_F64, FPROUND_PPCF128_F64 Support for soften float fp_round operands is added, Mips needs this to round f64->f32. Also added support to soften float FABS result, Mips doesn't support double fabs results while in 'single float only' mode. llvm-svn: 54484
2008-08-08 03:01:24 +08:00
return FPROUND_PPCF128_F64;
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
}
Make default expansion for FP16 <-> FP32 nodes into libcalls llvm-svn: 98501
2010-03-15 02:42:24 +08:00
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UNKNOWN_LIBCALL;
}
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::f32) {
if (RetVT == MVT::i8)
Added required libcalls for PIC16 (mostly floating points to integer casting operations). llvm-svn: 73480
2009-06-16 17:03:58 +08:00
return FPTOSINT_F32_I8;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i16)
Added required libcalls for PIC16 (mostly floating points to integer casting operations). llvm-svn: 73480
2009-06-16 17:03:58 +08:00
return FPTOSINT_F32_I16;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F32_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F32_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F32_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::f64) {
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
if (RetVT == MVT::i8)
return FPTOSINT_F64_I8;
if (RetVT == MVT::i16)
return FPTOSINT_F64_I16;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F64_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F64_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F64_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::f80) {
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F80_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F80_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_F80_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::ppcf128) {
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_PPCF128_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_PPCF128_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOSINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
}
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::f32) {
if (RetVT == MVT::i8)
Added required libcalls for PIC16 (mostly floating points to integer casting operations). llvm-svn: 73480
2009-06-16 17:03:58 +08:00
return FPTOUINT_F32_I8;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i16)
Added required libcalls for PIC16 (mostly floating points to integer casting operations). llvm-svn: 73480
2009-06-16 17:03:58 +08:00
return FPTOUINT_F32_I16;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F32_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F32_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F32_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::f64) {
Add few missed libcalls and correct names for others. llvm-svn: 99656
2010-03-27 05:32:14 +08:00
if (RetVT == MVT::i8)
return FPTOUINT_F64_I8;
if (RetVT == MVT::i16)
return FPTOUINT_F64_I16;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F64_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F64_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F64_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::f80) {
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F80_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F80_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_F80_I128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::ppcf128) {
if (RetVT == MVT::i32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_PPCF128_I32;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_PPCF128_I64;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (RetVT == MVT::i128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return FPTOUINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
}
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::i32) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I32_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I32_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I32_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I32_PPCF128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::i64) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I64_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I64_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I64_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I64_PPCF128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::i128) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I128_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I128_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I128_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return SINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
}
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (OpVT == MVT::i32) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I32_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I32_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I32_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I32_PPCF128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::i64) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I64_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I64_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I64_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I64_PPCF128;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
} else if (OpVT == MVT::i128) {
if (RetVT == MVT::f32)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I128_F32;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f64)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I128_F64;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::f80)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I128_F80;
Remove a bunch of 'else's after 'returns' llvm-svn: 170496
2012-12-19 14:39:17 +08:00
if (RetVT == MVT::ppcf128)
Factorize some code for determining which libcall to use. llvm-svn: 53713
2008-07-17 10:36:29 +08:00
return UINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
}
Allow the target to override the ISD::CondCode that's to be used to test the result of the comparison libcall against zero. llvm-svn: 33701
2007-01-31 17:29:11 +08:00
/// InitCmpLibcallCCs - Set default comparison libcall CC.
///
static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
CCs[RTLIB::UNE_F32] = ISD::SETNE;
CCs[RTLIB::UNE_F64] = ISD::SETNE;
CCs[RTLIB::OGE_F32] = ISD::SETGE;
CCs[RTLIB::OGE_F64] = ISD::SETGE;
CCs[RTLIB::OLT_F32] = ISD::SETLT;
CCs[RTLIB::OLT_F64] = ISD::SETLT;
CCs[RTLIB::OLE_F32] = ISD::SETLE;
CCs[RTLIB::OLE_F64] = ISD::SETLE;
CCs[RTLIB::OGT_F32] = ISD::SETGT;
CCs[RTLIB::OGT_F64] = ISD::SETGT;
CCs[RTLIB::UO_F32] = ISD::SETNE;
CCs[RTLIB::UO_F64] = ISD::SETNE;
CCs[RTLIB::O_F32] = ISD::SETEQ;
CCs[RTLIB::O_F64] = ISD::SETEQ;
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
}
Rip all of the global variable lowering logic out of TargetAsmInfo. Since it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. llvm-svn: 77294
2009-07-28 11:13:23 +08:00
/// NOTE: The constructor takes ownership of TLOF.
Add more const qualifiers on TargetMachine and friends. llvm-svn: 101977
2010-04-21 09:34:56 +08:00
TargetLowering::TargetLowering(const TargetMachine &tm,
const TargetLoweringObjectFile *tlof)
Move TargetData to DataLayout. llvm-svn: 165402
2012-10-09 00:38:25 +08:00
: TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) {
Use enums, move virtual dtor out of line. llvm-svn: 19610
2005-01-16 15:28:11 +08:00
// All operations default to being supported.
memset(OpActions, 0, sizeof(OpActions));
Rename LoadX to LoadExt. llvm-svn: 57526
2008-10-15 05:26:46 +08:00
memset(LoadExtActions, 0, sizeof(LoadExtActions));
This commit changes: 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret llvm-svn: 46140
2008-01-18 03:59:44 +08:00
memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
remove extraneous &'s. llvm-svn: 46171
2008-01-19 03:36:20 +08:00
memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
- Add target lowering hooks that specify which setcc conditions are illegal, i.e. conditions that cannot be checked with a single instruction. For example, SETONE and SETUEQ on x86. - Teach legalizer to implement *illegal* setcc as a and / or of a number of legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ. - Move x86 target over. llvm-svn: 57542
2008-10-15 10:05:31 +08:00
memset(CondCodeActions, 0, sizeof(CondCodeActions));
Initialize the IndexedModeActions array with memset before updating it with calls to setIndexedLoadAction/setIndexedStoreAction, which only update a few bits at a time. This avoids ostensible undefined behavior of operationg on values which may be trap-representations, and as a practical matter fixes errors from valgrind, which doesn't track uninitialized memory with bit granularity. llvm-svn: 38468
2007-07-10 04:49:44 +08:00
Add a new FGETSIGN operation, which defaults to expand on all targets. llvm-svn: 45320
2007-12-23 04:47:56 +08:00
// Set default actions for various operations.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Add a new FGETSIGN operation, which defaults to expand on all targets. llvm-svn: 45320
2007-12-23 04:47:56 +08:00
// Default all indexed load / store to expand.
Add a mechanism to specify whether a target supports a particular indexed load / store. llvm-svn: 31597
2006-11-10 02:56:43 +08:00
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Add a mechanism to specify whether a target supports a particular indexed load / store. llvm-svn: 31597
2006-11-10 02:56:43 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a new FGETSIGN operation, which defaults to expand on all targets. llvm-svn: 45320
2007-12-23 04:47:56 +08:00
// These operations default to expand.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Add a mechanism to specify whether a target supports a particular indexed load / store. llvm-svn: 31597
2006-11-10 02:56:43 +08:00
}
Default ISD::PREFETCH to expand. llvm-svn: 48169
2008-03-11 03:38:10 +08:00
// Most targets ignore the @llvm.prefetch intrinsic.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// ConstantFP nodes default to expand. Targets can either change this to
Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target. llvm-svn: 85281
2009-10-28 03:56:55 +08:00
// Legal, in which case all fp constants are legal, or use isFPImmLegal()
Change how FP immediates are handled. 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
2008-02-14 16:57:00 +08:00
// to optimize expansions for certain constants.
Add basic generic CodeGen support for half. llvm-svn: 146927
2011-12-20 08:02:33 +08:00
setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
Make log, log2, log10, exp, exp2 use Expand by default. llvm-svn: 56471
2008-09-23 05:57:32 +08:00
// These library functions default to expand.
Add basic generic CodeGen support for half. llvm-svn: 146927
2011-12-20 08:02:33 +08:00
setOperationAction(ISD::FLOG , MVT::f16, Expand);
setOperationAction(ISD::FLOG2, MVT::f16, Expand);
setOperationAction(ISD::FLOG10, MVT::f16, Expand);
setOperationAction(ISD::FEXP , MVT::f16, Expand);
setOperationAction(ISD::FEXP2, MVT::f16, Expand);
setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
setOperationAction(ISD::FCEIL, MVT::f16, Expand);
setOperationAction(ISD::FRINT, MVT::f16, Expand);
setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
Teach SelectionDAG to match more calls to libm functions onto existing SDNodes. Mark these nodes as illegal by default, unless the target declares otherwise. llvm-svn: 146171
2011-12-09 03:32:14 +08:00
setOperationAction(ISD::FLOG , MVT::f32, Expand);
setOperationAction(ISD::FLOG2, MVT::f32, Expand);
setOperationAction(ISD::FLOG10, MVT::f32, Expand);
setOperationAction(ISD::FEXP , MVT::f32, Expand);
setOperationAction(ISD::FEXP2, MVT::f32, Expand);
setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
setOperationAction(ISD::FCEIL, MVT::f32, Expand);
setOperationAction(ISD::FRINT, MVT::f32, Expand);
setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
Add basic generic CodeGen support for half. llvm-svn: 146927
2011-12-20 08:02:33 +08:00
setOperationAction(ISD::FLOG , MVT::f64, Expand);
setOperationAction(ISD::FLOG2, MVT::f64, Expand);
setOperationAction(ISD::FLOG10, MVT::f64, Expand);
setOperationAction(ISD::FEXP , MVT::f64, Expand);
setOperationAction(ISD::FEXP2, MVT::f64, Expand);
setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
setOperationAction(ISD::FCEIL, MVT::f64, Expand);
setOperationAction(ISD::FRINT, MVT::f64, Expand);
setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
Make log, log2, log10, exp, exp2 use Expand by default. llvm-svn: 56471
2008-09-23 05:57:32 +08:00
Add support for targets that have a legal ISD::TRAP. llvm-svn: 46014
2008-01-16 05:58:08 +08:00
// Default ISD::TRAP to expand (which turns it into abort).
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
setOperationAction(ISD::TRAP, MVT::Other, Expand);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
This patch is to fix radar://8426430. It is about llvm support of __builtin_debugtrap() which is supposed to consistently raise SIGTRAP across all systems. In contrast, __builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap" functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap(). The X86 backend is already able to handle debugtrap(). This patch is to: 1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang). 2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which make the __builtin_debugtrap() "available" to all existing ports without the hassle of changing their code. 3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and __builtin_trap() will be expanded into the function call of the specified trap function. This behavior may need change in the future. The provided testing-case is to make sure 2) and 3) are working for ARM port, and we already have a testing case for x86. llvm-svn: 166300
2012-10-20 04:11:16 +08:00
// On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
// here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
//
setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. This fixes PR 759. llvm-svn: 28074
2006-05-03 09:29:57 +08:00
IsLittleEndian = TD->isLittleEndian();
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
2012-10-10 00:06:12 +08:00
PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0));
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Add lengthof and endof templates that hide a lot of sizeof computations. Patch by Sterling Stein! llvm-svn: 41758
2007-09-07 12:06:50 +08:00
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Rename maxStoresPerMemSet to maxStoresPerMemset, etc. llvm-svn: 26174
2006-02-14 16:38:30 +08:00
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. llvm-svn: 122952
2011-01-06 14:52:41 +08:00
maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
= maxStoresPerMemmoveOptSize = 4;
Run code placement optimization for targets that want it (arm and x86 for now). llvm-svn: 71726
2009-05-14 05:42:09 +08:00
benefitFromCodePlacementOpt = false;
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right code (both asm & cbe) for Mingw32 target. Removed autoconf checks for underscored versions of setjmp/longjmp. llvm-svn: 32415
2006-12-11 07:12:42 +08:00
UseUnderscoreSetJmp = false;
UseUnderscoreLongJmp = false;
initialize a instance variable llvm-svn: 34567
2007-02-25 09:28:05 +08:00
SelectIsExpensive = false;
Invert the TargetLowering flag that controls divide by consant expansion. Add a new flag to TargetLowering indicating if the target has really cheap signed division by powers of two, make ppc use it. This will probably go away in the future. Implement some more ISD::SDIV folds in the dag combiner Remove now dead code in the x86 backend. llvm-svn: 23853
2005-10-21 08:02:42 +08:00
IntDivIsCheap = false;
Pow2DivIsCheap = false;
add TLI support indicating that jumps are more expensive than logical operations and use this to disable a specific optimization. Patch by Micah Villmow! llvm-svn: 120435
2010-12-01 02:12:52 +08:00
JumpIsExpensive = false;
Add a new target hook "predictableSelectIsExpensive". This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
2012-05-05 20:49:14 +08:00
predictableSelectIsExpensive = false;
initialize an instance var, apparently I forgot to commit this long ago llvm-svn: 25609
2006-01-26 02:57:15 +08:00
StackPointerRegisterToSaveRestore = 0;
Need to init. llvm-svn: 34499
2007-02-23 02:04:49 +08:00
ExceptionPointerRegister = 0;
ExceptionSelectorRegister = 0;
Rename SetCCResultContents to BooleanContents. In practice these booleans are mostly produced by SetCC, however the concept is more general. llvm-svn: 59911
2008-11-23 23:47:28 +08:00
BooleanContents = UndefinedBooleanContent;
Add codegen support for vector select (in the IR this means a select with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
2011-09-07 03:07:46 +08:00
BooleanVectorContents = UndefinedBooleanContent;
Change the default scheduler from Latency to ILP, since Latency is going away. llvm-svn: 142810
2011-10-25 01:45:02 +08:00
SchedPreferenceInfo = Sched::ILP;
Change the default to 0, which means 'default'. llvm-svn: 30114
2006-09-06 01:39:15 +08:00
JumpBufSize = 0;
forgot this llvm-svn: 30097
2006-09-04 15:44:11 +08:00
JumpBufAlignment = 0;
Make the logic for determining function alignment more explicit. No functionality change. llvm-svn: 131012
2011-05-07 04:34:06 +08:00
MinFunctionAlignment = 0;
PrefFunctionAlignment = 0;
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries. llvm-svn: 47703
2008-02-28 08:43:03 +08:00
PrefLoopAlignment = 0;
Fix va_arg for doubles. With this patch VAARG nodes always contain the correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
2010-07-11 12:01:49 +08:00
MinStackArgumentAlignment = 1;
Some targets don't require the fencing MEMBARRIER instructions surrounding atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. llvm-svn: 106630
2010-06-24 00:07:42 +08:00
ShouldFoldAtomicFences = false;
New approach to r136737: insert the necessary fences for atomic ops in platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. llvm-svn: 136813
2011-08-04 05:06:02 +08:00
InsertFencesForAtomic = false;
Target option DisableJumpTables is a gross hack. Move it to TargetLowering instead. llvm-svn: 159611
2012-07-03 06:39:56 +08:00
SupportJumpTables = true;
TargetLowering interface to set/get minimum block entries for jump tables. Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. llvm-svn: 164628
2012-09-26 04:35:36 +08:00
MinimumJumpTableEntries = 4;
Store default libgcc routine names and allow them to be redefined by target. llvm-svn: 33105
2007-01-12 10:11:51 +08:00
InitLibcallNames(LibcallRoutineNames);
Allow the target to override the ISD::CondCode that's to be used to test the result of the comparison libcall against zero. llvm-svn: 33701
2007-01-31 17:29:11 +08:00
InitCmpLibcallCCs(CmpLibcallCCs);
Allow targets to specify their choice of calling conventions per libcall. Take advantage of this in the ARM backend to rectify broken choice of CC when hard float is in effect. PIC16 may want to see if it could be of use in MakePIC16Libcall, which works unchanged. Patch by Sandeep! llvm-svn: 79033
2009-08-15 04:10:52 +08:00
InitLibcallCallingConvs(LibcallCallingConvs);
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
}
Rip all of the global variable lowering logic out of TargetAsmInfo. Since it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. llvm-svn: 77294
2009-07-28 11:13:23 +08:00
TargetLowering::~TargetLowering() {
delete &TLOF;
}
Use enums, move virtual dtor out of line. llvm-svn: 19610
2005-01-16 15:28:11 +08:00
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
2012-10-10 00:06:12 +08:00
return MVT::getIntegerVT(8*TD->getPointerSize(0));
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
}
The previous fix of widening divides that trap was too fragile as it depends on custom lowering and requires that certain types exist in ValueTypes.h. Modified widening to check if an op can trap and if so, the widening algorithm will apply only the op on the defined elements. It is safer to do this in widening because the optimizer can't guarantee removing unused ops in some cases. llvm-svn: 95823
2010-02-11 07:37:45 +08:00
/// canOpTrap - Returns true if the operation can trap for the value type.
/// VT must be a legal type.
bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
assert(isTypeLegal(VT));
switch (Op) {
default:
return false;
case ISD::FDIV:
case ISD::FREM:
case ISD::SDIV:
case ISD::UDIV:
case ISD::SREM:
case ISD::UREM:
return true;
}
}
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
random tidying llvm-svn: 107612
2010-07-05 13:36:21 +08:00
unsigned &NumIntermediates,
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
MVT &RegisterVT,
random tidying llvm-svn: 107612
2010-07-05 13:36:21 +08:00
TargetLowering *TLI) {
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = VT.getVectorNumElements();
MVT EltTy = VT.getVectorElementType();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
unsigned NumVectorRegs = 1;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
// could break down into LHS/RHS like LegalizeDAG does.
if (!isPowerOf2_32(NumElts)) {
NumVectorRegs = NumElts;
NumElts = 1;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
NumIntermediates = NumVectorRegs;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
if (!TLI->isTypeLegal(NewVT))
NewVT = EltTy;
IntermediateVT = NewVT;
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
2011-06-12 22:56:55 +08:00
unsigned NewVTSize = NewVT.getSizeInBits();
// Convert sizes such as i33 to i64.
if (!isPowerOf2_32(NewVTSize))
NewVTSize = NextPowerOf2(NewVTSize);
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of EVTs. llvm-svn: 170535
2012-12-19 19:48:16 +08:00
MVT DestVT = TLI->getRegisterType(NewVT);
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
RegisterVT = DestVT;
more tidying. llvm-svn: 107615
2010-07-05 13:53:14 +08:00
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
2011-06-12 22:56:55 +08:00
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
more tidying. llvm-svn: 107615
2010-07-05 13:53:14 +08:00
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.
return NumVectorRegs;
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
}
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
2010-07-20 02:47:01 +08:00
/// isLegalRC - Return true if the value types that can be represented by the
/// specified register class are all legal.
bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
I != E; ++I) {
if (isTypeLegal(*I))
return true;
}
return false;
}
/// findRepresentativeClass - Return the largest legal super-reg register class
Teach bottom up pre-ra scheduler to track register pressure. Work in progress. llvm-svn: 108991
2010-07-21 14:09:07 +08:00
/// of the register class for the specified type and its associated "cost".
std::pair<const TargetRegisterClass*, uint8_t>
Change TargetLowering::findRepresentativeClass to take an MVT, instead of EVT. llvm-svn: 170532
2012-12-19 19:30:36 +08:00
TargetLowering::findRepresentativeClass(MVT VT) const {
Use SuperRegClassIterator for findRepresentativeClass(). The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
2012-05-04 10:19:22 +08:00
const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
Change TargetLowering::findRepresentativeClass to take an MVT, instead of EVT. llvm-svn: 170532
2012-12-19 19:30:36 +08:00
const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
Teach bottom up pre-ra scheduler to track register pressure. Work in progress. llvm-svn: 108991
2010-07-21 14:09:07 +08:00
if (!RC)
return std::make_pair(RC, 0);
Use SuperRegClassIterator for findRepresentativeClass(). The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
2012-05-04 10:19:22 +08:00
// Compute the set of all super-register classes.
BitVector SuperRegRC(TRI->getNumRegClasses());
Make sure findRepresentativeClass picks the widest super-register. We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
2012-05-05 06:53:28 +08:00
for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
Use SuperRegClassIterator for findRepresentativeClass(). The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
2012-05-04 10:19:22 +08:00
SuperRegRC.setBitsInMask(RCI.getMask());
Make sure findRepresentativeClass picks the widest super-register. We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
2012-05-05 06:53:28 +08:00
// Find the first legal register class with the largest spill size.
const TargetRegisterClass *BestRC = RC;
Use SuperRegClassIterator for findRepresentativeClass(). The masks returned by SuperRegClassIterator are computed automatically by TableGen. This is better than depending on the manually specified SuperRegClasses. llvm-svn: 156147
2012-05-04 10:19:22 +08:00
for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
Make sure findRepresentativeClass picks the widest super-register. We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
2012-05-05 06:53:28 +08:00
// We want the largest possible spill size.
if (SuperRC->getSize() <= BestRC->getSize())
continue;
if (!isLegalRC(SuperRC))
continue;
BestRC = SuperRC;
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
2010-07-20 02:47:01 +08:00
}
Make sure findRepresentativeClass picks the widest super-register. We want the representative register class to contain the largest super-registers available. This makes the function less sensitive to the register class numbering. llvm-svn: 156220
2012-05-05 06:53:28 +08:00
return std::make_pair(BestRC, 1);
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
2010-07-20 02:47:01 +08:00
}
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Move some information out of LegalizeDAG into the generic Target interface. llvm-svn: 19581
2005-01-16 09:10:58 +08:00
"Too many value types for ValueTypeActions to hold!");
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
// Everything defaults to needing one register.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Rename TargetLowering::getNumElements and friends to TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. llvm-svn: 37687
2007-06-21 22:42:22 +08:00
NumRegistersForVT[i] = 1;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
}
// ...except isVoid, which doesn't need any registers.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
NumRegistersForVT[MVT::isVoid] = 0;
Remove trailing whitespace llvm-svn: 21422
2005-04-22 06:55:34 +08:00
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
// Find the largest integer register class.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
Cleanup: Simplify loop end logic in computeRegisterProperties(). llvm-svn: 168507
2012-11-23 16:35:04 +08:00
for (unsigned ExpandedReg = LargestIntReg + 1;
ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
Rename TargetLowering::getNumElements and friends to TargetLowering::getNumRegisters and similar, to avoid confusion with the actual number of elements for vector types. llvm-svn: 37687
2007-06-21 22:42:22 +08:00
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Cleanup: Simplify loop end logic in computeRegisterProperties(). llvm-svn: 168507
2012-11-23 16:35:04 +08:00
ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
TypeExpandInteger);
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
}
First draft of new Target interface llvm-svn: 19324
2005-01-07 15:44:53 +08:00
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
// Inspect all of the ValueType's smaller than the largest integer
// register to see which ones need promotion.
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
IntReg >= (unsigned)MVT::i1; --IntReg) {
Change TargetLowering::setTypeAction to take an MVT, instead fo EVT. llvm-svn: 170148
2012-12-14 04:42:43 +08:00
MVT IVT = (MVT::SimpleValueType)IntReg;
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
if (isTypeLegal(IVT)) {
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
LegalIntReg = IntReg;
} else {
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Stop casting away const qualifier needlessly. llvm-svn: 163258
2012-09-06 06:26:57 +08:00
(const MVT::SimpleValueType)LegalIntReg;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
}
}
Remove trailing whitespace llvm-svn: 21422
2005-04-22 06:55:34 +08:00
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
// ppcf128 type is really two f64's.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (!isTypeLegal(MVT::ppcf128)) {
NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
TransformToType[MVT::ppcf128] = MVT::f64;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
First round of ppc long double. call/return and basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
2007-10-06 04:04:43 +08:00
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (!isTypeLegal(MVT::f64)) {
NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
TransformToType[MVT::f64] = MVT::i64;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
Preliminary soft float support. llvm-svn: 32394
2006-12-09 10:42:38 +08:00
}
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
// Decide how to handle f32. If the target does not have native support for
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (!isTypeLegal(MVT::f32)) {
if (isTypeLegal(MVT::f64)) {
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
TransformToType[MVT::f32] = MVT::f64;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
} else {
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
TransformToType[MVT::f32] = MVT::i32;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
}
Preliminary soft float support. llvm-svn: 32394
2006-12-09 10:42:38 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
// Loop over all of the vector value types to see which need transformations.
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
MVT VT = (MVT::SimpleValueType)i;
random tidying llvm-svn: 107612
2010-07-05 13:36:21 +08:00
if (isTypeLegal(VT)) continue;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
// Determine if there is a legal wider type. If so, we should promote to
// that wider vector type.
Change TargetLowering::TransformToType to contain MVTs, instead of EVTs. llvm-svn: 170534
2012-12-19 19:42:00 +08:00
MVT EltVT = VT.getVectorElementType();
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
unsigned NElts = VT.getVectorNumElements();
Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. llvm-svn: 168882
2012-11-29 22:26:24 +08:00
if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) {
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
bool IsLegalWiderType = false;
TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
2011-06-05 04:32:01 +08:00
// First try to promote the elements of integer vectors. If no legal
// promotion was found, fallback to the widen-vector method.
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
Change TargetLowering::TransformToType to contain MVTs, instead of EVTs. llvm-svn: 170534
2012-12-19 19:42:00 +08:00
MVT SVT = (MVT::SimpleValueType)nVT;
TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
2011-06-05 04:32:01 +08:00
// Promote vectors of integers to vectors with the same number
// of elements, with a wider element type.
if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
&& SVT.getVectorNumElements() == NElts &&
isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
TransformToType[i] = SVT;
RegisterTypeForVT[i] = SVT;
NumRegistersForVT[i] = 1;
ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
IsLegalWiderType = true;
break;
This patch is another step in the direction of adding vector select. In this patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
2011-06-01 20:51:46 +08:00
}
TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
2011-06-05 04:32:01 +08:00
}
if (IsLegalWiderType) continue;
This patch is another step in the direction of adding vector select. In this patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. llvm-svn: 132394
2011-06-01 20:51:46 +08:00
TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. llvm-svn: 132648
2011-06-05 04:32:01 +08:00
// Try to widen the vector.
for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
Change TargetLowering::TransformToType to contain MVTs, instead of EVTs. llvm-svn: 170534
2012-12-19 19:42:00 +08:00
MVT SVT = (MVT::SimpleValueType)nVT;
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
if (SVT.getVectorElementType() == EltVT &&
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
SVT.getVectorNumElements() > NElts &&
Remove Synthesizable from the Type system; as MMX vector types are no longer Legal on X86, we don't need it. No functional change. 8499854. llvm-svn: 116947
2010-10-21 05:32:10 +08:00
isTypeLegal(SVT)) {
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
TransformToType[i] = SVT;
RegisterTypeForVT[i] = SVT;
NumRegistersForVT[i] = 1;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
IsLegalWiderType = true;
break;
}
}
if (IsLegalWiderType) continue;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
random tidying llvm-svn: 107612
2010-07-05 13:36:21 +08:00
MVT IntermediateVT;
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
MVT RegisterVT;
random tidying llvm-svn: 107612
2010-07-05 13:36:21 +08:00
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
RegisterVT, this);
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
RegisterTypeForVT[i] = RegisterVT;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Change TargetLowering::TransformToType to contain MVTs, instead of EVTs. llvm-svn: 170534
2012-12-19 19:42:00 +08:00
MVT NVT = VT.getPow2VectorType();
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
TransformToType[i] = MVT::Other;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
unsigned NumElts = VT.getVectorNumElements();
ValueTypeActions.setTypeAction(VT,
NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
} else {
TransformToType[i] = NVT;
Refactor the type legalizer. Switch TargetLowering to a new enum - LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). llvm-svn: 132263
2011-05-29 01:57:14 +08:00
ValueTypeActions.setTypeAction(VT, TypeWidenVector);
Generalize MVT::ValueType and associated functions to be able to represent extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
2007-06-26 00:23:39 +08:00
}
set TransformToType correctly for vector types. llvm-svn: 26797
2006-03-17 03:50:01 +08:00
}
Teach computeRegisterProperties() to compute "representative" register class for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. llvm-svn: 108735
2010-07-20 02:47:01 +08:00
// Determine the 'representative' register class for each value type.
// An representative register class is the largest (meaning one which is
// not a sub-register class / subreg register class) legal register class for
// a group of value types. For example, on i386, i8, i16, and i32
// representative would be GR32; while on x86_64 it's GR64.
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. llvm-svn: 108761
2010-07-20 06:15:08 +08:00
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Teach bottom up pre-ra scheduler to track register pressure. Work in progress. llvm-svn: 108991
2010-07-21 14:09:07 +08:00
const TargetRegisterClass* RRC;
uint8_t Cost;
tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
RepRegClassForVT[i] = RRC;
RepRegClassCostForVT[i] = Cost;
ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. llvm-svn: 108761
2010-07-20 06:15:08 +08:00
}
Move some information out of LegalizeDAG into the generic Target interface. llvm-svn: 19581
2005-01-16 09:10:58 +08:00
}
Use enums, move virtual dtor out of line. llvm-svn: 19610
2005-01-16 15:28:11 +08:00
Added a hook to print out names of target specific DAG nodes. llvm-svn: 24877
2005-12-20 14:22:03 +08:00
const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return NULL;
}
* Fix a GlobalAddress lowering bug. * Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook. llvm-svn: 24921
2005-12-22 07:05:39 +08:00
Add codegen support for vector select (in the IR this means a select with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
2011-09-07 03:07:46 +08:00
EVT TargetLowering::getSetCCResultType(EVT VT) const {
assert(!VT.isVector() && "No default SetCC type for vectors!");
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
2012-10-10 00:06:12 +08:00
return getPointerTy(0).SimpleTy;
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's return ValueType can depend its operands' ValueType. This is a cosmetic change, no functionality impacted. llvm-svn: 48145
2008-03-10 23:42:14 +08:00
}
Allow targets to specify the return type of libcalls that are generated for floating point comparisons, rather than hard-coding them as i32. llvm-svn: 92199
2009-12-28 10:40:33 +08:00
MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
return MVT::i32; // return the default value
}
Generalize MVT::ValueType and associated functions to be able to represent extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
2007-06-26 00:23:39 +08:00
/// getVectorTypeBreakdown - Vector types are broken down into some number of
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
///
Generalize MVT::ValueType and associated functions to be able to represent extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
2007-06-26 00:23:39 +08:00
/// This method returns the number of registers needed, and the VT for each
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
///
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT &IntermediateVT,
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
unsigned &NumIntermediates,
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
MVT &RegisterVT) const {
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
unsigned NumElts = VT.getVectorNumElements();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
// If there is a wider vector type with the same element type as this one,
Teach getVectorTypeBreakdown about promotion of vectors in addition to widening of vectors. llvm-svn: 155296
2012-04-22 04:08:32 +08:00
// or a promoted vector type that has the same number of elements which
// are wider, then we should convert to that legal vector type.
// This handles things like <2 x float> -> <4 x float> and
// <4 x i1> -> <4 x i32>.
LegalizeTypeAction TA = getTypeAction(Context, VT);
if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
EVT RegisterEVT = getTypeToTransformTo(Context, VT);
if (isTypeLegal(RegisterEVT)) {
IntermediateVT = RegisterEVT;
RegisterVT = RegisterEVT.getSimpleVT();
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
NumIntermediates = 1;
return 1;
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
// Figure out the right, legal destination reg to copy into.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT EltTy = VT.getVectorElementType();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
unsigned NumVectorRegs = 1;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Support returning non-power-of-2 vectors to unblock some work llvm-svn: 44371
2007-11-28 03:28:48 +08:00
// could break down into LHS/RHS like LegalizeDAG does.
if (!isPowerOf2_32(NumElts)) {
NumVectorRegs = NumElts;
NumElts = 1;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
while (NumElts > 1 && !isTypeLegal(
EVT::getVectorVT(Context, EltTy, NumElts))) {
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
NumElts >>= 1;
NumVectorRegs <<= 1;
}
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
NumIntermediates = NumVectorRegs;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Generalize MVT::ValueType and associated functions to be able to represent extended vector types. Remove the special SDNode opcodes used for pre-legalize vector operations, and the special MVT::Vector type used with them. Adjust lowering and legalize to work with the normal SDNode kinds instead, and to use the normal MVT functions to work with vector types instead of using the two special operands that the pre-legalize nodes held. This allows pre-legalize and post-legalize DAGs, and the code that operates on them, to be more consistent. Pre-legalize vector operators can be handled more consistently with scalar operators. And, -view-dag-combine1-dags and -view-legalize-dags now look prettier for vector code. llvm-svn: 37719
2007-06-26 00:23:39 +08:00
if (!isTypeLegal(NewVT))
NewVT = EltTy;
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
IntermediateVT = NewVT;
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
MVT DestVT = getRegisterType(Context, NewVT);
Add new TargetLowering code to provide the final register type that an illegal value type will be transformed to, for code that needs the register type after all transformations instead of just after the first transformation. Factor out the code that uses this information to do copy-from-regs and copy-to-regs for various purposes into separate functions so that they are done consistently. llvm-svn: 37781
2007-06-29 07:29:44 +08:00
RegisterVT = DestVT;
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
2011-06-12 22:56:55 +08:00
unsigned NewVTSize = NewVT.getSizeInBits();
// Convert sizes such as i33 to i64.
if (!isPowerOf2_32(NewVTSize))
NewVTSize = NextPowerOf2(NewVTSize);
Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT, from EVT. llvm-svn: 170536
2012-12-19 19:53:21 +08:00
if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
2011-06-12 22:56:55 +08:00
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Change handling of illegal vector types to widen when possible instead of expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 llvm-svn: 112101
2010-08-26 06:49:25 +08:00
// Otherwise, promotion or legal types use the same number of registers as
// the vector decimated to the appropriate level.
return NumVectorRegs;
Implement TargetLowering::getPackedTypeBreakdown llvm-svn: 27270
2006-03-31 08:28:56 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
/// Get the EVTs and ArgFlags collections that represent the legalized return
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
/// type of the given function. This does not require a DAG or a return value,
/// and is suitable for use before any DAGs for the function are constructed.
/// TODO: Move this out of TargetLowering.cpp.
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
SmallVectorImpl<ISD::OutputArg> &Outs,
Simplify code for calling a function where CanLowerReturn fails, fixing a small bug in the process. llvm-svn: 157446
2012-05-25 08:09:29 +08:00
const TargetLowering &TLI) {
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, ReturnType, ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) return;
for (unsigned j = 0, f = NumValues; j != f; ++j) {
EVT VT = ValueVTs[j];
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
ExtendKind = ISD::SIGN_EXTEND;
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
ExtendKind = ISD::ZERO_EXTEND;
// FIXME: C calling convention requires the return type to be promoted to
// at least 32-bit. But this is not necessary for non-C calling
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of EVTs. llvm-svn: 170535
2012-12-19 19:48:16 +08:00
MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
if (VT.bitsLT(MinVT))
VT = MinVT;
}
unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of EVTs. llvm-svn: 170535
2012-12-19 19:48:16 +08:00
MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
// 'inreg' on function refers to return value
ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
Flags.setInReg();
// Propagate extension type if any
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
Flags.setSExt();
Remove the Function::getRetAttributes method in favor of using the AttributeSet accessor method. llvm-svn: 171256
2012-12-30 21:01:51 +08:00
else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
Flags.setZExt();
Add predicates for queries on whether an attribute exists. llvm-svn: 164264
2012-09-20 07:35:21 +08:00
for (unsigned i = 0; i < NumParts; ++i)
OutputArg: added an index of the original argument to match the change to InputArg in r165616. This will enable us to get the actual type for both InputArg and OutputArg. rdar://9932559 llvm-svn: 167265
2012-11-02 07:49:58 +08:00
Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0));
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
2010-07-10 17:00:22 +08:00
}
}
Forgot these. llvm-svn: 46292
2008-01-24 08:22:01 +08:00
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Interface of getByValTypeAlignment differed between generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
2008-02-29 06:31:51 +08:00
/// function arguments in the caller parameter area. This is the actual
/// alignment, not its logarithm.
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
Interface of getByValTypeAlignment differed between generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734
2008-02-29 06:31:51 +08:00
return TD->getCallFrameTypeAlignment(Ty);
Forgot these. llvm-svn: 46292
2008-01-24 08:22:01 +08:00
}
Rearrange handling of jump tables. Highlights: 1. MachineJumpTableInfo is now created lazily for a function the first time it actually makes a jump table instead of for every function. 2. The encoding of jump table entries is now described by the MachineJumpTableInfo::JTEntryKind enum. This enum is determined by the TLI::getJumpTableEncoding() hook, instead of by lots of code scattered throughout the compiler that "knows" that jump table entries are always 32-bits in pic mode (for example). 3. The size and alignment of jump table entries is now calculated based on their kind, instead of at machinefunction creation time. Future work includes using the EntryKind in more places in the compiler, eliminating other logic that "knows" the layout of jump tables in various situations. llvm-svn: 94470
2010-01-26 07:26:13 +08:00
/// getJumpTableEncoding - Return the entry encoding for a jump table in the
/// current function. The returned value is a member of the
/// MachineJumpTableInfo::JTEntryKind enum.
unsigned TargetLowering::getJumpTableEncoding() const {
// In non-pic modes, just use the address of a block.
if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
return MachineJumpTableInfo::EK_BlockAddress;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rearrange handling of jump tables. Highlights: 1. MachineJumpTableInfo is now created lazily for a function the first time it actually makes a jump table instead of for every function. 2. The encoding of jump table entries is now described by the MachineJumpTableInfo::JTEntryKind enum. This enum is determined by the TLI::getJumpTableEncoding() hook, instead of by lots of code scattered throughout the compiler that "knows" that jump table entries are always 32-bits in pic mode (for example). 3. The size and alignment of jump table entries is now calculated based on their kind, instead of at machinefunction creation time. Future work includes using the EntryKind in more places in the compiler, eliminating other logic that "knows" the layout of jump tables in various situations. llvm-svn: 94470
2010-01-26 07:26:13 +08:00
// In PIC mode, if the target supports a GPRel32 directive, use it.
if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rearrange handling of jump tables. Highlights: 1. MachineJumpTableInfo is now created lazily for a function the first time it actually makes a jump table instead of for every function. 2. The encoding of jump table entries is now described by the MachineJumpTableInfo::JTEntryKind enum. This enum is determined by the TLI::getJumpTableEncoding() hook, instead of by lots of code scattered throughout the compiler that "knows" that jump table entries are always 32-bits in pic mode (for example). 3. The size and alignment of jump table entries is now calculated based on their kind, instead of at machinefunction creation time. Future work includes using the EntryKind in more places in the compiler, eliminating other logic that "knows" the layout of jump tables in various situations. llvm-svn: 94470
2010-01-26 07:26:13 +08:00
// Otherwise, use a label difference.
return MachineJumpTableInfo::EK_LabelDifference32;
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
SelectionDAG &DAG) const {
eliminate the TargetLowering::UsesGlobalOffsetTable bool, which is subsumed by TargetLowering::getJumpTableEncoding(). Change uses of it to be more specific. llvm-svn: 94529
2010-01-26 14:53:37 +08:00
// If our PIC model is GP relative, use the global offset table as the base.
Have TargetLowering::getPICJumpTableRelocBase return a node that points to the GOT if jump table uses 64-bit gp-relative relocation. llvm-svn: 154341
2012-04-10 04:32:12 +08:00
unsigned JTEncoding = getJumpTableEncoding();
if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
(JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
2012-10-10 00:06:12 +08:00
return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
Have TargetLowering::getPICJumpTableRelocBase return a node that points to the GOT if jump table uses 64-bit gp-relative relocation. llvm-svn: 154341
2012-04-10 04:32:12 +08:00
Much improved pic jumptable codegen: Then: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry imull $4, %ecx, %ecx leal LJTI1_0-"L1$pb"(%eax), %edx addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx jmpl *%edx .align 2 .set L1_0_set_3,LBB1_3-LJTI1_0 .set L1_0_set_2,LBB1_2-LJTI1_0 .set L1_0_set_5,LBB1_5-LJTI1_0 .set L1_0_set_4,LBB1_4-LJTI1_0 LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 Now: call "L1$pb" "L1$pb": popl %eax ... LBB1_1: # entry addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax jmpl *%eax .align 2 .set L1_0_set_3,LBB1_3-"L1$pb" .set L1_0_set_2,LBB1_2-"L1$pb" .set L1_0_set_5,LBB1_5-"L1$pb" .set L1_0_set_4,LBB1_4-"L1$pb" LJTI1_0: .long L1_0_set_3 .long L1_0_set_2 llvm-svn: 43924
2007-11-09 09:32:10 +08:00
return Table;
}
stub out a new target hook, need some refactoring before I can implement it. llvm-svn: 94521
2010-01-26 13:30:30 +08:00
/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
/// MCExpr.
const MCExpr *
Move getJTISymbol from MachineJumpTableInfo to MachineFunction, which is more convenient, and change getPICJumpTableRelocBaseExpr to take a MachineFunction to match. Next, move the X86 code that create a PICBase symbol to X86TargetLowering::getPICBaseSymbol from X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific library. This eliminates a 'gross hack', and allows us to implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now calls it. This in turn allows us to eliminate the X86AsmPrinter::printPICJumpTableSetLabel method, which was the only overload of printPICJumpTableSetLabel. llvm-svn: 94526
2010-01-26 14:28:43 +08:00
TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
unsigned JTI,MCContext &Ctx) const{
add a new MachineJumpTableInfo::getJTISymbol method, use it to implement the default TargetLowering::getPICJumpTableRelocBaseExpr llvm-svn: 94523
2010-01-26 13:58:28 +08:00
// The normal PIC reloc base is the label at the start of the jump table.
Move getJTISymbol from MachineJumpTableInfo to MachineFunction, which is more convenient, and change getPICJumpTableRelocBaseExpr to take a MachineFunction to match. Next, move the X86 code that create a PICBase symbol to X86TargetLowering::getPICBaseSymbol from X86MCInstLower::GetPICBaseSymbol, which was an asmprinter specific library. This eliminates a 'gross hack', and allows us to implement X86ISelLowering::getPICJumpTableRelocBaseExpr which now calls it. This in turn allows us to eliminate the X86AsmPrinter::printPICJumpTableSetLabel method, which was the only overload of printPICJumpTableSetLabel. llvm-svn: 94526
2010-01-26 14:28:43 +08:00
return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
stub out a new target hook, need some refactoring before I can implement it. llvm-svn: 94521
2010-01-26 13:30:30 +08:00
}
Teach DAGCombine to fold constant offsets into GlobalAddress nodes, and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
2008-10-18 10:06:02 +08:00
bool
TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// Assume that everything is safe in static mode.
if (getTargetMachine().getRelocationModel() == Reloc::Static)
return true;
// In dynamic-no-pic mode, assume that known defined values are safe.
if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
GA &&
!GA->getGlobal()->isDeclaration() &&
Introduce new linkage types linkonce_odr, weak_odr, common_odr and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an *equivalent* global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. llvm-svn: 66339
2009-03-07 23:45:40 +08:00
!GA->getGlobal()->isWeakForLinker())
Teach DAGCombine to fold constant offsets into GlobalAddress nodes, and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
2008-10-18 10:06:02 +08:00
return true;
// Otherwise assume nothing is safe.
return false;
}
Switch TargetTransformInfo from an immutable analysis pass that requires a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
2013-01-07 09:37:14 +08:00
//===----------------------------------------------------------------------===//
// TargetTransformInfo Helpers
//===----------------------------------------------------------------------===//
int TargetLowering::InstructionOpcodeToISD(unsigned Opcode) const {
enum InstructionOpcodes {
#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
#include "llvm/IR/Instruction.def"
};
switch (static_cast<InstructionOpcodes>(Opcode)) {
case Ret: return 0;
case Br: return 0;
case Switch: return 0;
case IndirectBr: return 0;
case Invoke: return 0;
case Resume: return 0;
case Unreachable: return 0;
case Add: return ISD::ADD;
case FAdd: return ISD::FADD;
case Sub: return ISD::SUB;
case FSub: return ISD::FSUB;
case Mul: return ISD::MUL;
case FMul: return ISD::FMUL;
case UDiv: return ISD::UDIV;
case SDiv: return ISD::UDIV;
case FDiv: return ISD::FDIV;
case URem: return ISD::UREM;
case SRem: return ISD::SREM;
case FRem: return ISD::FREM;
case Shl: return ISD::SHL;
case LShr: return ISD::SRL;
case AShr: return ISD::SRA;
case And: return ISD::AND;
case Or: return ISD::OR;
case Xor: return ISD::XOR;
case Alloca: return 0;
case Load: return ISD::LOAD;
case Store: return ISD::STORE;
case GetElementPtr: return 0;
case Fence: return 0;
case AtomicCmpXchg: return 0;
case AtomicRMW: return 0;
case Trunc: return ISD::TRUNCATE;
case ZExt: return ISD::ZERO_EXTEND;
case SExt: return ISD::SIGN_EXTEND;
case FPToUI: return ISD::FP_TO_UINT;
case FPToSI: return ISD::FP_TO_SINT;
case UIToFP: return ISD::UINT_TO_FP;
case SIToFP: return ISD::SINT_TO_FP;
case FPTrunc: return ISD::FP_ROUND;
case FPExt: return ISD::FP_EXTEND;
case PtrToInt: return ISD::BITCAST;
case IntToPtr: return ISD::BITCAST;
case BitCast: return ISD::BITCAST;
case ICmp: return ISD::SETCC;
case FCmp: return ISD::SETCC;
case PHI: return 0;
case Call: return 0;
case Select: return ISD::SELECT;
case UserOp1: return 0;
case UserOp2: return 0;
case VAArg: return 0;
case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
case InsertElement: return ISD::INSERT_VECTOR_ELT;
case ShuffleVector: return ISD::VECTOR_SHUFFLE;
case ExtractValue: return ISD::MERGE_VALUES;
case InsertValue: return ISD::MERGE_VALUES;
case LandingPad: return 0;
}
llvm_unreachable("Unknown instruction type encountered!");
}
std::pair<unsigned, MVT>
TargetLowering::getTypeLegalizationCost(Type *Ty) const {
LLVMContext &C = Ty->getContext();
EVT MTy = getValueType(Ty);
unsigned Cost = 1;
// We keep legalizing the type until we find a legal kind. We assume that
// the only operation that costs anything is the split. After splitting
// we need to handle two types.
while (true) {
LegalizeKind LK = getTypeConversion(C, MTy);
if (LK.first == TypeLegal)
return std::make_pair(Cost, MTy.getSimpleVT());
if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
Cost *= 2;
// Keep legalizing the type.
MTy = LK.second;
}
}
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
//===----------------------------------------------------------------------===//
// Optimization Methods
//===----------------------------------------------------------------------===//
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
/// ShrinkDemandedConstant - Check to see if the specified operand of the
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
/// specified instruction is a constant integer. If so, check to see if there
/// are any bits set in the constant that are not demanded. If so, shrink the
/// constant and return true.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
const APInt &Demanded) {
Remove more non-DebugLoc versions of getNode. llvm-svn: 63969
2009-02-07 05:50:26 +08:00
DebugLoc dl = Op.getDebugLoc();
The DAG combiner was performing a BT combine. The BT combine had a value of -1, so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it would go through the DAG combiner again. This time it had a value of 31, which was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong forever. Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded value is an XOR of all ones. llvm-svn: 65985
2009-03-04 08:18:06 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// FIXME: ISD::SELECT, ISD::SELECT_CC
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
switch (Op.getOpcode()) {
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
default: break;
case ISD::XOR:
The DAG combiner was performing a BT combine. The BT combine had a value of -1, so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it would go through the DAG combiner again. This time it had a value of 31, which was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong forever. Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded value is an XOR of all ones. llvm-svn: 65985
2009-03-04 08:18:06 +08:00
case ISD::AND:
case ISD::OR: {
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
if (!C) return false;
if (Op.getOpcode() == ISD::XOR &&
(C->getAPIntValue() | (~Demanded)).isAllOnesValue())
return false;
// if we can expand it to have all bits set, do it
if (C->getAPIntValue().intersects(~Demanded)) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
The DAG combiner was performing a BT combine. The BT combine had a value of -1, so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it would go through the DAG combiner again. This time it had a value of 31, which was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong forever. Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded value is an XOR of all ones. llvm-svn: 65985
2009-03-04 08:18:06 +08:00
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded &
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
C->getAPIntValue(),
The DAG combiner was performing a BT combine. The BT combine had a value of -1, so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it would go through the DAG combiner again. This time it had a value of 31, which was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong forever. Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded value is an XOR of all ones. llvm-svn: 65985
2009-03-04 08:18:06 +08:00
VT));
return CombineTo(Op, New);
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
break;
}
The DAG combiner was performing a BT combine. The BT combine had a value of -1, so it changed it into a 31 via the TLO.ShrinkDemandedConstant() call. Then it would go through the DAG combiner again. This time it had a value of 31, which was turned into a -1 by TLI.SimplifyDemandedBits(). This would ping pong forever. Teach the TLO.ShrinkDemandedConstant() call not to lower a value if the demanded value is an XOR of all ones. llvm-svn: 65985
2009-03-04 08:18:06 +08:00
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return false;
}
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
/// cast, but it could be generalized for targets with other types of
/// implicit widening casts.
bool
TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
unsigned BitWidth,
const APInt &Demanded,
DebugLoc dl) {
assert(Op.getNumOperands() == 2 &&
"ShrinkDemandedOp only supports binary operators!");
assert(Op.getNode()->getNumValues() == 1 &&
"ShrinkDemandedOp only supports nodes with one result!");
// Don't do this if the node has another user, which may require the
// full value.
if (!Op.getNode()->hasOneUse())
return false;
// Search for the smallest integer type with free casts to and from
// Op's type. For expedience, just check power-of-2 integer types.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
After reducing the size of an operation in the DAG we zero-extend the reduced bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
2012-12-19 15:39:08 +08:00
unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
unsigned SmallVTBits = DemandedSize;
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
if (!isPowerOf2_32(SmallVTBits))
SmallVTBits = NextPowerOf2(SmallVTBits);
for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Add contexts to some of the MVT APIs. No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first. llvm-svn: 78759
2009-08-12 08:36:31 +08:00
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
TLI.isZExtFree(SmallVT, Op.getValueType())) {
// We found a type with free casts.
SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
Op.getNode()->getOperand(0)),
DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
Op.getNode()->getOperand(1)));
After reducing the size of an operation in the DAG we zero-extend the reduced bitwidth op back to the original size. If we reduce ANDs then this can cause an endless loop. This patch changes the ZEXT to ANY_EXTEND if the demanded bits are equal or smaller than the size of the reduced operation. llvm-svn: 170505
2012-12-19 15:39:08 +08:00
bool NeedZext = DemandedSize > SmallVTBits;
SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
dl, Op.getValueType(), X);
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
return CombineTo(Op, Z);
}
}
return false;
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
Revert r132871. llvm-svn: 132872
2011-06-11 10:27:46 +08:00
/// DemandedMask bits of the result of Op are ever used downstream. If we can
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
/// use this information to simplify Op, create a new simplified DAG node and
/// return true, returning the original and new nodes in Old and New. Otherwise,
/// analyze the expression and return a mask of KnownOne and KnownZero bits for
/// the expression (used to simplify the caller). The KnownZero/One bits may
/// only be accurate for those bits in the DemandedMask.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
const APInt &DemandedMask,
APInt &KnownZero,
APInt &KnownOne,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
TargetLoweringOpt &TLO,
unsigned Depth) const {
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
unsigned BitWidth = DemandedMask.getBitWidth();
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. llvm-svn: 91158
2009-12-12 05:31:27 +08:00
assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
"Mask size mismatches value type size!");
APInt NewMask = DemandedMask;
Use getDebugLoc forwarder instead of getNode()->getDebugLoc. No functional change. llvm-svn: 64026
2009-02-08 03:59:05 +08:00
DebugLoc dl = Op.getDebugLoc();
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// Don't know anything.
KnownZero = KnownOne = APInt(BitWidth, 0);
disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for i128 integers. The 64-bit masks are not wide enough to represent the results. These should be converted to APInt someday. llvm-svn: 37169
2007-05-18 02:19:23 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Other users may use these bits.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (!Op.getNode()->hasOneUse()) {
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
if (Depth != 0) {
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// If not at the root, Just compute the KnownZero/KnownOne bits to
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// simplify things downstream.
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return false;
}
// If this is the root being simplified, allow it to have multiple uses,
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// just set the NewMask to all bits.
NewMask = APInt::getAllOnesValue(BitWidth);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
} else if (DemandedMask == 0) {
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Not demanding any bits from Op.
if (Op.getOpcode() != ISD::UNDEF)
Remove more non-DebugLoc getNode variants. Use getCALLSEQ_{END,START} to permit passing no DebugLoc there. UNDEF doesn't logically have DebugLoc; add getUNDEF to encapsulate this. llvm-svn: 63978
2009-02-07 07:05:02 +08:00
return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
return false;
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
} else if (Depth == 6) { // Limit search depth.
return false;
}
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
switch (Op.getOpcode()) {
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
case ISD::Constant:
// We know all of the bits for a constant!
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
KnownZero = ~KnownOne;
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
return false; // Don't fall through, will infinitely loop.
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
case ISD::AND:
Check RHS simplification before LHS simplification to avoid infinitely looping on PowerPC/small-arguments.ll llvm-svn: 26389
2006-02-27 08:36:27 +08:00
// If the RHS is a constant, check to see if the LHS would be zero without
// using the bits from the RHS. Below, we use knowledge about the RHS to
// simplify the LHS, here we're using information from the LHS to simplify
// the RHS.
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt LHSZero, LHSOne;
Fix PR 8916 (qv for analysis), at least the immediate problem. There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. llvm-svn: 123191
2011-01-11 05:53:07 +08:00
// Do not increment Depth here; that can cause an infinite loop.
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
Check RHS simplification before LHS simplification to avoid infinitely looping on PowerPC/small-arguments.ll llvm-svn: 26389
2006-02-27 08:36:27 +08:00
// If the LHS already has zeros where RHSC does, this and is dead.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Check RHS simplification before LHS simplification to avoid infinitely looping on PowerPC/small-arguments.ll llvm-svn: 26389
2006-02-27 08:36:27 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
// If any of the set bits in the RHS are known zero on the LHS, shrink
// the constant.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Check RHS simplification before LHS simplification to avoid infinitely looping on PowerPC/small-arguments.ll llvm-svn: 26389
2006-02-27 08:36:27 +08:00
return true;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero2, KnownOne2, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If all of the demanded bits are known one on one side, return the other.
// These bits cannot contribute to the result of the 'and'.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(1));
// If all of the demanded bits in the inputs are known zeros, return zero.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
// If the RHS is a constant, see if we can simplify it.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return true;
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
// If the operation can be done in a smaller type, do so.
Reapply r106634, now that the bug it exposed is fixed. llvm-svn: 106746
2010-06-24 22:30:44 +08:00
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
return true;
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Output known-1 bits are only known if set in both the LHS & RHS.
KnownOne &= KnownOne2;
// Output known-0 are known to be clear if zero in either the LHS | RHS.
KnownZero |= KnownZero2;
break;
case ISD::OR:
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero2, KnownOne2, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'or'.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(1));
// If all of the potentially set bits on one side are known to be set on
// the other side, just use the 'other' side.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(1));
// If the RHS is a constant, see if we can simplify it.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (TLO.ShrinkDemandedConstant(Op, NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return true;
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
// If the operation can be done in a smaller type, do so.
Reapply r106634, now that the bug it exposed is fixed. llvm-svn: 106746
2010-06-24 22:30:44 +08:00
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
return true;
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Output known-0 bits are only known if clear in both the LHS & RHS.
KnownZero &= KnownZero2;
// Output known-1 are known to be set if set in either the LHS | RHS.
KnownOne |= KnownOne2;
break;
case ISD::XOR:
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne2, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If all of the demanded bits are known zero on one side, return the other.
// These bits cannot contribute to the result of the 'xor'.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((KnownZero & NewMask) == NewMask)
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((KnownZero2 & NewMask) == NewMask)
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return TLO.CombineTo(Op, Op.getOperand(1));
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
// If the operation can be done in a smaller type, do so.
Reapply r106634, now that the bug it exposed is fixed. llvm-svn: 106746
2010-06-24 22:30:44 +08:00
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
return true;
Fix the dag combiner bug corresponding to PR1014. llvm-svn: 31943
2006-11-28 05:50:02 +08:00
// If all of the unknown bits are known to be zero on one side or the other
// (but not both) turn this into an *inclusive* or.
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
2012-09-27 18:14:43 +08:00
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Remove more non-DebugLoc versions of getNode. llvm-svn: 63969
2009-02-07 05:50:26 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Fix the dag combiner bug corresponding to PR1014. llvm-svn: 31943
2006-11-28 05:50:02 +08:00
Op.getOperand(0),
Op.getOperand(1)));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Output known-0 bits are known if clear or set in both the LHS & RHS.
KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
// Output known-1 are known to be set if set in only one of the LHS, RHS.
KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If all of the demanded bits on one side are known, and all of the set
// bits on that side are also known to be set on the other side, turn this
// into an AND, as we know the bits will be cleared.
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
2012-09-27 18:14:43 +08:00
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Fixes a problem in instruction selection with testing whether or not the transformation: (X op C1) ^ C2 --> (X op C1) & ~C2 iff (C1&C2) == C2 should be done. This change has been tested: Using a debug+asserts build: on the specific test case that brought this bug to light make check-all lnt nt using this clang to build a release version of clang Using the release+asserts clang-with-clang build: on the specific test case that brought this bug to light make check-all lnt nt Checking in because Evan wants it checked in. Test case forthcoming after scrubbing. llvm-svn: 154955
2012-04-18 06:23:10 +08:00
// NB: it is okay if more bits are known than are requested
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
if (KnownOne == KnownOne2) { // set bits are the same on both sides
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Op.getOperand(0), ANDC));
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
}
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If the RHS is a constant, see if we can simplify it.
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
// for XOR, we prefer to force bits to 1 if they will make a -1.
// if we can't force bits, try to shrink constant
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
APInt Expanded = C->getAPIntValue() | (~NewMask);
// if we can expand it to have all bits set, do it
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Prefer to expand mask for xor to -1, so we have a chance to turn it into a not. If it cannot be expanded, it will keep the old behaviour and try to shrink the constant. Part of enhancement for PR2191. llvm-svn: 49280
2008-04-07 05:23:02 +08:00
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
}
// if it already has all the bits set, nothing to change
// but don't shrink either!
} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
return true;
}
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero = KnownZeroOut;
KnownOne = KnownOneOut;
break;
case ISD::SELECT:
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne, TLO, Depth+1))
return true;
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne2, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If the operands are constants, see if we can simplify them.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (TLO.ShrinkDemandedConstant(Op, NewMask))
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// Only known if known in both the LHS and RHS.
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
break;
case ISD::SELECT_CC:
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownOne, TLO, Depth+1))
return true;
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownOne2, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If the operands are constants, see if we can simplify them.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (TLO.ShrinkDemandedConstant(Op, NewMask))
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Only known if known in both the LHS and RHS.
KnownOne &= KnownOne2;
KnownZero &= KnownZero2;
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
break;
case ISD::SHL:
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
unsigned ShAmt = SA->getZExtValue();
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue InOp = Op.getOperand(0);
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
break;
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
// single shift. We can do this if the bottom bits (which are shifted
// out) are never demanded.
if (InOp.getOpcode() == ISD::SRL &&
isa<ConstantSDNode>(InOp.getOperand(1))) {
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
unsigned Opc = ISD::SHL;
int Diff = ShAmt-C1;
if (Diff < 0) {
Diff = -Diff;
Opc = ISD::SRL;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
SDValue NewSA =
Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473. llvm-svn: 37362
2007-05-31 00:30:06 +08:00
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
InOp.getOperand(0), NewSA));
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
2010-07-24 02:03:30 +08:00
if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
2010-07-24 02:03:30 +08:00
// Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
// are not demanded. This will likely allow the anyext to be folded away.
if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
SDValue InnerOp = InOp.getNode()->getOperand(0);
EVT InnerVT = InnerOp.getValueType();
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514. llvm-svn: 146219
2011-12-09 09:16:26 +08:00
unsigned InnerBits = InnerVT.getSizeInBits();
if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
2010-07-24 02:03:30 +08:00
isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
EVT ShTy = getShiftAmountTy(InnerVT);
Use the proper type for shift counts. This fixes a bootstrap error. llvm-svn: 109265
2010-07-24 05:08:12 +08:00
if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
ShTy = InnerVT;
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
2010-07-24 02:03:30 +08:00
SDValue NarrowShl =
TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Use the proper type for shift counts. This fixes a bootstrap error. llvm-svn: 109265
2010-07-24 05:08:12 +08:00
TLO.DAG.getConstant(ShAmt, ShTy));
DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits are not demanded. This often allows the anyext to be folded away. llvm-svn: 109242
2010-07-24 02:03:30 +08:00
return
TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
NarrowShl));
}
}
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
KnownZero <<= SA->getZExtValue();
KnownOne <<= SA->getZExtValue();
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// low bits known zero.
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
}
break;
case ISD::SRL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
unsigned ShAmt = SA->getZExtValue();
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
unsigned VTSize = VT.getSizeInBits();
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue InOp = Op.getOperand(0);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
break;
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
// single shift. We can do this if the top bits (which are shifted out)
// are never demanded.
if (InOp.getOpcode() == ISD::SHL &&
isa<ConstantSDNode>(InOp.getOperand(1))) {
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
unsigned Opc = ISD::SRL;
int Diff = ShAmt-C1;
if (Diff < 0) {
Diff = -Diff;
Opc = ISD::SHL;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue NewSA =
Fix a bug in my previous patch, grabbing the shift amount width from the wrong operand. llvm-svn: 36223
2007-04-18 06:53:02 +08:00
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. This compiles: int baz(long long a) { return (short)(((int)(a >>24)) >> 9); } into: _baz: srwi r2, r3, 1 extsh r3, r2 blr on PPC, instead of: _baz: slwi r2, r3, 8 srwi r2, r2, 9 extsh r3, r2 blr GCC produces: _baz: srwi r10,r4,24 insrwi r10,r3,24,0 srawi r9,r3,24 srawi r3,r10,9 extsh r3,r3 blr This implements CodeGen/PowerPC/shl_elim.ll llvm-svn: 36221
2007-04-18 05:14:16 +08:00
InOp.getOperand(0), NewSA));
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// Compute the new bits that are at the top now.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt);
Port some bugfixes in shift handling from SimplifyDemandedBits over to ComputeMaskedBits. DemandedMasks and KnownZero/One masks should never have bits set out of the range of the base datatype. llvm-svn: 28768
2006-06-14 00:52:37 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Port some bugfixes in shift handling from SimplifyDemandedBits over to ComputeMaskedBits. DemandedMasks and KnownZero/One masks should never have bits set out of the range of the base datatype. llvm-svn: 28768
2006-06-14 00:52:37 +08:00
KnownZero |= HighBits; // High bits known zero.
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
}
break;
case ISD::SRA:
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
// If this is an arithmetic shift right and only the low-bit is set, we can
// always convert this into a logical shr, even if the shift amount is
// variable. The low bit of the shift cannot be an input sign bit unless
// the shift amount is >= the size of the datatype, which is undefined.
Fix a couple of logic bugs in TargetLowering::SimplifyDemandedBits. PR11514. llvm-svn: 146219
2011-12-09 09:16:26 +08:00
if (NewMask == 1)
More work to allow dag combiner to promote 16-bit ops to 32-bit. llvm-svn: 101621
2010-04-17 14:13:15 +08:00
return TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
Op.getOperand(0), Op.getOperand(1)));
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = Op.getValueType();
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
unsigned ShAmt = SA->getZExtValue();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// If the shift count is an invalid immediate, don't do anything.
if (ShAmt >= BitWidth)
break;
APInt InDemandedMask = (NewMask << ShAmt);
When tracking demanded bits, if any bits from the sext of an SRA are demanded, then so is the input sign bit. This fixes mediabench/g721 on X86. llvm-svn: 28166
2006-05-09 01:22:53 +08:00
// If any of the demanded bits are produced by the sign extension, we also
// demand the input sign bit.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
if (HighBits.intersects(NewMask))
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. llvm-svn: 91158
2009-12-12 05:31:27 +08:00
InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
When tracking demanded bits, if any bits from the sext of an SRA are demanded, then so is the input sign bit. This fixes mediabench/g721 on X86. llvm-svn: 28166
2006-05-09 01:22:53 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
// Handle the sign bit, adjusted to where it is now in the mask.
APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Op.getOperand(0),
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
Op.getOperand(1)));
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne |= HighBits;
}
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
}
break;
case ISD::SIGN_EXTEND_INREG: {
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
// If we only care about the highest bit, don't bother shifting right.
Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. Not committing a testcase because I think it will be too fragile. llvm-svn: 149315
2012-01-31 09:08:03 +08:00
if (MsbMask == DemandedMask) {
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
SDValue InOp = Op.getOperand(0);
Use the correct ShiftAmtTy for creating shifts after legalization. PR11881. Not committing a testcase because I think it will be too fragile. llvm-svn: 149315
2012-01-31 09:08:03 +08:00
// Compute the correct shift amount type, which must be getShiftAmountTy
// for scalar types after legalization.
EVT ShiftAmtTy = Op.getValueType();
if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
Op.getValueType(), InOp, ShiftAmt));
}
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Sign extension. Compute the demanded bits in the result that are not
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// present in the input.
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
APInt NewBits =
APInt::getHighBitsSet(BitWidth,
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
BitWidth - ExVT.getScalarType().getSizeInBits());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If none of the extended bits are demanded, eliminate the sextinreg.
PR7586: Make sure we don't claim that unknown bits are actually known in the ISD::AND case of TargetLowering::SimplifyDemandedBits. llvm-svn: 110019
2010-08-02 12:42:25 +08:00
if ((NewBits & NewMask) == 0)
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
return TLO.CombineTo(Op, Op.getOperand(0));
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
APInt InSignBit =
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
APInt InputDemandedBits =
APInt::getLowBitsSet(BitWidth,
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
ExVT.getScalarType().getSizeInBits()) &
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
NewMask;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// Since the sign extended bits are demanded, we know that the sign
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// bit is demanded.
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
InputDemandedBits |= InSignBit;
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
KnownZero, KnownOne, TLO, Depth+1))
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
// If the sign bit of the input is known set or clear, then we know the
// top bits of the result.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If the input sign bit is known zero, convert this into a zero extension.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (KnownZero.intersects(InSignBit))
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return TLO.CombineTo(Op,
[AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits. We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
2012-01-16 03:27:55 +08:00
TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownOne |= NewBits;
KnownZero &= ~NewBits;
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
} else { // Input sign bit unknown
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
KnownZero &= ~NewBits;
KnownOne &= ~NewBits;
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
}
break;
}
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
case ISD::ZERO_EXTEND: {
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
unsigned OperandBitWidth =
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
APInt InMask = NewMask.trunc(OperandBitWidth);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If none of the top bits are demanded, convert this into an any_extend.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt NewBits =
APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
if (!NewBits.intersects(NewMask))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Op.getValueType(),
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
Op.getOperand(0)));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth);
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownZero |= NewBits;
break;
}
case ISD::SIGN_EXTEND: {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT InVT = Op.getOperand(0).getValueType();
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
unsigned InBits = InVT.getScalarType().getSizeInBits();
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Use the correct value for InSignBit. llvm-svn: 48245
2008-03-12 05:29:43 +08:00
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt NewBits = ~InMask & NewMask;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If none of the top bits are demanded, convert this into an any_extend.
if (NewBits == 0)
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Op.getValueType(),
Op.getOperand(0)));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// Since some of the sign extended bits are demanded, we know that the sign
// bit is demanded.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
APInt InDemandedBits = InMask & NewMask;
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
InDemandedBits |= InSignBit;
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
InDemandedBits = InDemandedBits.trunc(InBits);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownOne, TLO, Depth+1))
return true;
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If the sign bit is known zero, convert this to a zero extend.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (KnownZero.intersects(InSignBit))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Op.getValueType(),
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
Op.getOperand(0)));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If the sign bit is known one, the top bits match.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (KnownOne.intersects(InSignBit)) {
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
KnownOne |= NewBits;
assert((KnownZero & NewBits) == 0);
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
} else { // Otherwise, top bits aren't known.
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
assert((KnownOne & NewBits) == 0);
assert((KnownZero & NewBits) == 0);
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
}
break;
}
case ISD::ANY_EXTEND: {
Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode really does need to be a vector type, because TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type, and it needs to be able to distinguish between vectors and scalars. Also, fix some more issues with legalization of vector casts. llvm-svn: 93043
2010-01-09 10:13:55 +08:00
unsigned OperandBitWidth =
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
APInt InMask = NewMask.trunc(OperandBitWidth);
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth);
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
break;
}
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE llvm-svn: 28135
2006-05-06 06:32:12 +08:00
case ISD::TRUNCATE: {
Fold (trunc (srl x, c)) -> (srl (trunc x), c) llvm-svn: 28138
2006-05-06 08:11:52 +08:00
// Simplify the input, using demanded bit information, and compute the known
// zero/one bits live out.
Fix optimization of ISD::TRUNCATE on vector operands. Based on a patch by Micah Villmow for PR6335. llvm-svn: 97461
2010-03-02 01:59:21 +08:00
unsigned OperandBitWidth =
Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
APInt TruncMask = NewMask.zext(OperandBitWidth);
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE llvm-svn: 28135
2006-05-06 06:32:12 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
KnownZero = KnownZero.trunc(BitWidth);
KnownOne = KnownOne.trunc(BitWidth);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Fold (trunc (srl x, c)) -> (srl (trunc x), c) llvm-svn: 28138
2006-05-06 08:11:52 +08:00
// If the input is only used by this truncate, see if we can shrink it based
// on the known demanded bits.
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (Op.getOperand(0).getNode()->hasOneUse()) {
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue In = Op.getOperand(0);
Fold (trunc (srl x, c)) -> (srl (trunc x), c) llvm-svn: 28138
2006-05-06 08:11:52 +08:00
switch (In.getOpcode()) {
default: break;
case ISD::SRL:
// Shrink SRL by a constant if none of the high bits shifted in are
// demanded.
More work to allow dag combiner to promote 16-bit ops to 32-bit. llvm-svn: 101621
2010-04-17 14:13:15 +08:00
if (TLO.LegalTypes() &&
!isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
// Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
// undesirable.
break;
ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
if (!ShAmt)
break;
During post-legalization DAG combining, be careful to only create shifts where the RHS is of the legal type for the new operation. llvm-svn: 129484
2011-04-14 07:22:23 +08:00
SDValue Shift = In.getOperand(1);
if (TLO.LegalTypes()) {
uint64_t ShVal = ShAmt->getZExtValue();
Shift =
TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
}
More work to allow dag combiner to promote 16-bit ops to 32-bit. llvm-svn: 101621
2010-04-17 14:13:15 +08:00
APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
OperandBitWidth - BitWidth);
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
More work to allow dag combiner to promote 16-bit ops to 32-bit. llvm-svn: 101621
2010-04-17 14:13:15 +08:00
if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
// None of the shifted in bits are needed. Add a truncate of the
// shift input, then shift it.
SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Op.getValueType(),
More work to allow dag combiner to promote 16-bit ops to 32-bit. llvm-svn: 101621
2010-04-17 14:13:15 +08:00
In.getOperand(0));
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
Op.getValueType(),
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
NewTrunc,
During post-legalization DAG combining, be careful to only create shifts where the RHS is of the legal type for the new operation. llvm-svn: 129484
2011-04-14 07:22:23 +08:00
Shift));
Fold (trunc (srl x, c)) -> (srl (trunc x), c) llvm-svn: 28138
2006-05-06 08:11:52 +08:00
}
break;
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE llvm-svn: 28135
2006-05-06 06:32:12 +08:00
break;
}
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
case ISD::AssertZext: {
Fix a truly heinous bug in DAGCombine related to AssertZext. If we have a chain of zext -> assert_zext -> zext -> use, the first zext would get simplified away because of the later zext, and then the later zext would get simplified away because of the assert. The solution is to teach SimplifyDemandedBits that assert_zext demands all of the high bits of its input, rather than only those demanded by its users. No testcase because the only example I have manifests as llvm-gcc miscompiling LLVM, and I haven't found a smaller case that reproduces this problem. Fixes <rdar://problem/10063365>. llvm-svn: 139059
2011-09-03 08:26:49 +08:00
// AssertZext demands all of the high bits, plus any of the low bits
// demanded by its users.
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
KnownZero, KnownOne, TLO, Depth+1))
return true;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It needs to demand the high bits because it's asserting that they're zero. llvm-svn: 105406
2010-06-04 04:21:33 +08:00
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
KnownZero |= ~InMask & NewMask;
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
break;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
case ISD::BITCAST:
Avoid FGETSIGN of 80-bit types. Fixes PR10085. llvm-svn: 132681
2011-06-07 00:44:31 +08:00
// If this is an FP->Int bitcast and if the sign bit is the only
// thing demanded, turn this into a FGETSIGN.
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570. llvm-svn: 146630
2011-12-15 10:07:20 +08:00
if (!TLO.LegalOperations() &&
!Op.getValueType().isVector() &&
Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. llvm-svn: 144216
2011-11-10 06:25:12 +08:00
!Op.getOperand(0).getValueType().isVector() &&
Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd types such as i33 were rounded to i32. Originated from Duncan's testcase. llvm-svn: 132893
2011-06-12 22:56:55 +08:00
NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
Op.getOperand(0).getValueType().isFloatingPoint()) {
Avoid FGETSIGN of 80-bit types. Fixes PR10085. llvm-svn: 132681
2011-06-07 00:44:31 +08:00
bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
initial code for forming an FGETSIGN node. This is disabled until legalizer support goes in. llvm-svn: 45323
2007-12-23 05:35:38 +08:00
// Make a FGETSIGN + SHL to move the sign bit into the appropriate
// place. We expect the SHL to be eliminated by other optimizations.
Fix double FGETSIGN to work on x86_32; followup to 132396. rdar://problem/5660695 llvm-svn: 132411
2011-06-02 02:32:25 +08:00
SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
Avoid FGETSIGN of 80-bit types. Fixes PR10085. llvm-svn: 132681
2011-06-07 00:44:31 +08:00
unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
if (!OpVTLegal && OpVTSizeInBits > 32)
Fix double FGETSIGN to work on x86_32; followup to 132396. rdar://problem/5660695 llvm-svn: 132411
2011-06-02 02:32:25 +08:00
Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695 llvm-svn: 132396
2011-06-01 22:04:17 +08:00
SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
Update some currently-disabled code, preparing for eventual use. llvm-svn: 131663
2011-05-20 02:48:20 +08:00
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
Op.getValueType(),
initial code for forming an FGETSIGN node. This is disabled until legalizer support goes in. llvm-svn: 45323
2007-12-23 05:35:38 +08:00
Sign, ShAmt));
}
}
break;
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
case ISD::ADD:
case ISD::MUL:
case ISD::SUB: {
// Add, Sub, and Mul don't demand any bits in positions beyond that
// of the highest bit demanded of them.
APInt LoMask = APInt::getLowBitsSet(BitWidth,
BitWidth - NewMask.countLeadingZeros());
if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
KnownOne2, TLO, Depth+1))
return true;
if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
KnownOne2, TLO, Depth+1))
return true;
// See if the operation should be performed at a smaller bit width.
Reapply r106634, now that the bug it exposed is fixed. llvm-svn: 106746
2010-06-24 22:30:44 +08:00
if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. llvm-svn: 68576
2009-04-08 08:15:30 +08:00
return true;
}
// FALL THROUGH
Instead of enumerating each opcode that isn't handled that ComputeMaskedBits handles, just use a 'default:'. This avoids TargetLowering's list getting out of date with SelectionDAG's. llvm-svn: 50693
2008-05-06 08:53:29 +08:00
default:
Allow targets to compute masked bits for intrinsics. llvm-svn: 27357
2006-04-02 14:15:09 +08:00
// Just use ComputeMaskedBits to compute output bits.
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
Implement bit propagation through sub nodes, this (re)implements PowerPC/div-2.ll llvm-svn: 26392
2006-02-27 09:00:42 +08:00
break;
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
// If we know the value of all of the demanded bits, return this as a
// constant.
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt. Change several cases in SimplifyDemandedMask that don't ever do any simplifying to reuse the logic in ComputeMaskedBits instead of duplicating it. llvm-svn: 47648
2008-02-27 08:25:32 +08:00
if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Add a bunch of missed cases. Perhaps the most significant of which is that assertzext produces zero bits. llvm-svn: 26386
2006-02-27 07:36:02 +08:00
return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Add a framework for eliminating instructions that produces undemanded bits. llvm-svn: 25945
2006-02-04 06:24:05 +08:00
return false;
}
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. llvm-svn: 25803
2006-01-30 12:09:27 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
/// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
/// KnownZero/KnownOne bitsets.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero,
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
2008-02-13 08:35:47 +08:00
APInt &KnownOne,
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. llvm-svn: 37704
2007-06-22 22:59:07 +08:00
const SelectionDAG &DAG,
Rework the SelectionDAG-based implementations of SimplifyDemandedBits and ComputeMaskedBits to match the new improved versions in instcombine. Tested against all of multisource/benchmarks on ppc. llvm-svn: 26238
2006-02-17 05:11:51 +08:00
unsigned Depth) const {
relax assertion llvm-svn: 27358
2006-04-02 14:19:46 +08:00
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,making isMaskedValueZeroForTargetNode simpler, and useable from other partsof the compiler. llvm-svn: 25803
2006-01-30 12:09:27 +08:00
"Should use MaskedValueIsZero if you don't know whether Op"
" is a target node!");
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
* Fix a GlobalAddress lowering bug. * Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook. llvm-svn: 24921
2005-12-22 07:05:39 +08:00
}
Implement a method for inline asm support llvm-svn: 25660
2006-01-27 04:37:03 +08:00
Add some really really simple code for computing sign-bit propagation. This will certainly be enhanced in the future. llvm-svn: 28145
2006-05-06 17:27:13 +08:00
/// ComputeNumSignBitsForTargetNode - This method can be implemented by
/// targets that want to expose additional information about sign bits to the
/// DAG Combiner.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Add some really really simple code for computing sign-bit propagation. This will certainly be enhanced in the future. llvm-svn: 28145
2006-05-06 17:27:13 +08:00
unsigned Depth) const {
assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
Op.getOpcode() == ISD::INTRINSIC_VOID) &&
"Should use ComputeNumSignBits if you don't know whether Op"
" is a target node!");
return 1;
}
Don't assume that a left-shift of a value with one bit set will have one bit set, because the bit may be shifted off the end. Instead, just check for a constant 1 being shifted. This is still sufficient to handle all the cases in test/CodeGen/X86/bt.ll. This fixes PR3583. llvm-svn: 64622
2009-02-16 07:59:32 +08:00
/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
/// determine which bit is set.
///
Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c llvm-svn: 64314
2009-02-12 03:19:41 +08:00
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Don't assume that a left-shift of a value with one bit set will have one bit set, because the bit may be shifted off the end. Instead, just check for a constant 1 being shifted. This is still sufficient to handle all the cases in test/CodeGen/X86/bt.ll. This fixes PR3583. llvm-svn: 64622
2009-02-16 07:59:32 +08:00
// A left-shift of a constant one will have exactly one bit set, because
// shifting the bit off the end is undefined.
if (Val.getOpcode() == ISD::SHL)
if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
if (C->getAPIntValue() == 1)
return true;
// Similarly, a right-shift of a constant sign-bit will have exactly
// one bit set.
if (Val.getOpcode() == ISD::SRL)
if (ConstantSDNode *C =
dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
if (C->getAPIntValue().isSignBit())
return true;
// More could be done here, though the above checks are enough
// to handle some common cases.
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
Don't assume that a left-shift of a value with one bit set will have one bit set, because the bit may be shifted off the end. Instead, just check for a constant 1 being shifted. This is still sufficient to handle all the cases in test/CodeGen/X86/bt.ll. This fixes PR3583. llvm-svn: 64622
2009-02-16 07:59:32 +08:00
// Fall back to ComputeMaskedBits to catch other known cases.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT OpVT = Val.getValueType();
Fix several places to handle vector operands properly. Based on a patch by Micah Villmow for PR6438. llvm-svn: 97538
2010-03-02 10:14:38 +08:00
unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
APInt KnownZero, KnownOne;
Always compute all the bits in ComputeMaskedBits. This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
2012-04-04 20:51:34 +08:00
DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c llvm-svn: 64314
2009-02-12 03:19:41 +08:00
return (KnownZero.countPopulation() == BitWidth - 1) &&
(KnownOne.countPopulation() == 1);
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
Add some really really simple code for computing sign-bit propagation. This will certainly be enhanced in the future. llvm-svn: 28145
2006-05-06 17:27:13 +08:00
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
/// and cc. If it is unable to simplify it, return a null SDValue.
SDValue
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
ISD::CondCode Cond, bool foldBooleans,
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DAGCombinerInfo &DCI, DebugLoc dl) const {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
SelectionDAG &DAG = DCI.DAG;
// These setcc operations always fold.
switch (Cond) {
default: break;
case ISD::SETFALSE:
case ISD::SETFALSE2: return DAG.getConstant(0, VT);
case ISD::SETTRUE:
case ISD::SETTRUE2: return DAG.getConstant(1, VT);
}
Fix a ton of comment typos found by codespell. Patch by Luis Felipe Strano Moraes! llvm-svn: 129558
2011-04-15 13:18:47 +08:00
// Ensure that the constant occurs on the RHS, and fold constant
// comparisons.
if (isa<ConstantSDNode>(N0.getNode()))
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
Lower multiply with overflow checking to __mulo<mode> calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
2011-06-18 04:41:29 +08:00
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
More APInt-ification. llvm-svn: 47866
2008-03-04 06:22:56 +08:00
const APInt &C1 = N1C->getAPIntValue();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
// equality comparison, then we're just comparing whether X itself is
// zero.
if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
const APInt &ShAmt
= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
if ((C1 == 0) == (Cond == ISD::SETEQ)) {
// (srl (ctlz x), 5) == 0 -> X != 0
// (srl (ctlz x), 5) != 1 -> X != 0
Cond = ISD::SETNE;
} else {
// (srl (ctlz x), 5) != 0 -> X == 0
// (srl (ctlz x), 5) == 1 -> X == 0
Cond = ISD::SETEQ;
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
SDValue Zero = DAG.getConstant(0, N0.getValueType());
return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
Zero, Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
When we're doing a compare of load-AND-constant to 0 (e.g. a bitfield test) narrow the load as much as possible. The has the potential to avoid unnecessary partial-word load-after-store conflicts, which cause stalls on several targets. Also a size win on x86 (testb vs testl). llvm-svn: 58825
2008-11-07 09:28:02 +08:00
Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0. This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. llvm-svn: 123621
2011-01-17 20:04:57 +08:00
SDValue CTPOP = N0;
// Look through truncs that don't change the value of a ctpop.
if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
CTPOP = N0.getOperand(0);
if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Fix an off-by-one error in ctpop combining. llvm-svn: 123664
2011-01-18 02:00:28 +08:00
(N0 == CTPOP || N0.getValueType().getSizeInBits() >
Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0. This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. llvm-svn: 123621
2011-01-17 20:04:57 +08:00
Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
EVT CTVT = CTPOP.getValueType();
SDValue CTOp = CTPOP.getOperand(0);
// (ctpop x) u< 2 -> (x & x-1) == 0
// (ctpop x) u> 1 -> (x & x-1) != 0
if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
DAG.getConstant(1, CTVT));
SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
}
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
2012-09-27 18:14:43 +08:00
// TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
Add a DAGCombine to turn (ctpop x) u< 2 into (x & x-1) == 0. This shaves off 4 popcounts from the hacked 186.crafty source. This is enabled even when a native popcount instruction is available. The combined code is one operation longer but it should be faster nevertheless. llvm-svn: 123621
2011-01-17 20:04:57 +08:00
}
DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless. On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
2011-04-23 02:47:44 +08:00
// (zext x) == C --> x == (trunc C)
if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
unsigned MinBits = N0.getValueSizeInBits();
SDValue PreZExt;
if (N0->getOpcode() == ISD::ZERO_EXTEND) {
// ZExt
MinBits = N0->getOperand(0).getValueSizeInBits();
PreZExt = N0->getOperand(0);
} else if (N0->getOpcode() == ISD::AND) {
// DAGCombine turns costly ZExts into ANDs
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
if ((C->getAPIntValue()+1).isPowerOf2()) {
MinBits = C->getAPIntValue().countTrailingOnes();
PreZExt = N0->getOperand(0);
}
} else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
// ZEXTLOAD
if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
MinBits = LN0->getMemoryVT().getSizeInBits();
PreZExt = N0;
}
}
Fix typos found by http://github.com/lyda/misspell-check llvm-svn: 157885
2012-06-02 18:20:22 +08:00
// Make sure we're not losing bits from the constant.
DAGCombine: fold "(zext x) == C" into "x == (trunc C)" if the trunc is lossless. On x86 this allows to fold a load into the cmp, greatly reducing register pressure. movzbl (%rdi), %eax cmpl $47, %eax -> cmpb $47, (%rdi) This shaves 8k off gcc.o on i386. I'll leave applying the patch in README.txt to Chris :) llvm-svn: 130005
2011-04-23 02:47:44 +08:00
if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
// Will get folded away.
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
return DAG.getSetCC(dl, VT, Trunc, C, Cond);
}
}
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// If the LHS is '(and load, const)', the RHS is 0,
// the test is for equality or unsigned, and all 1 bits of the const are
// in the same partial word, see if we can shorten the load.
if (DCI.isBeforeLegalize() &&
N0.getOpcode() == ISD::AND && C1 == 0 &&
N0.getNode()->hasOneUse() &&
isa<LoadSDNode>(N0.getOperand(0)) &&
N0.getOperand(0).getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1))) {
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
APInt bestMask;
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
unsigned bestWidth = 0, bestOffset = 0;
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
if (!Lod->isVolatile() && Lod->isUnindexed()) {
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
unsigned origWidth = N0.getValueType().getSizeInBits();
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
unsigned maskWidth = origWidth;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// 8 bits, but have to be careful...
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
origWidth = Lod->getMemoryVT().getSizeInBits();
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
const APInt &Mask =
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
for (unsigned offset=0; offset<origWidth/width; offset++) {
if ((newMask & Mask) == Mask) {
if (!TD->isLittleEndian())
bestOffset = (origWidth/width - offset - 1) * (width/8);
else
bestOffset = (uint64_t)offset * (width/8);
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
bestMask = Mask.lshr(offset * (width/8) * 8);
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
bestWidth = width;
break;
When we're doing a compare of load-AND-constant to 0 (e.g. a bitfield test) narrow the load as much as possible. The has the potential to avoid unnecessary partial-word load-after-store conflicts, which cause stalls on several targets. Also a size win on x86 (testb vs testl). llvm-svn: 58825
2008-11-07 09:28:02 +08:00
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
newMask = newMask << width;
When we're doing a compare of load-AND-constant to 0 (e.g. a bitfield test) narrow the load as much as possible. The has the potential to avoid unnecessary partial-word load-after-store conflicts, which cause stalls on several targets. Also a size win on x86 (testb vs testl). llvm-svn: 58825
2008-11-07 09:28:02 +08:00
}
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
if (bestWidth) {
sink a call into its only use. llvm-svn: 129503
2011-04-14 12:12:47 +08:00
EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (newVT.isRound()) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT PtrType = Lod->getOperand(1).getValueType();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
SDValue Ptr = Lod->getBasePtr();
if (bestOffset != 0)
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
DAG.getConstant(bestOffset, PtrType));
unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
continue MachinePointerInfo'izing, eliminating use of one of the old getLoad overloads. llvm-svn: 114443
2010-09-22 00:36:31 +08:00
Lod->getPointerInfo().getWithOffset(bestOffset),
Added invariant field to the DAG.getLoad method and changed all calls. When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
2011-11-09 02:42:53 +08:00
false, false, false, NewAlign);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getNode(ISD::AND, dl, newVT, NewLoad,
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
DAG.getConstant(bestMask.trunc(bestWidth),
newVT)),
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(0LL, newVT), Cond);
When we're doing a compare of load-AND-constant to 0 (e.g. a bitfield test) narrow the load as much as possible. The has the potential to avoid unnecessary partial-word load-after-store conflicts, which cause stalls on several targets. Also a size win on x86 (testb vs testl). llvm-svn: 58825
2008-11-07 09:28:02 +08:00
}
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
Temporarily revert r58979 and related patch. It's causing a failure in X86 bootstrap: Comparing stages 2 and 3 warning: ./cc1-checksum.o differs warning: ./cc1obj-checksum.o differs warning: ./cc1objplus-checksum.o differs warning: ./cc1plus-checksum.o differs Bootstrap comparison failure! ./alias.o differs ./alloc-pool.o differs ./attribs.o differs ./bb-reorder.o differs ./bitmap.o differs ./build/errors.o differs ./build/genattrtab.o differs ./build/genautomata.o differs ./build/genemit.o differs ./build/genextract.o differs ... -bw llvm-svn: 59003
2008-11-11 05:22:06 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
if (N0.getOpcode() == ISD::ZERO_EXTEND) {
unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// If the comparison constant has bits in the upper part, the
// zero-extended value could never match.
if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
C1.getBitWidth() - InSize))) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
switch (Cond) {
case ISD::SETUGT:
case ISD::SETUGE:
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
case ISD::SETEQ: return DAG.getConstant(0, VT);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
case ISD::SETULT:
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
case ISD::SETULE:
case ISD::SETNE: return DAG.getConstant(1, VT);
case ISD::SETGT:
case ISD::SETGE:
// True if the sign bit of C1 is set.
return DAG.getConstant(C1.isNegative(), VT);
case ISD::SETLT:
case ISD::SETLE:
// True if the sign bit of C1 isn't set.
return DAG.getConstant(C1.isNonNegative(), VT);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
default:
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
break;
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// Otherwise, we can perform the comparison with the low bits.
switch (Cond) {
case ISD::SETEQ:
case ISD::SETNE:
case ISD::SETUGT:
case ISD::SETUGE:
case ISD::SETULT:
case ISD::SETULE: {
Revert EVT->MVT changes, r169836-169851, due to buildbot failures. llvm-svn: 169854
2012-12-11 19:14:33 +08:00
EVT newVT = N0.getOperand(0).getValueType();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (DCI.isBeforeLegalizeOps() ||
(isOperationLegal(ISD::SETCC, newVT) &&
Change TargetLowering::getCondCodeAction to take an MVT, instead of EVT. llvm-svn: 170522
2012-12-19 18:09:26 +08:00
getCondCodeAction(Cond, newVT.getSimpleVT())==Legal))
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(0),
PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
2010-12-07 16:25:19 +08:00
DAG.getConstant(C1.trunc(InSize), newVT),
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
Cond);
break;
}
default:
break; // todo, be more careful with signed comparisons
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT ExtDstTy = N0.getValueType();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly check the range of the constant when optimizing a comparison between a constant and a sign_extend_inreg node. llvm-svn: 109854
2010-07-30 14:44:31 +08:00
// If the constant doesn't fit into the number of bits for the source of
// the sign extension, it is impossible for both sides to be equal.
if (C1.getMinSignedBits() > ExtSrcTyBits)
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
return DAG.getConstant(Cond == ISD::SETNE, VT);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
SDValue ZextOp;
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT Op0Ty = N0.getOperand(0).getValueType();
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
} else {
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
DAG.getConstant(Imm, Op0Ty));
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(ZextOp.getNode());
// Otherwise, make this a use of a zext.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, ZextOp,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(C1 & APInt::getLowBitsSet(
ExtDstTyBits,
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
ExtSrcTyBits),
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
ExtDstTy),
Cond);
} else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
// SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
if (N0.getOpcode() == ISD::SETCC &&
isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (TrueWhenTrue)
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// Invert the condition.
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
CC = ISD::getSetCCInverse(CC,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
N0.getOperand(0).getValueType().isInteger());
return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if ((N0.getOpcode() == ISD::XOR ||
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
(N0.getOpcode() == ISD::AND &&
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
N0.getOperand(0).getOpcode() == ISD::XOR &&
N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
isa<ConstantSDNode>(N0.getOperand(1)) &&
cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
// can only do this if the top bits are known zero.
unsigned BitWidth = N0.getValueSizeInBits();
if (DAG.MaskedValueIsZero(N0,
APInt::getHighBitsSet(BitWidth,
BitWidth-1))) {
// Okay, get the un-inverted input value.
SDValue Val;
if (N0.getOpcode() == ISD::XOR)
Val = N0.getOperand(0);
else {
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
assert(N0.getOpcode() == ISD::AND &&
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
N0.getOperand(0).getOpcode() == ISD::XOR);
// ((X^1)&1)^1 -> X & 1
Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
N0.getOperand(0).getOperand(0),
N0.getOperand(1));
}
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
return DAG.getSetCC(dl, VT, Val, N1,
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
}
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
} else if (N1C->getAPIntValue() == 1 &&
(VT == MVT::i1 ||
Add codegen support for vector select (in the IR this means a select with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. llvm-svn: 139159
2011-09-07 03:07:46 +08:00
getBooleanContents(false) == ZeroOrOneBooleanContent)) {
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
SDValue Op0 = N0;
if (Op0.getOpcode() == ISD::TRUNCATE)
Op0 = Op0.getOperand(0);
if ((Op0.getOpcode() == ISD::XOR) &&
Op0.getOperand(0).getOpcode() == ISD::SETCC &&
Op0.getOperand(1).getOpcode() == ISD::SETCC) {
// (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
Cond);
Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
2012-12-19 14:12:28 +08:00
}
if (Op0.getOpcode() == ISD::AND &&
isa<ConstantSDNode>(Op0.getOperand(1)) &&
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), when needed. This fixes PR7001 llvm-svn: 102838
2010-05-01 20:52:34 +08:00
if (Op0.getValueType().bitsGT(VT))
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
Op0 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
DAG.getConstant(1, VT));
Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), when needed. This fixes PR7001 llvm-svn: 102838
2010-05-01 20:52:34 +08:00
else if (Op0.getValueType().bitsLT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
DAG.getConstant(1, VT));
Re-apply 97040 with fix. This survives a ppc self-host llvm-gcc bootstrap. llvm-svn: 97310
2010-02-27 15:36:59 +08:00
return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
}
Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition. llvm-svn: 170495
2012-12-19 14:12:28 +08:00
if (Op0.getOpcode() == ISD::AssertZext &&
cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
APInt MinVal, MaxVal;
unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
if (ISD::isSignedIntSetCC(Cond)) {
MinVal = APInt::getSignedMinValue(OperandBitSize);
MaxVal = APInt::getSignedMaxValue(OperandBitSize);
} else {
MinVal = APInt::getMinValue(OperandBitSize);
MaxVal = APInt::getMaxValue(OperandBitSize);
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// Canonicalize GE/LE comparisons to use GT/LT comparisons.
if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
// X >= C0 --> X > (C0-1)
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(C1-1, N1.getValueType()),
(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
// X <= C0 --> X < (C0+1)
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(C1+1, N1.getValueType()),
(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
}
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
return DAG.getConstant(0, VT); // X < MIN --> false
if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
return DAG.getConstant(1, VT); // X >= MIN --> true
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
return DAG.getConstant(0, VT); // X > MAX --> false
if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
return DAG.getConstant(1, VT); // X <= MAX --> true
// Canonicalize setgt X, Min --> setne X, Min
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
// Canonicalize setlt X, Max --> setne X, Max
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
// If we have setult X, 1, turn it into seteq X, 0
if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0,
DAG.getConstant(MinVal, N0.getValueType()),
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
ISD::SETEQ);
// If we have setugt X, Max-1, turn it into seteq X, Max
Remove more of 'else's after 'returns'. No functional change. llvm-svn: 170497
2012-12-19 14:43:58 +08:00
if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(MaxVal, N0.getValueType()),
ISD::SETEQ);
// If we have "setcc X, C0", check to see if we can shrink the immediate
// by changing cc.
// SETUGT X, SINTMAX -> SETLT X, 0
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (Cond == ISD::SETUGT &&
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
C1 == APInt::getSignedMaxValue(OperandBitSize))
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0,
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
DAG.getConstant(0, N1.getValueType()),
ISD::SETLT);
// SETULT X, SINTMIN -> SETGT X, -1
if (Cond == ISD::SETULT &&
C1 == APInt::getSignedMinValue(OperandBitSize)) {
SDValue ConstMinusOne =
DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
N1.getValueType());
return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
}
// Fold bit comparisons when we can.
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Teach dag combine to fold the following transformation more aggressively: (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
2010-01-07 03:38:29 +08:00
(VT == N0.getValueType() ||
(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
N0.getOpcode() == ISD::AND)
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
TargetLowering: Use the large shift amount during legalize types. The legalizer may call us with an overly large type. llvm-svn: 162101
2012-08-17 23:54:21 +08:00
EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
getPointerTy() : getShiftAmountTy(N0.getValueType());
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
if (AndRHS->getAPIntValue().isPowerOf2()) {
Teach dag combine to fold the following transformation more aggressively: (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
2010-01-07 03:38:29 +08:00
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
APInt'fy TargetLowering::SimplifySetCC to fix PR5963. llvm-svn: 92943
2010-01-08 04:58:44 +08:00
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C1 is a single bit.
if (C1.isPowerOf2()) {
Teach dag combine to fold the following transformation more aggressively: (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
2010-01-07 03:38:29 +08:00
return DAG.getNode(ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
DAG.getConstant(C1.logBase2(), ShiftTy)));
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
}
Reorganize code a bit to reduce indentation. No visible functionality change. llvm-svn: 77171
2009-07-27 07:47:17 +08:00
}
This is another case where instcombine demanded bits optimization created large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
2012-07-17 14:53:39 +08:00
Make sure constant bitwidth is <= 64 bit before calling getSExtValue(). llvm-svn: 160350
2012-07-17 15:47:50 +08:00
if (C1.getMinSignedBits() <= 64 &&
!isLegalICmpImmediate(C1.getSExtValue())) {
This is another case where instcombine demanded bits optimization created large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
2012-07-17 14:53:39 +08:00
// (X & -256) == 256 -> (X >> 8) == 1
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
const APInt &AndRHSC = AndRHS->getAPIntValue();
if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
unsigned ShiftBits = AndRHSC.countTrailingZeros();
TargetLowering: Use the large shift amount during legalize types. The legalizer may call us with an overly large type. llvm-svn: 162101
2012-08-17 23:54:21 +08:00
EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
This is another case where instcombine demanded bits optimization created large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
2012-07-17 14:53:39 +08:00
getPointerTy() : getShiftAmountTy(N0.getValueType());
EVT CmpTy = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
DAG.getConstant(ShiftBits, ShiftTy));
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
}
}
Implement r160312 as target indepedenet dag combine. llvm-svn: 160354
2012-07-17 16:31:11 +08:00
} else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
Cond == ISD::SETULE || Cond == ISD::SETUGT) {
bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
// X < 0x100000000 -> (X >> 32) < 1
// X >= 0x100000000 -> (X >> 32) >= 1
// X <= 0x0ffffffff -> (X >> 32) < 1
// X > 0x0ffffffff -> (X >> 32) >= 1
unsigned ShiftBits;
APInt NewC = C1;
ISD::CondCode NewCond = Cond;
if (AdjOne) {
ShiftBits = C1.countTrailingOnes();
NewC = NewC + 1;
NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
} else {
ShiftBits = C1.countTrailingZeros();
}
NewC = NewC.lshr(ShiftBits);
if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
TargetLowering: Use the large shift amount during legalize types. The legalizer may call us with an overly large type. llvm-svn: 162101
2012-08-17 23:54:21 +08:00
EVT ShiftTy = DCI.isBeforeLegalizeOps() ?
Implement r160312 as target indepedenet dag combine. llvm-svn: 160354
2012-07-17 16:31:11 +08:00
getPointerTy() : getShiftAmountTy(N0.getValueType());
EVT CmpTy = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
DAG.getConstant(ShiftBits, ShiftTy));
SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
}
This is another case where instcombine demanded bits optimization created large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
2012-07-17 14:53:39 +08:00
}
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (isa<ConstantFPSDNode>(N0.getNode())) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
// Constant fold or commute setcc.
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (O.getNode()) return O;
} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Fold comparisons against a constant nan, and optimize ORD/UNORD comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
2007-12-29 16:37:08 +08:00
// If the RHS of an FP comparison is a constant, simplify it away in
// some cases.
if (CFP->getValueAPF().isNaN()) {
// If an operand is known to be a nan, we can fold it.
switch (ISD::getUnorderedFlavor(Cond)) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Unknown flavor!");
Fold comparisons against a constant nan, and optimize ORD/UNORD comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
2007-12-29 16:37:08 +08:00
case 0: // Known false.
return DAG.getConstant(0, VT);
case 1: // Known true.
return DAG.getConstant(1, VT);
fix typo duncan noticed! llvm-svn: 45459
2007-12-31 05:21:10 +08:00
case 2: // Undefined.
Remove more non-DebugLoc getNode variants. Use getCALLSEQ_{END,START} to permit passing no DebugLoc there. UNDEF doesn't logically have DebugLoc; add getUNDEF to encapsulate this. llvm-svn: 63978
2009-02-07 07:05:02 +08:00
return DAG.getUNDEF(VT);
Fold comparisons against a constant nan, and optimize ORD/UNORD comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
2007-12-29 16:37:08 +08:00
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Fold comparisons against a constant nan, and optimize ORD/UNORD comparisons with a constant. This allows us to compile isnan to: _foo: fcmpu cr7, f1, f1 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr instead of: LCPI1_0: ; float .space 4 _foo: lis r2, ha16(LCPI1_0) lfs f0, lo16(LCPI1_0)(r2) fcmpu cr7, f1, f0 mfcr r2 rlwinm r3, r2, 0, 31, 31 blr llvm-svn: 45405
2007-12-29 16:37:08 +08:00
// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
// constant if knowing that the operand is non-nan is enough. We prefer to
// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
// materialize 0.0.
if (Cond == ISD::SETO || Cond == ISD::SETUO)
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0, N0, Cond);
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
// If the condition is not legal, see if we can find an equivalent one
// which is legal.
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
// If the comparison was an awkward floating-point == or != and one of
// the comparison operands is infinity or negative infinity, convert the
// condition to a less-awkward <= or >=.
if (CFP->getValueAPF().isInfinity()) {
if (CFP->getValueAPF().isNegative()) {
if (Cond == ISD::SETOEQ &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
if (Cond == ISD::SETUEQ &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
if (Cond == ISD::SETUNE &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
if (Cond == ISD::SETONE &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
} else {
if (Cond == ISD::SETOEQ &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
if (Cond == ISD::SETUEQ &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
if (Cond == ISD::SETUNE &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
if (Cond == ISD::SETONE &&
Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT. llvm-svn: 170524
2012-12-19 18:19:55 +08:00
isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
Convert comparisons like (x == infinity) to (x >= infinity) on targets where FCMP_OEQ is not legal and FCMP_OGE is, such as x86. llvm-svn: 82861
2009-09-26 23:24:17 +08:00
return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
}
}
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
if (N0 == N1) {
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1 booleans. Patch by James Benton. llvm-svn: 159739
2012-07-05 17:32:46 +08:00
// The sext(setcc()) => setcc() optimization relies on the appropriate
// constant being emitted.
Fix a few old-GCC warnings. No functional change. llvm-svn: 163309
2012-09-06 19:13:55 +08:00
uint64_t EqVal = 0;
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1 booleans. Patch by James Benton. llvm-svn: 159739
2012-07-05 17:32:46 +08:00
switch (getBooleanContents(N0.getValueType().isVector())) {
case UndefinedBooleanContent:
case ZeroOrOneBooleanContent:
EqVal = ISD::isTrueWhenEqual(Cond);
break;
case ZeroOrNegativeOneBooleanContent:
EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
break;
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
// We can always fold X == X for integer setcc's.
Fix an issue in SimplifySetCC() specific to vector comparisons. When folding X == X we need to check getBooleanContents() to determine if the result is a vector of ones or a vector of negative ones. I tried creating a test case, but the problem seems to only be exposed on a much older version of clang (around r144500). rdar://10923049 llvm-svn: 153966
2012-04-04 04:11:24 +08:00
if (N0.getValueType().isInteger()) {
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1 booleans. Patch by James Benton. llvm-svn: 159739
2012-07-05 17:32:46 +08:00
return DAG.getConstant(EqVal, VT);
Fix an issue in SimplifySetCC() specific to vector comparisons. When folding X == X we need to check getBooleanContents() to determine if the result is a vector of ones or a vector of negative ones. I tried creating a test case, but the problem seems to only be exposed on a much older version of clang (around r144500). rdar://10923049 llvm-svn: 153966
2012-04-04 04:11:24 +08:00
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
unsigned UOF = ISD::getUnorderedFlavor(Cond);
if (UOF == 2) // FP operators that are undefined on NaNs.
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1 booleans. Patch by James Benton. llvm-svn: 159739
2012-07-05 17:32:46 +08:00
return DAG.getConstant(EqVal, VT);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
Use the right kind of booleans: we were emitting 0/1 booleans, instead of 0/-1 booleans. Patch by James Benton. llvm-svn: 159739
2012-07-05 17:32:46 +08:00
return DAG.getConstant(EqVal, VT);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
// if it is not already.
ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
Conform to LLVM coding style. llvm-svn: 161061
2012-08-01 02:07:43 +08:00
if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
Change TargetLowering::getCondCodeAction to take an MVT, instead of EVT. llvm-svn: 170522
2012-12-19 18:09:26 +08:00
getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
N0.getValueType().isInteger()) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
N0.getOpcode() == ISD::XOR) {
// Simplify (X+Y) == (X+Z) --> Y == Z
if (N0.getOpcode() == N1.getOpcode()) {
if (N0.getOperand(0) == N1.getOperand(0))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (N0.getOperand(1) == N1.getOperand(1))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (DAG.isCommutativeBinOp(N0.getOpcode())) {
// If X op Y == Y op X, try other combinations.
if (N0.getOperand(0) == N1.getOperand(1))
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (N0.getOperand(1) == N1.getOperand(0))
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
2012-04-06 04:30:20 +08:00
// If RHS is a legal immediate value for a compare instruction, we need
// to be careful about increasing register pressure needlessly.
bool LegalRHSImm = false;
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
// Turn (X+C1) == C2 --> X == C2-C1
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0.getOperand(0),
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
DAG.getConstant(RHSC->getAPIntValue()-
LHSR->getAPIntValue(),
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
N0.getValueType()), Cond);
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 llvm-svn: 164768
2012-09-27 18:14:43 +08:00
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (N0.getOpcode() == ISD::XOR)
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.
Convert MaskedValueIsZero and all its users to use APInt. Also add a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
2008-02-26 05:11:39 +08:00
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
return
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DAG.getSetCC(dl, VT, N0.getOperand(0),
Convert MaskedValueIsZero and all its users to use APInt. Also add a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
2008-02-26 05:11:39 +08:00
DAG.getConstant(LHSR->getAPIntValue() ^
RHSC->getAPIntValue(),
N0.getValueType()),
Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
// Turn (C1-X) == C2 --> X == C1-C2
if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Convert MaskedValueIsZero and all its users to use APInt. Also add a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
2008-02-26 05:11:39 +08:00
return
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DAG.getSetCC(dl, VT, N0.getOperand(1),
Convert MaskedValueIsZero and all its users to use APInt. Also add a SignBitIsZero function to simplify a common use case. llvm-svn: 47561
2008-02-26 05:11:39 +08:00
DAG.getConstant(SUBC->getAPIntValue() -
RHSC->getAPIntValue(),
N0.getValueType()),
Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
}
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
2012-04-06 04:30:20 +08:00
// Could RHSC fold directly into a compare?
if (RHSC->getValueType(0).getSizeInBits() <= 64)
LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
// Simplify (X+Z) == X --> Z == 0
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
2012-04-06 04:30:20 +08:00
// Don't do this if X is an immediate that can fold into a cmp
// instruction and X+Z has other uses. It could be an induction variable
// chain, and the transform would increase register pressure.
if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
if (N0.getOperand(0) == N1)
return DAG.getSetCC(dl, VT, N0.getOperand(1),
DAG.getConstant(0, N0.getValueType()), Cond);
if (N0.getOperand(1) == N1) {
if (DAG.isCommutativeBinOp(N0.getOpcode()))
return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(0, N0.getValueType()), Cond);
Remove more of 'else's after 'returns'. No functional change. llvm-svn: 170497
2012-12-19 14:43:58 +08:00
if (N0.getNode()->hasOneUse()) {
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
2012-04-06 04:30:20 +08:00
assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
// (Z-X) == X --> Z == X<<1
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Don't break the IV update in TLI::SimplifySetCC(). LSR always tries to make the ICmp in the loop latch use the incremented induction variable. This allows the induction variable to be kept in a single register. When the induction variable limit is equal to the stride, SimplifySetCC() would break LSR's hard work by transforming: (icmp (add iv, stride), stride) --> (cmp iv, 0) This forced us to use lea for the IC update, preventing the simpler incl+cmp. <rdar://problem/7643606> <rdar://problem/11184260> llvm-svn: 154119
2012-04-06 04:30:20 +08:00
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(SH.getNode());
return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
}
}
if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
N1.getOpcode() == ISD::XOR) {
// Simplify X == (X+Z) --> Z == 0
Remove more of 'else's after 'returns'. No functional change. llvm-svn: 170497
2012-12-19 14:43:58 +08:00
if (N1.getOperand(0) == N0)
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N1.getOperand(1),
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
DAG.getConstant(0, N1.getValueType()), Cond);
Remove more of 'else's after 'returns'. No functional change. llvm-svn: 170497
2012-12-19 14:43:58 +08:00
if (N1.getOperand(1) == N0) {
if (DAG.isCommutativeBinOp(N1.getOpcode()))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N1.getOperand(0),
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
DAG.getConstant(0, N1.getValueType()), Cond);
Remove more of 'else's after 'returns'. No functional change. llvm-svn: 170497
2012-12-19 14:43:58 +08:00
if (N1.getNode()->hasOneUse()) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
// X == (Z-X) --> X<<1 == Z
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(SH.getNode());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
}
}
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
Fix two typos that Duncan spotted in a comment. llvm-svn: 63312
2009-01-30 00:18:12 +08:00
// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c llvm-svn: 64314
2009-02-12 03:19:41 +08:00
// Note that where y is variable and is known to have at most
// one bit set (for example, if it is z&1) we cannot do this;
// the expressions are not equivalent when y==0.
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
if (N0.getOpcode() == ISD::AND)
if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c llvm-svn: 64314
2009-02-12 03:19:41 +08:00
if (ValueHasExactlyOneBitSet(N1, DAG)) {
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
SDValue Zero = DAG.getConstant(0, N1.getValueType());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
}
if (N1.getOpcode() == ISD::AND)
if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Make a transformation added in 63266 a bit less aggressive. It was transforming (x&y)==y to (x&y)!=0 in the case where y is variable and known to have at most one bit set (e.g. z&1). This is not correct; the expressions are not equivalent when y==0. I believe this patch salvages what can be salvaged, including all the cases in bt.ll. Dan, please review. Fixes gcc.c-torture/execute/20040709-[12].c llvm-svn: 64314
2009-02-12 03:19:41 +08:00
if (ValueHasExactlyOneBitSet(N0, DAG)) {
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
SDValue Zero = DAG.getConstant(0, N0.getValueType());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Make x86's BT instruction matching more thorough, and add some dagcombines that help it match in several more cases. Add several more cases to test/CodeGen/X86/bt.ll. This doesn't yet include matching for BT with an immediate operand, it just covers more register+register cases. llvm-svn: 63266
2009-01-29 09:59:02 +08:00
}
}
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
// Fold away ALL boolean setcc's.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Temp;
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (N0.getValueType() == MVT::i1 && foldBooleans) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
switch (Cond) {
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
2009-07-15 00:55:14 +08:00
default: llvm_unreachable("Unknown integer setcc!");
Add SelectionDAG::getNOT method to construct bitwise NOT operations, corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
2009-01-23 01:39:32 +08:00
case ISD::SETEQ: // X == Y -> ~(X^Y)
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
N0 = DAG.getNOT(dl, Temp, MVT::i1);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(Temp.getNode());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
case ISD::SETNE: // X != Y --> (X^Y)
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
Add SelectionDAG::getNOT method to construct bitwise NOT operations, corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
2009-01-23 01:39:32 +08:00
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
Temp = DAG.getNOT(dl, N0, MVT::i1);
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(Temp.getNode());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
Add SelectionDAG::getNOT method to construct bitwise NOT operations, corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
2009-01-23 01:39:32 +08:00
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
Temp = DAG.getNOT(dl, N1, MVT::i1);
N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(Temp.getNode());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
Add SelectionDAG::getNOT method to construct bitwise NOT operations, corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
2009-01-23 01:39:32 +08:00
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
Temp = DAG.getNOT(dl, N0, MVT::i1);
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(Temp.getNode());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
Add SelectionDAG::getNOT method to construct bitwise NOT operations, corresponding to the "not" and "vnot" PatFrags. Use the new method in some places where it seems appropriate. llvm-svn: 62768
2009-01-23 01:39:32 +08:00
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
Temp = DAG.getNOT(dl, N1, MVT::i1);
N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
break;
}
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
if (VT != MVT::i1) {
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
if (!DCI.isCalledByLegalizer())
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DCI.AddToWorklist(N0.getNode());
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
// FIXME: If running after legalize, we probably can't do this.
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
return N0;
}
// Could not fold it.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
return SDValue();
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer. llvm-svn: 34065
2007-02-09 06:13:59 +08:00
}
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
/// node is a GlobalAddress + offset.
Enhance ComputeMaskedBits to know that aligned frameindexes have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. llvm-svn: 125470
2011-02-14 06:25:43 +08:00
bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
int64_t &Offset) const {
if (isa<GlobalAddressSDNode>(N)) {
Teach isGAPlusOffset to respect a GlobalAddressSDNode's offset value, which is something that apparently isn't used much. llvm-svn: 52158
2008-06-10 06:05:52 +08:00
GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
GA = GASD->getGlobal();
Offset += GASD->getOffset();
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
return true;
}
if (N->getOpcode() == ISD::ADD) {
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue N1 = N->getOperand(0);
SDValue N2 = N->getOperand(1);
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
if (V) {
Rename ConstantSDNode's getSignExtended to getSExtValue, for consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. llvm-svn: 56700
2008-09-27 05:54:37 +08:00
Offset += V->getSExtValue();
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
return true;
}
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
if (V) {
Rename ConstantSDNode's getSignExtended to getSExtValue, for consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. llvm-svn: 56700
2008-09-27 05:54:37 +08:00
Offset += V->getSExtValue();
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
return true;
}
}
}
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it. llvm-svn: 50991
2008-05-13 03:56:52 +08:00
return false;
}
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue TargetLowering::
Add interfaces for targets to provide target-specific dag combiner optimizations. llvm-svn: 26442
2006-03-01 12:52:55 +08:00
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
// Default implementation: no optimization.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
return SDValue();
Add interfaces for targets to provide target-specific dag combiner optimizations. llvm-svn: 26442
2006-03-01 12:52:55 +08:00
}
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
//===----------------------------------------------------------------------===//
// Inline Assembler Implementation Methods
//===----------------------------------------------------------------------===//
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
TargetLowering::ConstraintType
switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. llvm-svn: 35322
2007-03-25 10:14:49 +08:00
TargetLowering::getConstraintType(const std::string &Constraint) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default: break;
case 'r': return C_RegisterClass;
case 'm': // memory
case 'o': // offsetable
case 'V': // not offsetable
return C_Memory;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
case 'E': // Floating Point Constant
case 'F': // Floating Point Constant
switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. llvm-svn: 35322
2007-03-25 10:14:49 +08:00
case 's': // Relocatable Constant
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
case 'p': // Address.
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll llvm-svn: 35327
2007-03-25 12:35:41 +08:00
case 'X': // Allow ANY value.
switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. llvm-svn: 35322
2007-03-25 10:14:49 +08:00
case 'I': // Target registers.
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P':
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
case '<':
case '>':
switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. llvm-svn: 35322
2007-03-25 10:14:49 +08:00
return C_Other;
}
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (Constraint.size() > 1 && Constraint[0] == '{' &&
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll llvm-svn: 35324
2007-03-25 10:18:14 +08:00
Constraint[Constraint.size()-1] == '}')
return C_Register;
switch TargetLowering::getConstraintType to take the entire constraint, not just the first letter. No functionality change. llvm-svn: 35322
2007-03-25 10:14:49 +08:00
return C_Unknown;
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
}
Handle 'X' constraint in asm's better. llvm-svn: 46485
2008-01-29 10:21:21 +08:00
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
if (ConstraintVT.isInteger())
A few inline asm cleanups: - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. llvm-svn: 50312
2008-04-27 07:02:14 +08:00
return "r";
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
2008-06-06 20:08:01 +08:00
if (ConstraintVT.isFloatingPoint())
A few inline asm cleanups: - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. llvm-svn: 50312
2008-04-27 07:02:14 +08:00
return "f"; // works for many targets
return 0;
Handle 'X' constraint in asm's better. llvm-svn: 46485
2008-01-29 10:21:21 +08:00
}
rename isOperandValidForConstraint to LowerAsmOperandForConstraint, changing the interface to allow for future changes. llvm-svn: 41384
2007-08-25 08:47:38 +08:00
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops.
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Have LowerOperandForConstraint handle multiple character constraints. Part of rdar://9119939 llvm-svn: 132510
2011-06-03 07:16:42 +08:00
std::string &Constraint,
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
std::vector<SDValue> &Ops,
A few inline asm cleanups: - Make targetlowering.h fit in 80 cols. - Make LowerAsmOperandForConstraint const. - Make lowerXConstraint -> LowerXConstraint - Make LowerXConstraint return a const char* instead of taking a string byref. llvm-svn: 50312
2008-04-27 07:02:14 +08:00
SelectionDAG &DAG) const {
Lower multiply with overflow checking to __mulo<mode> calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
2011-06-18 04:41:29 +08:00
Have LowerOperandForConstraint handle multiple character constraints. Part of rdar://9119939 llvm-svn: 132510
2011-06-03 07:16:42 +08:00
if (Constraint.length() > 1) return;
Lower multiply with overflow checking to __mulo<mode> calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
2011-06-18 04:41:29 +08:00
Have LowerOperandForConstraint handle multiple character constraints. Part of rdar://9119939 llvm-svn: 132510
2011-06-03 07:16:42 +08:00
char ConstraintLetter = Constraint[0];
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
switch (ConstraintLetter) {
Implement i/n/s constraints correctly. This fixes test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll llvm-svn: 34368
2007-02-17 14:00:35 +08:00
default: break;
Make labels work in asm blocks; allow labels as parameters. Rename ValueRefList to ParamList in AsmParser, since its only use is for parameters. llvm-svn: 43734
2007-11-06 05:20:28 +08:00
case 'X': // Allows any operand; labels (basic block) use this.
if (Op.getOpcode() == ISD::BasicBlock) {
Ops.push_back(Op);
return;
}
// fall through
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
Make labels work in asm blocks; allow labels as parameters. Rename ValueRefList to ParamList in AsmParser, since its only use is for parameters. llvm-svn: 43734
2007-11-06 05:20:28 +08:00
case 's': { // Relocatable Constant
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
2007-05-04 00:54:34 +08:00
// These operands are interested in values of the form (GV+C), where C may
// be folded in as an offset of GV, or it may be explicitly added. Also, it
// is possible and fine if either GV or C are missing.
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
2007-05-04 00:54:34 +08:00
// If we have "(add GV, C)", pull out GV/C
if (Op.getOpcode() == ISD::ADD) {
C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
if (C == 0 || GA == 0) {
C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
}
if (C == 0 || GA == 0)
C = 0, GA = 0;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
2007-05-04 00:54:34 +08:00
// If we find a valid operand, map to the TargetXXX version so that the
// value itself doesn't get selected.
if (GA) { // Either &GV or &GV+C
if (ConstraintLetter != 'n') {
int64_t Offs = GA->getOffset();
Rename ConstantSDNode::getValue to getZExtValue, for consistency with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
2008-09-13 00:56:44 +08:00
if (C) Offs += C->getZExtValue();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Fix crash reported in PR7653. llvm-svn: 108441
2010-07-16 02:45:27 +08:00
C ? C->getDebugLoc() : DebugLoc(),
rename isOperandValidForConstraint to LowerAsmOperandForConstraint, changing the interface to allow for future changes. llvm-svn: 41384
2007-08-25 08:47:38 +08:00
Op.getValueType(), Offs));
return;
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
2007-05-04 00:54:34 +08:00
}
}
if (C) { // just C, no GV.
Implement i/n/s constraints correctly. This fixes test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll llvm-svn: 34368
2007-02-17 14:00:35 +08:00
// Simple constants are not allowed for 's'.
rename isOperandValidForConstraint to LowerAsmOperandForConstraint, changing the interface to allow for future changes. llvm-svn: 41384
2007-08-25 08:47:38 +08:00
if (ConstraintLetter != 's') {
Arrange to print constants that match "n" and "i" constraints in inline asm as signed (what gcc does). Add partial support for x86-specific "e" and "Z" constraints, with appropriate signedness for printing. llvm-svn: 64400
2009-02-13 04:58:09 +08:00
// gcc prints these as sign extended. Sign extend value to 64 bits
// now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
2009-08-12 04:47:22 +08:00
MVT::i64));
rename isOperandValidForConstraint to LowerAsmOperandForConstraint, changing the interface to allow for future changes. llvm-svn: 41384
2007-08-25 08:47:38 +08:00
return;
}
Implement i/n/s constraints correctly. This fixes test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll llvm-svn: 34368
2007-02-17 14:00:35 +08:00
}
break;
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
}
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll and PR1382 llvm-svn: 36672
2007-05-04 00:54:34 +08:00
}
implementation of some methods for inlineasm llvm-svn: 25951
2006-02-04 10:13:02 +08:00
}
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Updates to match change of getRegForInlineAsmConstraint prototype llvm-svn: 26305
2006-02-22 07:11:00 +08:00
getRegForInlineAsmConstraint(const std::string &Constraint,
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT) const {
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
if (Constraint[0] != '{')
Fixes for Microsoft Visual Studio 2010, from Steven Watanabe! llvm-svn: 103457
2010-05-11 14:17:44 +08:00
return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. llvm-svn: 25866
2006-02-01 09:29:47 +08:00
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
// Remove the braces from around the name.
Add compare_lower and equals_lower methods to StringRef. Switch all users of StringsEqualNoCase (from StringExtras.h) to it. llvm-svn: 87020
2009-11-13 04:36:59 +08:00
StringRef RegName(Constraint.data()+1, Constraint.size()-2);
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
Check multiple register classes for inline asm tied registers A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
2012-12-19 01:50:58 +08:00
std::pair<unsigned, const TargetRegisterClass*> R =
std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
// Figure out which register class contains this reg.
Rename MRegisterInfo to TargetRegisterInfo. llvm-svn: 46930
2008-02-11 02:45:23 +08:00
const TargetRegisterInfo *RI = TM.getRegisterInfo();
for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
E = RI->regclass_end(); RCI != E; ++RCI) {
const TargetRegisterClass *RC = *RCI;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// If none of the value types for this register class are valid, we
Don't return registers from register classes that aren't legal. llvm-svn: 26317
2006-02-23 07:00:51 +08:00
// can't use it. For example, 64-bit reg classes on 32-bit targets.
Use an existing function. llvm-svn: 141763
2011-10-12 09:24:51 +08:00
if (!isLegalRC(RC))
continue;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
I != E; ++I) {
Check multiple register classes for inline asm tied registers A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
2012-12-19 01:50:58 +08:00
if (RegName.equals_lower(RI->getName(*I))) {
std::pair<unsigned, const TargetRegisterClass*> S =
std::make_pair(*I, RC);
// If this register class has the requested value type, return it,
// otherwise keep searching and return the first class found
// if no other is found which explicitly has the requested type.
if (RC->hasType(VT))
return S;
else if (!R.second)
R = S;
}
split register class handling from explicit physreg handling. llvm-svn: 26308
2006-02-22 08:56:39 +08:00
}
Implement a method for inline asm support llvm-svn: 25660
2006-01-27 04:37:03 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Check multiple register classes for inline asm tied registers A register can be associated with several distinct register classes. For example, on PPC, the floating point registers are each associated with both F4RC (which holds f32) and F8RC (which holds f64). As a result, this code would fail when provided with a floating point register and an f64 operand because it would happen to find the register in the F4RC class first and return that. From the F4RC class, SDAG would extract f32 as the register type and then assert because of the invalid implied conversion between the f64 value and the f32 register. Instead, search all register classes. If a register class containing the the requested register has the requested type, then return that register class. Otherwise, as before, return the first register class found that contains the requested register. llvm-svn: 170436
2012-12-19 01:50:58 +08:00
return R;
Implement a method for inline asm support llvm-svn: 25660
2006-01-27 04:37:03 +08:00
}
Add LSR hooks. llvm-svn: 26740
2006-03-14 07:18:16 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
//===----------------------------------------------------------------------===//
// Constraint Selection.
Keep track of *which* input constraint matches an output constraint. Reject asms where an output has multiple input constraints tied to it. llvm-svn: 57687
2008-10-18 00:47:46 +08:00
/// isMatchingInputConstraint - Return true of this is an input operand that is
/// a matching constraint like "4".
bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
add an assert so that PR2356 explodes instead of running off an array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
2008-10-18 00:21:11 +08:00
assert(!ConstraintCode.empty() && "No known constraint!");
return isdigit(ConstraintCode[0]);
}
/// getMatchedOperand - If this is an input matching constraint, this method
/// returns the output operand it matches.
unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
assert(!ConstraintCode.empty() && "No known constraint!");
return atoi(ConstraintCode.c_str());
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
/// ParseConstraints - Split up the constraint string from the inline
/// assembly value into the specific constraints and their prefixes,
/// and also tie in the associated operand values.
/// If this returns an empty vector, and if the constraint string itself
/// isn't empty, there was an error parsing.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
ImmutableCallSite CS) const {
/// ConstraintOperands - Information about all of the constraints.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
AsmOperandInfoVector ConstraintOperands;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
unsigned maCount = 0; // Largest number of multiple alternative constraints.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
// Do a prepass over the constraints, canonicalizing them, and building up the
// ConstraintOperands list.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
InlineAsm::ConstraintInfoVector
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
ConstraintInfos = IA->ParseConstraints();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
unsigned ResNo = 0; // ResNo - The result number of the next output.
for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
AsmOperandInfo &OpInfo = ConstraintOperands.back();
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
// Update multiple alternative constraint count.
if (OpInfo.multipleAlternatives.size() > maCount)
maCount = OpInfo.multipleAlternatives.size();
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
OpInfo.ConstraintVT = MVT::Other;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
// Compute the value type for each operand.
switch (OpInfo.Type) {
case InlineAsm::isOutput:
// Indirect outputs just consume an argument.
if (OpInfo.isIndirect) {
OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
break;
}
// The return value of the call is this value. As such, there is no
// corresponding argument.
assert(!CS.getType()->isVoidTy() &&
"Bad inline asm!");
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT. Accordingly, add MVT::getVT. llvm-svn: 170550
2012-12-19 23:19:11 +08:00
OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
} else {
assert(ResNo == 0 && "Asm only has one result!");
Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT. Accordingly, add MVT::getVT. llvm-svn: 170550
2012-12-19 23:19:11 +08:00
OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
}
++ResNo;
break;
case InlineAsm::isInput:
OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
break;
case InlineAsm::isClobber:
// Nothing to do.
break;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (OpInfo.CallOperandVal) {
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (OpInfo.isIndirect) {
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (!PtrTy)
report_fatal_error("Indirect operand for inline asm not a pointer!");
OpTy = PtrTy->getElementType();
}
Lower multiply with overflow checking to __mulo<mode> calls if we haven't been able to lower them any other way. Fixes rdar://9090077 and rdar://9210061 llvm-svn: 133288
2011-06-18 04:41:29 +08:00
Look through struct wrapped types for inline asm statments. Patch by Evan Cheng. llvm-svn: 131093
2011-05-10 04:04:43 +08:00
// Look for vector wrapped in a struct. e.g. { <16 x i8> }.
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
if (StructType *STy = dyn_cast<StructType>(OpTy))
Look through struct wrapped types for inline asm statments. Patch by Evan Cheng. llvm-svn: 131093
2011-05-10 04:04:43 +08:00
if (STy->getNumElements() == 1)
OpTy = STy->getElementType(0);
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
// If OpTy is not a single value, it may be a struct/union that we
// can tile with integers.
if (!OpTy->isSingleValueType() && OpTy->isSized()) {
unsigned BitSize = TD->getTypeSizeInBits(OpTy);
switch (BitSize) {
default: break;
case 1:
case 8:
case 16:
case 32:
case 64:
case 128:
Fix an inline asm pasto from 117667; was preventing {i64, i64} from matching i128. llvm-svn: 118465
2010-11-09 09:15:07 +08:00
OpInfo.ConstraintVT =
Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT. Accordingly, add MVT::getVT. llvm-svn: 170550
2012-12-19 23:19:11 +08:00
MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
break;
}
Add in the first step of the multiple pointer support. This adds in support to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. llvm-svn: 165505
2012-10-10 00:06:12 +08:00
} else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
OpInfo.ConstraintVT = MVT::getIntegerVT(
8*TD->getPointerSize(PT->getAddressSpace()));
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
} else {
Change AsmOperandInfo::ConstraintVT to MVT, instead of EVT. Accordingly, add MVT::getVT. llvm-svn: 170550
2012-12-19 23:19:11 +08:00
OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
}
}
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
}
// If we have multiple alternative constraints, select the best alternative.
if (ConstraintInfos.size()) {
if (maCount) {
unsigned bestMAIndex = 0;
int bestWeight = -1;
// weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
int weight = -1;
unsigned maIndex;
// Compute the sums of the weights for each alternative, keeping track
// of the best (highest weight) one so far.
for (maIndex = 0; maIndex < maCount; ++maIndex) {
int weightSum = 0;
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
cIndex != eIndex; ++cIndex) {
AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
if (OpInfo.Type == InlineAsm::isClobber)
continue;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
// If this is an output operand with a matching input operand,
// look up the matching input. If their types mismatch, e.g. one
// is an integer, the other is floating point, or their sizes are
// different, flag it as an maCantMatch.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
if (OpInfo.hasMatchingInput()) {
AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
if ((OpInfo.ConstraintVT.isInteger() !=
Input.ConstraintVT.isInteger()) ||
(OpInfo.ConstraintVT.getSizeInBits() !=
Input.ConstraintVT.getSizeInBits())) {
weightSum = -1; // Can't match.
break;
}
}
}
weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
if (weight == -1) {
weightSum = -1;
break;
}
weightSum += weight;
}
// Update best.
if (weightSum > bestWeight) {
bestWeight = weightSum;
bestMAIndex = maIndex;
}
}
// Now select chosen alternative in each constraint.
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
cIndex != eIndex; ++cIndex) {
AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
if (cInfo.Type == InlineAsm::isClobber)
continue;
cInfo.selectAlternative(bestMAIndex);
}
}
}
// Check and hook up tied operands, choose constraint code to use.
for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
cIndex != eIndex; ++cIndex) {
AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
// If this is an output operand with a matching input operand, look up the
// matching input. If their types mismatch, e.g. one is an integer, the
// other is floating point, or their sizes are different, flag it as an
// error.
if (OpInfo.hasMatchingInput()) {
AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
Remove tabs. llvm-svn: 160475
2012-07-19 08:04:14 +08:00
std::pair<unsigned, const TargetRegisterClass*> MatchRC =
getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
OpInfo.ConstraintVT);
std::pair<unsigned, const TargetRegisterClass*> InputRC =
getRegForInlineAsmConstraint(Input.ConstraintCode,
Input.ConstraintVT);
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
if ((OpInfo.ConstraintVT.isInteger() !=
Input.ConstraintVT.isInteger()) ||
Check register class matching instead of width of type matching when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
2011-07-15 04:13:52 +08:00
(MatchRC.second != InputRC.second)) {
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
" incompatible type!");
}
}
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
}
}
return ConstraintOperands;
}
add an assert so that PR2356 explodes instead of running off an array. Improve some minor comments, refactor some helpers in AsmOperandInfo. No functionality change for valid code. llvm-svn: 57686
2008-10-18 00:21:11 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
/// getConstraintGenerality - Return an integer indicating how general CT
/// is.
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
switch (CT) {
case TargetLowering::C_Other:
case TargetLowering::C_Unknown:
return 0;
case TargetLowering::C_Register:
return 1;
case TargetLowering::C_RegisterClass:
return 2;
case TargetLowering::C_Memory:
return 3;
}
Add 'llvm_unreachable' to passify GCC's understanding of the constraints of several newly un-defaulted switches. This also helps optimizers (including LLVM's) recognize that every case is covered, and we should assume as much. llvm-svn: 147861
2012-01-11 02:08:01 +08:00
llvm_unreachable("Invalid constraint type");
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
}
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
/// Examine constraint type and operand type and determine a weight value.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
/// This object must already have been set up with the operand type
/// and the current alternative constraint selected.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
TargetLowering::ConstraintWeight
TargetLowering::getMultipleConstraintMatchWeight(
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
AsmOperandInfo &info, int maIndex) const {
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
InlineAsm::ConstraintCodeVector *rCodes;
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
if (maIndex >= (int)info.multipleAlternatives.size())
rCodes = &info.Codes;
else
rCodes = &info.multipleAlternatives[maIndex].Codes;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
ConstraintWeight BestWeight = CW_Invalid;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
// Loop over the options, keeping track of the most general one.
Fixed pr20314-2.c failure, added E, F, p constraint letters. llvm-svn: 114490
2010-09-22 06:04:54 +08:00
for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
ConstraintWeight weight =
getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
if (weight > BestWeight)
BestWeight = weight;
}
return BestWeight;
}
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
/// Examine constraint type and operand type and determine a weight value.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
/// This object must already have been set up with the operand type
/// and the current alternative constraint selected.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
TargetLowering::ConstraintWeight
TargetLowering::getSingleConstraintMatchWeight(
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
AsmOperandInfo &info, const char *constraint) const {
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
ConstraintWeight weight = CW_Invalid;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
Value *CallOperandVal = info.CallOperandVal;
// If we don't have a value, we can't do a match,
// but allow it at the lowest weight.
if (CallOperandVal == NULL)
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
return CW_Default;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
// Look at the constraint type.
switch (*constraint) {
case 'i': // immediate integer.
case 'n': // immediate integer with a known value.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (isa<ConstantInt>(CallOperandVal))
weight = CW_Constant;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
break;
case 's': // non-explicit intregal immediate.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
if (isa<GlobalValue>(CallOperandVal))
weight = CW_Constant;
break;
case 'E': // immediate float if host format.
case 'F': // immediate float.
if (isa<ConstantFP>(CallOperandVal))
weight = CW_Constant;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
break;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
case '<': // memory operand with autodecrement.
case '>': // memory operand with autoincrement.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
case 'm': // memory operand.
case 'o': // offsettable memory operand
case 'V': // non-offsettable memory operand
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
weight = CW_Memory;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
break;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
case 'r': // general register.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
case 'g': // general register, memory operand or immediate integer.
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
// note: Clang converts "g" to "imr".
if (CallOperandVal->getType()->isIntegerTy())
weight = CW_Register;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
break;
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
case 'X': // any operand.
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
default:
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. llvm-svn: 117667
2010-10-30 01:29:13 +08:00
weight = CW_Default;
Added skeleton for inline asm multiple alternative constraint support. llvm-svn: 113766
2010-09-14 02:15:37 +08:00
break;
}
return weight;
}
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
/// ChooseConstraint - If there are multiple different constraints that we
/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
typo llvm-svn: 50316
2008-04-27 09:49:46 +08:00
/// This is somewhat tricky: constraints fall into four classes:
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
/// Other -> immediates and magic values
/// Register -> one specific register
/// RegisterClass -> a group of regs
/// Memory -> memory
/// Ideally, we would pick the most specific constraint possible: if we have
/// something that fits into a register, we would pick it. The problem here
/// is that if we have something that could either be in a register or in
/// memory that use of the register could cause selection of *other*
/// operands to fail: they might only succeed if we pick memory. Because of
/// this the heuristic we use is:
///
/// 1) If there is an 'other' constraint, and if the operand is valid for
/// that constraint, use it. This makes us take advantage of 'i'
/// constraints when available.
/// 2) Otherwise, pick the most general constraint present. This prefers
/// 'm' over 'r', for example.
///
static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
The hasMemory argument is irrelevant to how the argument for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
2010-06-26 05:55:36 +08:00
const TargetLowering &TLI,
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Op, SelectionDAG *DAG) {
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
unsigned BestIdx = 0;
TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
int BestGenerality = -1;
In asm's, output operands with matching input constraints have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
2010-06-29 06:09:45 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
// Loop over the options, keeping track of the most general one.
for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
TargetLowering::ConstraintType CType =
TLI.getConstraintType(OpInfo.Codes[i]);
In asm's, output operands with matching input constraints have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
2010-06-29 06:09:45 +08:00
Implement a signficant optimization for inline asm: When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
2008-04-27 08:37:18 +08:00
// If this is an 'other' constraint, see if the operand is valid for it.
// For example, on X86 we might have an 'rI' constraint. If the operand
// is an integer in the range [0..31] we want to use I (saving a load
// of a register), otherwise we must use 'r'.
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
if (CType == TargetLowering::C_Other && Op.getNode()) {
Implement a signficant optimization for inline asm: When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
2008-04-27 08:37:18 +08:00
assert(OpInfo.Codes[i].size() == 1 &&
"Unhandled multi-letter 'other' constraint");
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
std::vector<SDValue> ResultOps;
Have LowerOperandForConstraint handle multiple character constraints. Part of rdar://9119939 llvm-svn: 132510
2011-06-03 07:16:42 +08:00
TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
Implement a signficant optimization for inline asm: When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
2008-04-27 08:37:18 +08:00
ResultOps, *DAG);
if (!ResultOps.empty()) {
BestType = CType;
BestIdx = i;
break;
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
In asm's, output operands with matching input constraints have to be registers, per gcc documentation. This affects the logic for determining what "g" should lower to. PR 7393. A couple of existing testcases are affected. llvm-svn: 107079
2010-06-29 06:09:45 +08:00
// Things with matching constraints can only be registers, per gcc
// documentation. This mainly affects "g" constraints.
if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
continue;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
// This constraint letter is more general than the previous one, use it.
int Generality = getConstraintGenerality(CType);
if (Generality > BestGenerality) {
BestType = CType;
BestIdx = i;
BestGenerality = Generality;
}
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
OpInfo.ConstraintType = BestType;
}
/// ComputeConstraintToUse - Determines the constraint code and constraint
/// type to use for the specific AsmOperandInfo, setting
/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Implement a signficant optimization for inline asm: When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
2008-04-27 08:37:18 +08:00
void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
SDValue Op,
Implement a signficant optimization for inline asm: When choosing between constraints with multiple options, like "ir", test to see if we can use the 'i' constraint and go with that if possible. This produces more optimal ASM in all cases (sparing a register and an instruction to load it), and fixes inline asm like this: void test () { asm volatile (" %c0 %1 " : : "imr" (42), "imr"(14)); } Previously we would dump "42" into a memory location (which is ok for the 'm' constraint) which would cause a problem because the 'c' modifier is not valid on memory operands. Isn't it great how inline asm turns 'missed optimization' into 'compile failed'?? Incidentally, this was the todo in PowerPC/2007-04-24-InlineAsm-I-Modifier.ll Please do NOT pull this into Tak. llvm-svn: 50315
2008-04-27 08:37:18 +08:00
SelectionDAG *DAG) const {
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
// Single-letter constraints ('r') are very common.
if (OpInfo.Codes.size() == 1) {
OpInfo.ConstraintCode = OpInfo.Codes[0];
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
} else {
The hasMemory argument is irrelevant to how the argument for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
2010-06-26 05:55:36 +08:00
ChooseConstraint(OpInfo, *this, Op, DAG);
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
// 'X' matches anything.
if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
// Labels and constants are handled elsewhere ('X' is the only thing
Operand of asm("call") (the callee function) is represented as "X" constraint and "P" modifier on x86. Make this work. (Change may not be sufficient to fix it for non-Darwin, but I'm pretty sure it won't break anything.) gcc.apple/asm-block-32.c gcc.apple/asm-block-33.c llvm-svn: 74967
2009-07-08 07:26:33 +08:00
// that matches labels). For Functions, the type here is the type of
Move stripping of bitcasts in inline asm arguments to a place where it affects everything. Occurs only on calls AFAIK. llvm-svn: 76502
2009-07-21 07:27:39 +08:00
// the result, which is not what we want to look at; leave them alone.
Value *v = OpInfo.CallOperandVal;
Operand of asm("call") (the callee function) is represented as "X" constraint and "P" modifier on x86. Make this work. (Change may not be sufficient to fix it for non-Darwin, but I'm pretty sure it won't break anything.) gcc.apple/asm-block-32.c gcc.apple/asm-block-33.c llvm-svn: 74967
2009-07-08 07:26:33 +08:00
if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
OpInfo.CallOperandVal = v;
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
return;
Operand of asm("call") (the callee function) is represented as "X" constraint and "P" modifier on x86. Make this work. (Change may not be sufficient to fix it for non-Darwin, but I'm pretty sure it won't break anything.) gcc.apple/asm-block-32.c gcc.apple/asm-block-33.c llvm-svn: 74967
2009-07-08 07:26:33 +08:00
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move a bunch of inline asm code out of line. llvm-svn: 50313
2008-04-27 08:09:47 +08:00
// Otherwise, try to resolve it to something we know about by looking at
// the actual operand type.
if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
OpInfo.ConstraintCode = Repl;
OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
}
}
}
Add LSR hooks. llvm-svn: 26740
2006-03-14 07:18:16 +08:00
//===----------------------------------------------------------------------===//
// Loop Strength Reduction hooks
//===----------------------------------------------------------------------===//
add one addressing mode description hook to rule them all. llvm-svn: 35520
2007-03-31 07:14:50 +08:00
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
land David Blaikie's patch to de-constify Type, with a few tweaks. llvm-svn: 135375
2011-07-18 12:54:35 +08:00
Type *Ty) const {
add one addressing mode description hook to rule them all. llvm-svn: 35520
2007-03-31 07:14:50 +08:00
// The default implementation of this implements a conservative RISCy, r+r and
// r+i addr mode.
// Allows a sign-extended 16-bit immediate field.
if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
return false;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
add one addressing mode description hook to rule them all. llvm-svn: 35520
2007-03-31 07:14:50 +08:00
// No global is ever allowed as a base.
if (AM.BaseGV)
return false;
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
// Only support r+r,
add one addressing mode description hook to rule them all. llvm-svn: 35520
2007-03-31 07:14:50 +08:00
switch (AM.Scale) {
case 0: // "r+i" or just "i", depending on HasBaseReg.
break;
case 1:
if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
return false;
// Otherwise we have r+r or r+i.
break;
case 2:
if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
return false;
// Allow 2*r as r+r.
break;
}
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
add one addressing mode description hook to rule them all. llvm-svn: 35520
2007-03-31 07:14:50 +08:00
return true;
}
Emit a more efficient magic number multiplication for exact sdivs. We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building. struct foo { char x[24]; }; long bar(struct foo *a, struct foo *b) { return a-b; } is now compiled into movl 4(%esp), %eax subl 8(%esp), %eax sarl $3, %eax imull $-1431655765, %eax, %eax instead of movl 4(%esp), %eax subl 8(%esp), %eax movl $715827883, %ecx imull %ecx movl %edx, %eax shrl $31, %eax sarl $2, %edx addl %eax, %edx movl %edx, %eax llvm-svn: 134695
2011-07-08 18:31:30 +08:00
/// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
/// with the multiplicative inverse of the constant.
SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
SelectionDAG &DAG) const {
ConstantSDNode *C = cast<ConstantSDNode>(Op2);
APInt d = C->getAPIntValue();
assert(d != 0 && "Division by zero!");
// Shift the value upfront if it is even, so the LSB is one.
unsigned ShAmt = d.countTrailingZeros();
if (ShAmt) {
// TODO: For UDIV use SRL instead of SRA.
SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
d = d.ashr(ShAmt);
}
// Calculate the multiplicative inverse, using Newton's method.
APInt t, xn = d;
while ((t = d*xn) != 1)
xn *= APInt(d.getBitWidth(), 2) - t;
Op2 = DAG.getConstant(xn, Op1.getValueType());
return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
}
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
SDValue TargetLowering::
BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
Fix a coding style nit. llvm-svn: 169776
2012-12-11 06:00:20 +08:00
std::vector<SDNode*> *Created) const {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = N->getValueType(0);
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DebugLoc dl= N->getDebugLoc();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
// Check to see if we can do this.
Followup to r60283: optimize arbitrary width signed divisions as well as unsigned divisions. Same caveats as before. llvm-svn: 60284
2008-11-30 14:35:39 +08:00
// FIXME: We should be more aggressive here.
if (!isTypeLegal(VT))
return SDValue();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Followup to r60283: optimize arbitrary width signed divisions as well as unsigned divisions. Same caveats as before. llvm-svn: 60284
2008-11-30 14:35:39 +08:00
APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Move helper functions for optimizing division by constant into the APInt class. llvm-svn: 70488
2009-04-30 18:15:35 +08:00
APInt::ms magics = d.magic();
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
// Multiply the numerator (operand 0) by the magic value
Followup to r60283: optimize arbitrary width signed divisions as well as unsigned divisions. Same caveats as before. llvm-svn: 60284
2008-11-30 14:35:39 +08:00
// FIXME: We should support doing a MUL in a wider type
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue Q;
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
isOperationLegalOrCustom(ISD::MULHS, VT))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
2007-10-09 02:33:35 +08:00
DAG.getConstant(magics.m, VT));
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
2007-10-09 02:33:35 +08:00
N->getOperand(0),
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
DAG.getConstant(magics.m, VT)).getNode(), 1);
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
2007-10-09 02:33:35 +08:00
else
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
return SDValue(); // No mulhs or equvialent
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
// If d > 0 and m < 0, add the numerator
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
if (d.isStrictlyPositive() && magics.m.isNegative()) {
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(Q.getNode());
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
}
// If d < 0 and m > 0, subtract the numerator.
Followup to r60283: optimize arbitrary width signed divisions as well as unsigned divisions. Same caveats as before. llvm-svn: 60284
2008-11-30 14:35:39 +08:00
if (d.isNegative() && magics.m.isStrictlyPositive()) {
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(Q.getNode());
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
}
// Shift right algebraic if shift value is nonzero
if (magics.s > 0) {
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(Q.getNode());
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
}
// Extract the sign bit and add it to the quotient
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
SDValue T =
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
getShiftAmountTy(Q.getValueType())));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(T.getNode());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
}
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
SDValue TargetLowering::
BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
Fix a coding style nit. llvm-svn: 169776
2012-12-11 06:00:20 +08:00
std::vector<SDNode*> *Created) const {
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. llvm-svn: 78610
2009-08-11 06:56:29 +08:00
EVT VT = N->getValueType(0);
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
DebugLoc dl = N->getDebugLoc();
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
// Check to see if we can do this.
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
// FIXME: We should be more aggressive here.
if (!isTypeLegal(VT))
return SDValue();
// FIXME: We should use a narrower constant when the upper
// bits are known to be zero.
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
APInt::mu magics = N1C.magicu();
SDValue Q = N->getOperand(0);
// If the divisor is even, we can avoid using the expensive fixup by shifting
// the divided value upfront.
if (magics.a != 0 && !N1C[0]) {
unsigned Shift = N1C.countTrailingZeros();
Q = DAG.getNode(ISD::SRL, dl, VT, Q,
DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
if (Created)
Created->push_back(Q.getNode());
// Get magic number for the shifted divisor.
magics = N1C.lshr(Shift).magicu(Shift);
assert(magics.a == 0 && "Should use cheap fixup now");
}
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
// Multiply the numerator (operand 0) by the magic value
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
// FIXME: We should support doing a MUL in a wider type
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
isOperationLegalOrCustom(ISD::MULHU, VT))
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Don't introduce custom nodes after legalization in TargetLowering::BuildSDIV() and TargetLowering::BuildUDIV(). Fixes PR11283 llvm-svn: 143964
2011-11-08 01:09:05 +08:00
else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
DAG.getConstant(magics.m, VT)).getNode(), 1);
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
2007-10-09 02:33:35 +08:00
else
Rename SDOperand to SDValue. llvm-svn: 54128
2008-07-28 05:46:04 +08:00
return SDValue(); // No mulhu or equvialent
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(Q.getNode());
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (magics.a == 0) {
BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 llvm-svn: 127829
2011-03-18 04:39:14 +08:00
assert(magics.s < N1C.getBitWidth() &&
Fix for PR2164: allow transforming arbitrary-width unsigned divides into multiplies. Some more cleverness would be nice, though. It would be nice if we could do this transformation on illegal types. Also, we would prefer a narrower constant when possible so that we can use a narrower multiply, which can be cheaper. llvm-svn: 60283
2008-11-30 14:02:26 +08:00
"We shouldn't generate an undefined shift!");
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getNode(ISD::SRL, dl, VT, Q,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
} else {
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(NPQ.getNode());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(NPQ.getNode());
Propagation in TargetLowering. Includes passing a DL into SimplifySetCC which gets called elsewhere. llvm-svn: 63583
2009-02-03 08:47:48 +08:00
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
if (Created)
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics llvm-svn: 55504
2008-08-29 05:40:38 +08:00
Created->push_back(NPQ.getNode());
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. llvm-svn: 119990
2010-11-23 11:31:01 +08:00
return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. llvm-svn: 126518
2011-02-26 05:41:48 +08:00
DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Move this code to a common place llvm-svn: 28329
2006-05-17 01:42:15 +08:00
}
}