2019-01-16 23:43:53 +08:00
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VIGFX9,FUNC %s
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; FUNC-LABEL: {{^}}ds_ordered_swap:
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; GCN: s_mov_b32 m0, s0
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; VIGFX9-NEXT: s_nop 0
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; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v0 offset:4868 gds
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; GCN-NEXT: s_waitcnt expcnt(0) lgkmcnt(0)
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define amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value) {
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%val = call i32@llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
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%r = bitcast i32 %val to float
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ret float %r
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}
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; FUNC-LABEL: {{^}}ds_ordered_swap_conditional:
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[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
Summary:
- `dead-mi-elimination` assumes MIR in the SSA form and cannot be
arranged after phi elimination or DeSSA. It's enhanced to handle the
dead register definition by skipping use check on it. Once a register
def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after
`detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.
Reviewers: rampitec, qcolombet, sunfish
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
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; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]]
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2019-01-16 23:43:53 +08:00
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; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc
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; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0
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; GCN: s_cbranch_execz [[BB:BB._.]]
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; GCN: s_mov_b32 m0, s0
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; VIGFX9-NEXT: s_nop 0
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[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
Summary:
- `dead-mi-elimination` assumes MIR in the SSA form and cannot be
arranged after phi elimination or DeSSA. It's enhanced to handle the
dead register definition by skipping use check on it. Once a register
def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after
`detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.
Reviewers: rampitec, qcolombet, sunfish
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D72709
2020-01-08 23:50:23 +08:00
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; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds
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2019-01-16 23:43:53 +08:00
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; GCN-NEXT: [[BB]]:
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; // Wait for expcnt(0) before modifying EXEC
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; GCN-NEXT: s_waitcnt expcnt(0)
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; GCN-NEXT: s_or_b64 exec, exec, s[[SAVED]]
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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define amdgpu_cs float @ds_ordered_swap_conditional(i32 addrspace(2)* inreg %gds, i32 %value) {
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entry:
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%c = icmp ne i32 %value, 0
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br i1 %c, label %if-true, label %endif
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if-true:
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%val = call i32@llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* %gds, i32 %value, i32 0, i32 0, i1 false, i32 1, i1 true, i1 true)
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br label %endif
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endif:
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%v = phi i32 [ %val, %if-true ], [ undef, %entry ]
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%r = bitcast i32 %v to float
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ret float %r
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}
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declare i32 @llvm.amdgcn.ds.ordered.swap(i32 addrspace(2)* nocapture, i32, i32, i32, i1, i32, i1, i1)
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