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llvm-project/llvm/test/CodeGen/X86/sse-align-2.ll

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llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. llvm-svn: 171084
2012-12-26 11:19:30 +08:00
; RUN: llc < %s -march=x86-64 -mcpu=penryn | FileCheck %s
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015
2007-07-19 04:23:34 +08:00
Add nounwind. llvm-svn: 50837
2008-05-08 06:59:08 +08:00
define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind {
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015
2007-07-19 04:23:34 +08:00
%t = load <4 x float>* %p, align 4
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%z = fmul <4 x float> %t, %x
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015
2007-07-19 04:23:34 +08:00
ret <4 x float> %z
}
llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. llvm-svn: 171084
2012-12-26 11:19:30 +08:00
; CHECK: foo:
; CHECK: movups
; CHECK: ret
Add nounwind. llvm-svn: 50837
2008-05-08 06:59:08 +08:00
define <2 x double> @bar(<2 x double>* %p, <2 x double> %x) nounwind {
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015
2007-07-19 04:23:34 +08:00
%t = load <2 x double>* %p, align 8
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%z = fmul <2 x double> %t, %x
Implement initial memory alignment awareness for SSE instructions. Vector loads and stores that have a specified alignment of less than 16 bytes now use instructions that support misaligned memory references. llvm-svn: 40015
2007-07-19 04:23:34 +08:00
ret <2 x double> %z
}
llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. llvm-svn: 171084
2012-12-26 11:19:30 +08:00
; CHECK: bar:
; CHECK: movupd
; CHECK: ret