2016-11-15 17:51:02 +08:00
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//===- SubtargetFeatureInfo.cpp - Helpers for subtarget features ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SubtargetFeatureInfo.h"
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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#include "Types.h"
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2016-11-15 17:51:02 +08:00
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#include "llvm/TableGen/Record.h"
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#include <map>
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using namespace llvm;
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2017-01-28 10:47:46 +08:00
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void SubtargetFeatureInfo::dump() const {
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errs() << getEnumName() << " " << Index << "\n" << *TheDef;
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2016-11-15 17:51:02 +08:00
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}
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2017-01-28 10:47:46 +08:00
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#endif
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2016-11-15 17:51:02 +08:00
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std::vector<std::pair<Record *, SubtargetFeatureInfo>>
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SubtargetFeatureInfo::getAll(const RecordKeeper &Records) {
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std::vector<std::pair<Record *, SubtargetFeatureInfo>> SubtargetFeatures;
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std::vector<Record *> AllPredicates =
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Records.getAllDerivedDefinitions("Predicate");
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for (Record *Pred : AllPredicates) {
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// Ignore predicates that are not intended for the assembler.
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//
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// The "AssemblerMatcherPredicate" string should be promoted to an argument
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// if we re-use the machinery for non-assembler purposes in future.
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if (!Pred->getValueAsBit("AssemblerMatcherPredicate"))
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continue;
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if (Pred->getName().empty())
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PrintFatalError(Pred->getLoc(), "Predicate has no name!");
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SubtargetFeatures.emplace_back(
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Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size()));
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}
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return SubtargetFeatures;
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}
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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void SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
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std::map<Record *, SubtargetFeatureInfo, LessRecordByID> &SubtargetFeatures,
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raw_ostream &OS) {
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OS << "// Flags for subtarget features that participate in "
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<< "instruction matching.\n";
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OS << "enum SubtargetFeatureFlag : "
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<< getMinimalTypeForEnumBitfield(SubtargetFeatures.size()) << " {\n";
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for (const auto &SF : SubtargetFeatures) {
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const SubtargetFeatureInfo &SFI = SF.second;
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OS << " " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
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}
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OS << " Feature_None = 0\n";
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OS << "};\n\n";
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}
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void SubtargetFeatureInfo::emitNameTable(
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std::map<Record *, SubtargetFeatureInfo, LessRecordByID> &SubtargetFeatures,
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raw_ostream &OS) {
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2017-03-07 05:26:49 +08:00
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// Need to sort the name table so that lookup by the log of the enum value
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// gives the proper name. More specifically, for a feature of value 1<<n,
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// SubtargetFeatureNames[n] should be the name of the feature.
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uint64_t IndexUB = 0;
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for (const auto &SF : SubtargetFeatures)
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if (IndexUB <= SF.second.Index)
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IndexUB = SF.second.Index+1;
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std::vector<std::string> Names;
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if (IndexUB > 0)
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Names.resize(IndexUB);
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for (const auto &SF : SubtargetFeatures)
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Names[SF.second.Index] = SF.second.getEnumName();
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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OS << "static const char *SubtargetFeatureNames[] = {\n";
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2017-03-07 05:26:49 +08:00
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for (uint64_t I = 0; I < IndexUB; ++I)
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OS << " \"" << Names[I] << "\",\n";
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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// A small number of targets have no predicates. Null terminate the array to
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// avoid a zero-length array.
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OS << " nullptr\n"
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<< "};\n\n";
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}
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2016-11-15 17:51:02 +08:00
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void SubtargetFeatureInfo::emitComputeAvailableFeatures(
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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StringRef TargetName, StringRef ClassName, StringRef FuncName,
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2016-11-15 17:51:02 +08:00
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std::map<Record *, SubtargetFeatureInfo, LessRecordByID> &SubtargetFeatures,
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raw_ostream &OS) {
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OS << "uint64_t " << TargetName << ClassName << "::\n"
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Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.
Summary:
* ARM is omitted from this patch because this check appears to expose bugs in this target.
* Mips is omitted from this patch because this check either detects bugs or deliberate
emission of instructions that don't satisfy their predicates. One deliberate
use is the SYNC instruction where the version with an operand is correctly
defined as requiring MIPS32 while the version without an operand is defined
as an alias of 'SYNC 0' and requires MIPS2.
* X86 is omitted from this patch because it doesn't use the tablegen-erated
MCCodeEmitter infrastructure.
Patches for ARM and Mips will follow.
Depends on D25617
Reviewers: tstellarAMD, jmolloy
Subscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D25618
llvm-svn: 287439
2016-11-19 21:05:44 +08:00
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<< FuncName << "(const FeatureBitset& FB) const {\n";
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2016-11-15 17:51:02 +08:00
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OS << " uint64_t Features = 0;\n";
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for (const auto &SF : SubtargetFeatures) {
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const SubtargetFeatureInfo &SFI = SF.second;
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OS << " if (";
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std::string CondStorage =
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SFI.TheDef->getValueAsString("AssemblerCondString");
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StringRef Conds = CondStorage;
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std::pair<StringRef, StringRef> Comma = Conds.split(',');
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bool First = true;
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do {
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if (!First)
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OS << " && ";
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bool Neg = false;
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StringRef Cond = Comma.first;
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if (Cond[0] == '!') {
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Neg = true;
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Cond = Cond.substr(1);
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}
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OS << "(";
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if (Neg)
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OS << "!";
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OS << "FB[" << TargetName << "::" << Cond << "])";
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if (Comma.second.empty())
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break;
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First = false;
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Comma = Comma.second.split(',');
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} while (true);
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OS << ")\n";
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OS << " Features |= " << SFI.getEnumName() << ";\n";
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}
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OS << " return Features;\n";
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OS << "}\n\n";
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}
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