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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

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GlobalISel: freeze reserved regs after IRTranslator. We can freeze the registers after the MachineFrameInfo has been configured (by telling it about calls, inline asm, ...). This doesn't happen at all yet, but will be part of IR translation. Fixes -verify-machineinstrs assertion. llvm-svn: 275221
2016-07-13 06:23:42 +08:00
; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
[AArch64][GlobalISel] Add a test case for the IRTranslator. llvm-svn: 262898
2016-03-08 09:48:08 +08:00
; REQUIRES: global-isel
; This file checks that the translation from llvm IR to generic MachineInstr
; is correct.
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-apple-ios"
; Tests for add.
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: addi64
[AArch64][GlobalISel] Add a test case for the IRTranslator. llvm-svn: 262898
2016-03-08 09:48:08 +08:00
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD s64 [[ARG1]], [[ARG2]]
[AArch64][GlobalISel] Add a test case for the IRTranslator. llvm-svn: 262898
2016-03-08 09:48:08 +08:00
; CHECK-NEXT: %x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @addi64(i64 %arg1, i64 %arg2) {
%res = add i64 %arg1, %arg2
ret i64 %res
}
[IRTranslator] Translate unconditional branches. llvm-svn: 263265
2016-03-12 01:28:03 +08:00
GlobalISel: implement alloca instruction llvm-svn: 276433
2016-07-23 00:59:52 +08:00
; Tests for alloca
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: allocai64
GlobalISel: implement alloca instruction llvm-svn: 276433
2016-07-23 00:59:52 +08:00
; CHECK: stack:
; CHECK-NEXT: - { id: 0, name: ptr1, offset: 0, size: 8, alignment: 8 }
; CHECK-NEXT: - { id: 1, name: ptr2, offset: 0, size: 8, alignment: 1 }
; CHECK-NEXT: - { id: 2, name: ptr3, offset: 0, size: 128, alignment: 8 }
GlobalISel: support zero-sized allocas All allocas must be at least 1 byte at the MachineIR level so we allocate just one byte. llvm-svn: 276897
2016-07-28 01:47:54 +08:00
; CHECK-NEXT: - { id: 3, name: ptr4, offset: 0, size: 1, alignment: 8 }
GlobalISel: add correct operand type to G_FRAME_INDEX instrs. Frame indices should use "addFrameIndex", not "addImm". llvm-svn: 276775
2016-07-27 01:42:40 +08:00
; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 %stack.0.ptr1
; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 %stack.1.ptr2
; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 %stack.2.ptr3
GlobalISel: support zero-sized allocas All allocas must be at least 1 byte at the MachineIR level so we allocate just one byte. llvm-svn: 276897
2016-07-28 01:47:54 +08:00
; CHECK: %{{[0-9]+}}(64) = G_FRAME_INDEX p0 %stack.3.ptr4
GlobalISel: implement alloca instruction llvm-svn: 276433
2016-07-23 00:59:52 +08:00
define void @allocai64() {
%ptr1 = alloca i64
%ptr2 = alloca i64, align 1
%ptr3 = alloca i64, i32 16
GlobalISel: support zero-sized allocas All allocas must be at least 1 byte at the MachineIR level so we allocate just one byte. llvm-svn: 276897
2016-07-28 01:47:54 +08:00
%ptr4 = alloca [0 x i64]
GlobalISel: implement alloca instruction llvm-svn: 276433
2016-07-23 00:59:52 +08:00
ret void
}
[IRTranslator] Translate unconditional branches. llvm-svn: 263265
2016-03-12 01:28:03 +08:00
; Tests for br.
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: uncondbr
[IRTranslator] Translate unconditional branches. llvm-svn: 263265
2016-03-12 01:28:03 +08:00
; CHECK: body:
;
; Entry basic block.
; CHECK: {{[0-9a-zA-Z._-]+}}:
;
; Make sure we have one successor and only one.
; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 100.00%)
;
; Check that we emit the correct branch.
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK: G_BR unsized %[[END]]
[IRTranslator] Translate unconditional branches. llvm-svn: 263265
2016-03-12 01:28:03 +08:00
;
; Check that end contains the return instruction.
; CHECK: [[END]]:
; CHECK-NEXT: RET_ReallyLR
define void @uncondbr() {
br label %end
end:
ret void
}
[IRTranslator] Support the translation of or. Now or instructions get translated into G_OR. llvm-svn: 272433
2016-06-11 04:50:35 +08:00
; Tests for or.
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: ori64
[IRTranslator] Support the translation of or. Now or instructions get translated into G_OR. llvm-svn: 272433
2016-06-11 04:50:35 +08:00
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR s64 [[ARG1]], [[ARG2]]
[IRTranslator] Support the translation of or. Now or instructions get translated into G_OR. llvm-svn: 272433
2016-06-11 04:50:35 +08:00
; CHECK-NEXT: %x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @ori64(i64 %arg1, i64 %arg2) {
%res = or i64 %arg1, %arg2
ret i64 %res
}
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: ori32
[IRTranslator] Support the translation of or. Now or instructions get translated into G_OR. llvm-svn: 272433
2016-06-11 04:50:35 +08:00
; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR s32 [[ARG1]], [[ARG2]]
[IRTranslator] Support the translation of or. Now or instructions get translated into G_OR. llvm-svn: 272433
2016-06-11 04:50:35 +08:00
; CHECK-NEXT: %w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %w0
define i32 @ori32(i32 %arg1, i32 %arg2) {
%res = or i32 %arg1, %arg2
ret i32 %res
}
[IRTranslator] Add G_AND opcode. This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
2016-07-21 23:50:42 +08:00
; Tests for and.
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: andi64
[IRTranslator] Add G_AND opcode. This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
2016-07-21 23:50:42 +08:00
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_AND s64 [[ARG1]], [[ARG2]]
[IRTranslator] Add G_AND opcode. This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
2016-07-21 23:50:42 +08:00
; CHECK-NEXT: %x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @andi64(i64 %arg1, i64 %arg2) {
%res = and i64 %arg1, %arg2
ret i64 %res
}
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: andi32
[IRTranslator] Add G_AND opcode. This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
2016-07-21 23:50:42 +08:00
; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_AND s32 [[ARG1]], [[ARG2]]
[IRTranslator] Add G_AND opcode. This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
2016-07-21 23:50:42 +08:00
; CHECK-NEXT: %w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %w0
define i32 @andi32(i32 %arg1, i32 %arg2) {
%res = and i32 %arg1, %arg2
ret i32 %res
}
[IRTranslator] Add G_SUB opcode. This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
2016-07-22 01:26:50 +08:00
; Tests for sub.
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: subi64
[IRTranslator] Add G_SUB opcode. This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
2016-07-22 01:26:50 +08:00
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_SUB s64 [[ARG1]], [[ARG2]]
[IRTranslator] Add G_SUB opcode. This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
2016-07-22 01:26:50 +08:00
; CHECK-NEXT: %x0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %x0
define i64 @subi64(i64 %arg1, i64 %arg2) {
%res = sub i64 %arg1, %arg2
ret i64 %res
}
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: subi32
[IRTranslator] Add G_SUB opcode. This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
2016-07-22 01:26:50 +08:00
; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
GlobalISel: omit braces on MachineInstr types when there's only one. Tidies up the representation a bit in the common case. llvm-svn: 276772
2016-07-27 01:28:01 +08:00
; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_SUB s32 [[ARG1]], [[ARG2]]
[IRTranslator] Add G_SUB opcode. This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
2016-07-22 01:26:50 +08:00
; CHECK-NEXT: %w0 = COPY [[RES]]
; CHECK-NEXT: RET_ReallyLR implicit %w0
define i32 @subi32(i32 %arg1, i32 %arg2) {
%res = sub i32 %arg1, %arg2
ret i32 %res
}
GlobalISel: add generic casts to IRTranslator This adds LLVM's 3 main cast instructions (inttoptr, ptrtoint, bitcast) to the IRTranslator. The first two are direct translations (with 2 MachineInstr types each). Since LLT discards information, a bitcast might become trivial and we emit a COPY in those cases instead. llvm-svn: 276690
2016-07-26 05:01:29 +08:00
; CHECK-LABEL: name: ptrtoint
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK: [[RES:%[0-9]+]](64) = G_PTRTOINT { s64, p0 } [[ARG1]]
; CHECK: %x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit %x0
define i64 @ptrtoint(i64* %a) {
%val = ptrtoint i64* %a to i64
ret i64 %val
}
; CHECK-LABEL: name: inttoptr
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK: [[RES:%[0-9]+]](64) = G_INTTOPTR { p0, s64 } [[ARG1]]
; CHECK: %x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit %x0
define i64* @inttoptr(i64 %a) {
%val = inttoptr i64 %a to i64*
ret i64* %val
}
; CHECK-LABEL: name: trivial_bitcast
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK: [[RES:%[0-9]+]](64) = COPY [[ARG1]]
; CHECK: %x0 = COPY [[RES]]
; CHECK: RET_ReallyLR implicit %x0
define i64* @trivial_bitcast(i8* %a) {
%val = bitcast i8* %a to i64*
ret i64* %val
}
; CHECK-LABEL: name: bitcast
; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
; CHECK: [[RES1:%[0-9]+]](64) = G_BITCAST { <2 x s32>, s64 } [[ARG1]]
; CHECK: [[RES2:%[0-9]+]](64) = G_BITCAST { s64, <2 x s32> } [[RES1]]
; CHECK: %x0 = COPY [[RES2]]
; CHECK: RET_ReallyLR implicit %x0
define i64 @bitcast(i64 %a) {
%res1 = bitcast i64 %a to <2 x i32>
%res2 = bitcast <2 x i32> %res1 to i64
ret i64 %res2
}
GlobalISel: add generic load and store instructions. Pretty straightforward, the only oddity is the MachineMemOperand (which it's surprisingly difficult to share code for). llvm-svn: 276799
2016-07-27 04:23:26 +08:00
; CHECK-LABEL: name: load
; CHECK: [[ADDR:%[0-9]+]](64) = COPY %x0
; CHECK: [[ADDR42:%[0-9]+]](64) = COPY %x1
; CHECK: [[VAL1:%[0-9]+]](64) = G_LOAD { s64, p0 } [[ADDR]] :: (load 8 from %ir.addr, align 16)
; CHECK: [[VAL2:%[0-9]+]](64) = G_LOAD { s64, p42 } [[ADDR42]] :: (load 8 from %ir.addr42)
; CHECK: [[SUM:%.*]](64) = G_ADD s64 [[VAL1]], [[VAL2]]
; CHECK: %x0 = COPY [[SUM]]
; CHECK: RET_ReallyLR implicit %x0
define i64 @load(i64* %addr, i64 addrspace(42)* %addr42) {
%val1 = load i64, i64* %addr, align 16
%val2 = load i64, i64 addrspace(42)* %addr42
%sum = add i64 %val1, %val2
ret i64 %sum
}
; CHECK-LABEL: name: store
; CHECK: [[ADDR:%[0-9]+]](64) = COPY %x0
; CHECK: [[ADDR42:%[0-9]+]](64) = COPY %x1
; CHECK: [[VAL1:%[0-9]+]](64) = COPY %x2
; CHECK: [[VAL2:%[0-9]+]](64) = COPY %x3
; CHECK: G_STORE { s64, p0 } [[VAL1]], [[ADDR]] :: (store 8 into %ir.addr, align 16)
; CHECK: G_STORE { s64, p42 } [[VAL2]], [[ADDR42]] :: (store 8 into %ir.addr42)
; CHECK: RET_ReallyLR
define void @store(i64* %addr, i64 addrspace(42)* %addr42, i64 %val1, i64 %val2) {
store i64 %val1, i64* %addr, align 16
store i64 %val2, i64 addrspace(42)* %addr42
%sum = add i64 %val1, %val2
ret void
}