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llvm-project/llvm/test/CodeGen/ARM/inlineasm-switch-mode.ll

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Don't use "llc -filetype=obj" now that the codepath is the same. r200011 remove the special codepaths in MC for inline asm, so we can now test all the logic with just llc + llvm-mc. llvm-svn: 200013
2014-01-24 23:59:50 +08:00
;RUN: llc -mtriple=thumbv7-linux-gnueabi < %s | llvm-mc -triple=thumbv7-linux-gnueabi -filetype=obj > %t
Fix inline assembly that switches between ARM and Thumb modes This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
2014-01-23 02:32:35 +08:00
; Two pass decoding needed because llvm-objdump does not respect mapping symbols
Revert r265817 lld tests need to be addressed. llvm-svn: 265822
2016-04-09 02:15:37 +08:00
;RUN: llvm-objdump -triple=armv7 -d %t | FileCheck %s --check-prefix=ARM
;RUN: llvm-objdump -triple=thumbv7 -d %t | FileCheck %s --check-prefix=THUMB
Fix inline assembly that switches between ARM and Thumb modes This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
2014-01-23 02:32:35 +08:00
define hidden i32 @bah(i8* %start) #0 align 2 {
%1 = ptrtoint i8* %start to i32
%2 = tail call i32 asm sideeffect "@ Enter ARM Mode \0A\09adr r3, 1f \0A\09bx r3 \0A\09.align 2 \0A\09.code 32 \0A1: push {r7} \0A\09mov r7, $4 \0A\09svc 0x0 \0A\09pop {r7} \0A\09@ Enter THUMB Mode\0A\09adr r3, 2f+1 \0A\09bx r3 \0A\09.code 16 \0A2: \0A\09", "={r0},{r0},{r1},{r2},r,~{r3}"(i32 %1, i32 %1, i32 0, i32 983042) #3
%3 = add i32 %1, 1
ret i32 %3
}
; ARM: $a
; ARM-NEXT: 04 70 2d e5 str r7, [sp, #-4]!
; ARM: $t
; ARM-NEXT: 48 1c
[llvm-objdump] Use the COFF export table for additional symbols Most linked executables do not have a symbol table in COFF. However, it is pretty typical to have some export entries. Use those entries to inform the disassembler about potential function definitions and call targets. llvm-svn: 253429
2015-11-18 10:49:19 +08:00
; THUMB: $a{{.*}}:
Fix inline assembly that switches between ARM and Thumb modes This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
2014-01-23 02:32:35 +08:00
; THUMB-NEXT: 04 70
; THUMB-NEXT: 2d e5
[llvm-objdump] Use the COFF export table for additional symbols Most linked executables do not have a symbol table in COFF. However, it is pretty typical to have some export entries. Use those entries to inform the disassembler about potential function definitions and call targets. llvm-svn: 253429
2015-11-18 10:49:19 +08:00
; THUMB: $t{{.*}}:
Fix inline assembly that switches between ARM and Thumb modes This patch restores the ARM mode if the user's inline assembly does not. In the object streamer, it ensures that instructions following the inline assembly are encoded correctly and that correct mapping symbols are emitted. For the asm streamer, it emits a .arm or .thumb directive. This patch does not ensure that the inline assembly contains the ADR instruction to switch modes at runtime. The problem we need to solve is code like this: int foo(int a, int b) { int r = a + b; asm volatile( ".align 2 \n" ".arm \n" "add r0,r0,r0 \n" : : "r"(r)); return r+1; } If we compile this function in thumb mode then the inline assembly will switch to arm mode. We need to make sure that we switch back to thumb mode after emitting the inline assembly or we will incorrectly encode the instructions that follow (i.e. the assembly instructions for return r+1). Based on patch by David Peixotto Change-Id: Ib57f6d2d78a22afad5de8693fba6230ff56ba48b llvm-svn: 199818
2014-01-23 02:32:35 +08:00
; THUMB-NEXT: 48 1c adds r0, r1, #1