maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/ARM/vext.ll

356 lines
13 KiB
LLVM
Raw Normal View History

[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[ARM][AArch64] Turn on by default interleaved access lowering Summary: Interleaved access lowering removes a memory operation and a sequence of vector shuffles and replaces it with a series of memory operations. This should be always beneficial. This pass in only enabled on ARM/AArch64. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D12145 llvm-svn: 246540
2015-09-01 19:12:35 +08:00
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
Add support for Neon VEXT (vector extract) shuffles. This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
2009-08-20 01:03:43 +08:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextd:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vext.8 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
Add support for Neon VEXT (vector extract) shuffles. This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
2009-08-20 01:03:43 +08:00
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x i8> %tmp3
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextRd:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vext.8 d16, d17, d16, #5
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
Add support for Neon VEXT (vector extract) shuffles. This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
2009-08-20 01:03:43 +08:00
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
ret <8 x i8> %tmp3
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextq:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vext.8 q8, q9, q8, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
Add support for Neon VEXT (vector extract) shuffles. This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
2009-08-20 01:03:43 +08:00
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
ret <16 x i8> %tmp3
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextRq:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vext.8 q8, q9, q8, #7
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
Add support for Neon VEXT (vector extract) shuffles. This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
2009-08-20 01:03:43 +08:00
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
ret <16 x i8> %tmp3
}
Add some tests for vext.16 and vext.32. llvm-svn: 79638
2009-08-22 00:35:24 +08:00
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextd16:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vext.16 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
Add some tests for vext.16 and vext.32. llvm-svn: 79638
2009-08-22 00:35:24 +08:00
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
ret <4 x i16> %tmp3
}
Remove arm_apcscc from the test files. It is the default and doing this matches what llvm-gcc and clang now produce. llvm-svn: 106221
2010-06-17 23:18:27 +08:00
define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextq32:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vext.32 q8, q9, q8, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
Add some tests for vext.16 and vext.32. llvm-svn: 79638
2009-08-22 00:35:24 +08:00
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
ret <4 x i32> %tmp3
}
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
; Undef shuffle indices should not prevent matching to VEXT:
define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextd_undef:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vext.8 d16, d17, d16, #3
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
ret <8 x i8> %tmp3
}
define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextRq_undef:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vext.8 q8, q9, q8, #7
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
ret <16 x i8> %tmp3
}
Vext Lowering was missing opportunities llvm-svn: 167318
2012-11-03 05:32:17 +08:00
define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextq_undef_op2:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vext.8 q8, q8, q8, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
Vext Lowering was missing opportunities llvm-svn: 167318
2012-11-03 05:32:17 +08:00
entry:
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
ret <16 x i8> %tmp1
}
define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextd_undef_op2:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vext.8 d16, d16, d16, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
Vext Lowering was missing opportunities llvm-svn: 167318
2012-11-03 05:32:17 +08:00
entry:
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
ret <8 x i8> %tmp1
}
define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextq_undef_op2_undef:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vmov d17, r2, r3
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vext.8 q8, q8, q8, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
Vext Lowering was missing opportunities llvm-svn: 167318
2012-11-03 05:32:17 +08:00
entry:
%tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
ret <16 x i8> %tmp1
}
define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_vextd_undef_op2_undef:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vmov d16, r0, r1
; CHECK-NEXT: vext.8 d16, d16, d16, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
Vext Lowering was missing opportunities llvm-svn: 167318
2012-11-03 05:32:17 +08:00
entry:
%tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
ret <8 x i8> %tmp1
}
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
; Tests for ReconstructShuffle function. Indices have to be carefully
; chosen to reach lowering phase as a BUILD_VECTOR.
; One vector needs vext, the other can be handled by extract_subvector
; Also checks interleaving of sources is handled correctly.
; Essence: a vext is used on %A and something saner than stack load/store for final result.
define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_interleaved:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vext.16 d16, d16, d17, #3
; CHECK-NEXT: vorr d17, d16, d16
; CHECK-NEXT: vuzp.16 d16, d17
; CHECK-NEXT: vzip.16 d16, d18
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9>
ret <4 x i16> %tmp3
}
; An undef in the shuffle list should still be optimizable
define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_undef:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vzip.16 d19, d16
; CHECK-NEXT: vmov r0, r1, d19
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
ret <4 x i16> %tmp3
}
; We should ignore a build_vector with more than two sources.
; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
ARM: Improve codegen for generic vselect. Fall back to by-element insert rather than building it up on the stack. rdar://14351991 llvm-svn: 185846
2013-07-09 02:18:52 +08:00
; Try to look for fallback to by-element inserts.
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_multisource:
; CHECK: @ BB#0:
; CHECK-NEXT: mov r1, r0
[ARM] Implement isExtractSubvectorCheap. See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap. Essentially the same considerations apply to ARM. This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles. See https://reviews.llvm.org/D27779 for followup fix. Differential Revision: https://reviews.llvm.org/D27774 llvm-svn: 290198
2016-12-21 04:05:07 +08:00
; CHECK-NEXT: add r2, r0, #32
; CHECK-NEXT: add r0, r0, #48
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-NEXT: vld1.16 {d16, d17}, [r1:128]!
; CHECK-NEXT: vld1.64 {d20, d21}, [r2:128]
[ARM] Implement isExtractSubvectorCheap. See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap. Essentially the same considerations apply to ARM. This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles. See https://reviews.llvm.org/D27779 for followup fix. Differential Revision: https://reviews.llvm.org/D27774 llvm-svn: 290198
2016-12-21 04:05:07 +08:00
; CHECK-NEXT: vld1.64 {d18, d19}, [r0:128]
; CHECK-NEXT: vld1.64 {d22, d23}, [r1:128]
; CHECK-NEXT: vorr d24, d20, d20
; CHECK-NEXT: vzip.16 d24, d18
; CHECK-NEXT: vext.16 d18, d20, d24, #2
; CHECK-NEXT: vtrn.16 q8, q11
; CHECK-NEXT: vext.16 d16, d18, d16, #2
; CHECK-NEXT: vext.16 d16, d16, d16, #2
; CHECK-NEXT: vmov r0, r1, d16
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <32 x i16>, <32 x i16>* %B
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
%tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <4 x i32> <i32 0, i32 8, i32 16, i32 24>
ret <4 x i16> %tmp2
}
; We don't handle shuffles using more than half of a 128-bit vector.
ARM: Improve codegen for generic vselect. Fall back to by-element insert rather than building it up on the stack. rdar://14351991 llvm-svn: 185846
2013-07-09 02:18:52 +08:00
; Again, test for fallback to by-element inserts.
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_largespan:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
[ARM] Implement isExtractSubvectorCheap. See https://reviews.llvm.org/D6678 for the history of isExtractSubvectorCheap. Essentially the same considerations apply to ARM. This temporarily breaks the formation of vpadd/vpaddl in certain cases; AddCombineToVPADDL essentially assumes that we won't form VUZP shuffles. See https://reviews.llvm.org/D27779 for followup fix. Differential Revision: https://reviews.llvm.org/D27774 llvm-svn: 290198
2016-12-21 04:05:07 +08:00
; CHECK-NEXT: vorr d18, d16, d16
; CHECK-NEXT: vuzp.16 d18, d17
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-NEXT: vmov r0, r1, d18
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %B
Lower some BUILD_VECTORS using VEXT+shuffle. Patch by Tim Northover. llvm-svn: 123035
2011-01-08 05:37:30 +08:00
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i16> %tmp2
}
Some minor cleanups based on feedback. llvm-svn: 127694
2011-03-16 04:47:26 +08:00
; The actual shuffle code only handles some cases, make sure we check
; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
; lowering loop can result otherwise).
[ARM] Split 128-bit vectors in BUILD_VECTOR lowering Given that INSERT_VECTOR_ELT operates on D registers anyway, combining 64-bit vectors into a 128-bit vector is basically free. Therefore, try to split BUILD_VECTOR nodes before giving up and lowering them to a series of INSERT_VECTOR_ELT instructions. Sometimes this allows dramatically better lowerings; see testcases for examples. Inspired by similar code in the x86 backend for AVX. Differential Revision: https://reviews.llvm.org/D27624 llvm-svn: 289706
2016-12-15 04:44:38 +08:00
; (There are probably better ways to lower this shuffle, but it's not
; really important.)
Some minor cleanups based on feedback. llvm-svn: 127694
2011-03-16 04:47:26 +08:00
define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_illegal:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vmov.u16 r1, d16[0]
; CHECK-NEXT: vmov.u16 r0, d17[3]
; CHECK-NEXT: vorr d22, d16, d16
; CHECK-NEXT: vorr d23, d16, d16
; CHECK-NEXT: vmov.16 d20[0], r1
; CHECK-NEXT: vuzp.16 d22, d23
; CHECK-NEXT: vmov.u16 r1, d17[1]
; CHECK-NEXT: vmov.16 d20[1], r0
; CHECK-NEXT: vuzp.16 d22, d18
; CHECK-NEXT: vmov.16 d20[2], r1
; CHECK-NEXT: vmov.u16 r0, d19[1]
; CHECK-NEXT: vext.16 d21, d16, d18, #3
; CHECK-NEXT: vmov.16 d20[3], r0
; CHECK-NEXT: vmov r0, r1, d20
; CHECK-NEXT: vmov r2, r3, d21
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
Some minor cleanups based on feedback. llvm-svn: 127694
2011-03-16 04:47:26 +08:00
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
ret <8 x i16> %tmp3
}
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. llvm-svn: 142022
2011-10-15 07:58:49 +08:00
; PR11129
; Make sure this doesn't crash
define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test_elem_mismatch:
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: vmov.32 r2, d16[0]
; CHECK-NEXT: vmov.32 r0, d17[0]
; CHECK-NEXT: vmov.16 d16[0], r2
; CHECK-NEXT: vmov.16 d16[1], r0
; CHECK-NEXT: vstr d16, [r1]
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp0 = load <2 x i64>, <2 x i64>* %src, align 16
Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. llvm-svn: 142022
2011-10-15 07:58:49 +08:00
%tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
%tmp2 = extractelement <4 x i32> %tmp1, i32 0
%tmp3 = extractelement <4 x i32> %tmp1, i32 2
%tmp4 = trunc i32 %tmp2 to i16
%tmp5 = trunc i32 %tmp3 to i16
%tmp6 = insertelement <4 x i16> undef, i16 %tmp4, i32 0
%tmp7 = insertelement <4 x i16> %tmp6, i16 %tmp5, i32 1
store <4 x i16> %tmp7, <4 x i16>* %dest, align 4
ret void
}
[ARM] - Fix lowering of shufflevectors in AArch32 Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 llvm-svn: 243103
2015-07-24 17:57:05 +08:00
define <4 x i32> @test_reverse_and_extract(<2 x i32>* %A) {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_reverse_and_extract:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vrev64.32 q9, q8
; CHECK-NEXT: vext.32 q8, q8, q9, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[ARM] - Fix lowering of shufflevectors in AArch32 Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 llvm-svn: 243103
2015-07-24 17:57:05 +08:00
entry:
%tmp1 = load <2 x i32>, <2 x i32>* %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 0>
ret <4 x i32> %0
}
define <4 x i32> @test_dup_and_extract(<2 x i32>* %A) {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_dup_and_extract:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vdup.32 q9, d16[0]
; CHECK-NEXT: vext.32 q8, q9, q8, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[ARM] - Fix lowering of shufflevectors in AArch32 Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 llvm-svn: 243103
2015-07-24 17:57:05 +08:00
entry:
%tmp1 = load <2 x i32>, <2 x i32>* %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
ret <4 x i32> %0
}
define <4 x i32> @test_zip_and_extract(<2 x i32>* %A) {
[ARM] Generate checks for shuffle tests using update_llc_test_checks.py. llvm-svn: 290196
2016-12-21 03:33:24 +08:00
; CHECK-LABEL: test_zip_and_extract:
; CHECK: @ BB#0: @ %entry
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vorr q9, q8, q8
; CHECK-NEXT: vorr q10, q8, q8
; CHECK-NEXT: vzip.32 q9, q10
; CHECK-NEXT: vext.32 q8, q9, q8, #2
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[ARM] - Fix lowering of shufflevectors in AArch32 Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 llvm-svn: 243103
2015-07-24 17:57:05 +08:00
entry:
%tmp1 = load <2 x i32>, <2 x i32>* %A
%0 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 0, i32 1>
ret <4 x i32> %0
}