llvm-project/llvm/test/CodeGen/SystemZ/cond-move-05.mir

# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=greedy %s -o - \
# RUN:   | FileCheck %s
#
# Test that regalloc hints work for LOCRMux when a 128bit register is
# involved.


--- |
  ; ModuleID = 'tc.ll'
  source_filename = "bugpoint-output-126c57d.bc"
  target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
  target triple = "s390x--linux-gnu"
  
  @g_74 = external global i32, align 4
  
  ; Function Attrs: nounwind
  define void @main() local_unnamed_addr #0 {
  entry:
    %0 = load i32, i32* @g_74, align 4
    %conv478.i.i = sext i32 %0 to i64
    %cond.i15.i.i = lshr i32 1, 0
    %conv2.i16.i.i = zext i32 %cond.i15.i.i to i64
    %rem.i12.i.i = urem i64 %conv2.i16.i.i, %conv478.i.i
    %conv480.i.i = trunc i64 %rem.i12.i.i to i32
    %1 = icmp ult i32 %conv480.i.i, -663124367
    %rem.i.i.i = select i1 %1, i32 %conv480.i.i, i32 undef
    %tobool482.i.i = icmp eq i32 %rem.i.i.i, 0
    br i1 %tobool482.i.i, label %for.inc591.1.i.i, label %cleanup584.i.i
  
  cleanup584.i.i:                                   ; preds = %entry
    unreachable
  
  for.inc591.1.i.i:                                 ; preds = %entry
    unreachable
  }
  
  attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="z13" "target-features"="+transactional-execution,+vector" "unsafe-fp-math"="false" "use-soft-float"="false" }
  
  !llvm.ident = !{!0}
  
  !0 = !{!"clang version 6.0.0 (http://llvm.org/git/clang.git d80246686d6ad2a749d11470afbbd1bbe4d1b561) (http://llvm.org/git/llvm.git 1693ef38604a3ad9c3da656d2b58a77312207b01)"}

...

# CHECK: locr
# CHECK-NOT: risblg

---
name:            main
alignment:       2
tracksRegLiveness: true
registers:       
  - { id: 0, class: gr64bit }
  - { id: 1, class: gr64bit }
  - { id: 2, class: gr128bit }
  - { id: 3, class: gr128bit }
  - { id: 4, class: gr64bit }
  - { id: 5, class: grx32bit }
  - { id: 6, class: grx32bit }
  - { id: 7, class: grx32bit }
  - { id: 8, class: gr128bit }
  - { id: 9, class: gr128bit }
  - { id: 10, class: gr64bit }
body:             |
  bb.0.entry:
    %0:gr64bit = LGFRL @g_74 :: (dereferenceable load 4 from @g_74)
    undef %3.subreg_l64:gr128bit = LGHI 1
    %3.subreg_h64:gr128bit = LLILL 0
    %3:gr128bit = DLGR %3, %0
    CLFIMux %3.subreg_hl32, 3631842929, implicit-def $cc
    %6:grx32bit = LOCRMux undef %6, %3.subreg_hl32, 14, 4, implicit killed $cc
    CHIMux %6, 0, implicit-def $cc
    BRC 14, 8, %bb.2.for.inc591.1.i.i, implicit killed $cc
    J %bb.1.cleanup584.i.i
  
  bb.1.cleanup584.i.i:
    successors: 
  
  
  bb.2.for.inc591.1.i.i:

...