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llvm-project/llvm/test/CodeGen/X86/system-intrinsics-xsetbv.ll

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[X86] Add xgetbv/xsetbv intrinsics to non-windows platforms Differential Revision: https://reviews.llvm.org/D21958 llvm-svn: 278782
2016-08-16 14:41:00 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+xsave | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xsave | FileCheck %s --check-prefix=CHECK64
define void @test_xsetbv(i32 %in, i32 %high, i32 %low) {
; CHECK-LABEL: test_xsetbv
; CHECK: movl 4(%esp), %ecx
; CHECK: movl 8(%esp), %edx
; CHECK: movl 12(%esp), %eax
; CHECK: xsetbv
; CHECK: ret
; CHECK64-LABEL: test_xsetbv
; CHECK64: movl %edx, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK64-DAG: movl %edi, %ecx
; CHECK64-DAG: movl %esi, %edx
[X86] Add xgetbv/xsetbv intrinsics to non-windows platforms Differential Revision: https://reviews.llvm.org/D21958 llvm-svn: 278782
2016-08-16 14:41:00 +08:00
; CHECK64: xsetbv
; CHECK64: ret
call void @llvm.x86.xsetbv(i32 %in, i32 %high, i32 %low)
ret void;
}
declare void @llvm.x86.xsetbv(i32, i32, i32)