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llvm-project/llvm/test/CodeGen/X86/3addr-or.ll

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[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. llvm-svn: 93152
2010-01-12 01:03:47 +08:00
; rdar://7527734
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
define i32 @test1(i32 %x) nounwind ssp {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test1:
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK: # %bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-NEXT: shll $5, %edi
; CHECK-NEXT: leal 3(%rdi), %eax
; CHECK-NEXT: retq
%t0 = shl i32 %x, 5
%t1 = or i32 %t0, 3
ret i32 %t1
Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. llvm-svn: 93152
2010-01-12 01:03:47 +08:00
}
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. llvm-svn: 93191
2010-01-12 06:03:29 +08:00
[X86] Add an override of targetShrinkDemandedConstant to limit the damage that shrinkdemandedbits can do to zext_in_reg operations Summary: This patch adds an implementation of targetShrinkDemandedConstant that tries to keep shrinkdemandedbits from removing bits that would otherwise have been recognized as a movzx. We still need a follow patch to stop moving ands across srl if the and could be represented as a movzx before the shift but not after. I think this should help with some of the cases that D42088 ended up removing during isel. Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42265 llvm-svn: 323048
2018-01-21 02:50:09 +08:00
; This test no longer requires or to be converted to 3 addr form because we are
; are able to use a zero extend instead of an 'and' which gives the register
; allocator freedom.
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. llvm-svn: 93191
2010-01-12 06:03:29 +08:00
define i64 @test2(i8 %A, i8 %B) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test2:
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK: # %bb.0:
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors. Masking first, prevents the extend from being combine with loads. Its also interfering with some vXi1 extraction code. Differential Revision: https://reviews.llvm.org/D42679 llvm-svn: 326500
2018-03-02 06:32:25 +08:00
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-NEXT: shll $4, %edi
; CHECK-NEXT: andl $48, %edi
[X86] Add an override of targetShrinkDemandedConstant to limit the damage that shrinkdemandedbits can do to zext_in_reg operations Summary: This patch adds an implementation of targetShrinkDemandedConstant that tries to keep shrinkdemandedbits from removing bits that would otherwise have been recognized as a movzx. We still need a follow patch to stop moving ands across srl if the and could be represented as a movzx before the shift but not after. I think this should help with some of the cases that D42088 ended up removing during isel. Reviewers: spatel, RKSimon Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42265 llvm-svn: 323048
2018-01-21 02:50:09 +08:00
; CHECK-NEXT: movzbl %sil, %eax
; CHECK-NEXT: shrq $4, %rax
; CHECK-NEXT: orq %rdi, %rax
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-NEXT: retq
%C = zext i8 %A to i64
%D = shl i64 %C, 4
%E = and i64 %D, 48
%F = zext i8 %B to i64
%G = lshr i64 %F, 4
%H = or i64 %G, %E
Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. llvm-svn: 93191
2010-01-12 06:03:29 +08:00
ret i64 %H
}
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
;; Test that OR is only emitted as LEA, not as ADD.
; No reason to emit an add here, should be an or.
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test3:
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: shll $5, %edi
; CHECK-NEXT: orl $3, %edi
; CHECK-NEXT: movl %edi, (%rsi)
; CHECK-NEXT: retq
%t0 = shl i32 %x, 5
%t1 = or i32 %t0, 3
store i32 %t1, i32* %P
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
ret void
}
define i32 @test4(i32 %a, i32 %b) nounwind readnone ssp {
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-LABEL: test4:
; CHECK: # %bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK-NEXT: # kill: def $esi killed $esi def $rsi
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-NEXT: andl $6, %edi
; CHECK-NEXT: andl $16, %esi
; CHECK-NEXT: leal (%rsi,%rdi), %eax
; CHECK-NEXT: retq
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
%and = and i32 %a, 6
%and2 = and i32 %b, 16
%or = or i32 %and2, %and
ret i32 %or
}
define void @test5(i32 %a, i32 %b, i32* nocapture %P) nounwind ssp {
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00
; CHECK-LABEL: test5:
; CHECK: # %bb.0:
; CHECK-NEXT: andl $6, %edi
; CHECK-NEXT: andl $16, %esi
; CHECK-NEXT: orl %edi, %esi
; CHECK-NEXT: movl %esi, (%rdx)
; CHECK-NEXT: retq
reapply: Use the new TB_NOT_REVERSABLE flag instead of special reapply: reimplement the second half of the or/add optimization. We should now with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things a bit. llvm-svn: 116040
2010-10-08 11:57:25 +08:00
%and = and i32 %a, 6
%and2 = and i32 %b, 16
%or = or i32 %and2, %and
store i32 %or, i32* %P, align 4
ret void
}
[x86] regenerate complete checks; NFC D42265 will improve something here, but it's not obvious how without more checks. llvm-svn: 322960
2018-01-20 01:05:16 +08:00