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llvm-project/llvm/test/CodeGen/PowerPC/ppcf128-2.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs < %s -march=ppc64
More APInt-ification. llvm-svn: 48344
2008-03-14 06:13:53 +08:00
define i64 @__fixtfdi(ppc_fp128 %a) nounwind {
entry:
br i1 false, label %bb, label %bb8
bb: ; preds = %entry
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp5 = fsub ppc_fp128 0xM80000000000000000000000000000000, %a ; <ppc_fp128> [#uses=1]
More APInt-ification. llvm-svn: 48344
2008-03-14 06:13:53 +08:00
%tmp6 = tail call i64 @__fixunstfdi( ppc_fp128 %tmp5 ) nounwind ; <i64> [#uses=0]
ret i64 0
bb8: ; preds = %entry
ret i64 0
}
declare i64 @__fixunstfdi(ppc_fp128)