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llvm-project/bolt/unittests/Core/CMakeLists.txt

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[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
set(LLVM_LINK_COMPONENTS
[BOLT-UnitTests] Fix shared libraries build Fix build with `-DBUILD_SHARED_LIBS=ON` (add explicit deps). Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D119042
2022-02-05 07:04:01 +08:00
DebugInfoDWARF
Object
[BOLT][NFC] Fix undefined behavior in encodeAnnotationImm Fix UBSan-reported issue in MCPlusBuilder::encodeAnnotationImm (left shift of a negative value). Test Plan: ``` ninja check-bolt ... PASS: BOLT-Unit :: Core/./CoreTests/AArch64/MCPlusBuilderTester.Annotation/0 (1 of 140) PASS: BOLT-Unit :: Core/./CoreTests/X86/MCPlusBuilderTester.Annotation/0 (131 of 134) ``` Reviewed By: maksfb, yota9 Differential Revision: https://reviews.llvm.org/D120260
2022-02-23 14:54:15 +08:00
MC
[BOLT-UnitTests] Fix shared libraries build Fix build with `-DBUILD_SHARED_LIBS=ON` (add explicit deps). Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D119042
2022-02-05 07:04:01 +08:00
${LLVM_TARGETS_TO_BUILD}
[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
)
add_bolt_unittest(CoreTests
[BOLT][perf2bolt] Fix base address calculation for shared objects When processing profile data for shared object or PIE, perf2bolt needs to calculate base address of the binary based on the map info reported by the perf tool. When the mapping data provided is for the second (or any other than the first) segment and the segment's file offset does not match its memory offset, perf2bolt uses wrong assumption about the binary base address. Add a function to calculate binary base address using the reported memory mapping and use the returned base for further address adjustments. Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D123755
2022-04-14 10:39:39 +08:00
BinaryContext.cpp
[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
MCPlusBuilder.cpp
)
[BOLT][CMAKE] Fix DYLIB build Move BOLT libraries out of `LLVM_LINK_COMPONENTS` to `target_link_libraries`. Addresses issue #55432. Reviewed By: rafauler Differential Revision: https://reviews.llvm.org/D125568
2022-05-14 04:14:45 +08:00
target_link_libraries(CoreTests
PRIVATE
LLVMBOLTCore
LLVMBOLTRewrite
)
[BOLT-UnitTests] Fix shared libraries build Fix build with `-DBUILD_SHARED_LIBS=ON` (add explicit deps). Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D119042
2022-02-05 07:04:01 +08:00
if ("AArch64" IN_LIST LLVM_TARGETS_TO_BUILD)
[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
include_directories(
[BOLT-UnitTests] Fix shared libraries build Fix build with `-DBUILD_SHARED_LIBS=ON` (add explicit deps). Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D119042
2022-02-05 07:04:01 +08:00
${LLVM_MAIN_SRC_DIR}/lib/Target/AArch64
${LLVM_BINARY_DIR}/lib/Target/AArch64
[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
)
target_compile_definitions(CoreTests PRIVATE AARCH64_AVAILABLE)
endif()
[BOLT-UnitTests] Fix shared libraries build Fix build with `-DBUILD_SHARED_LIBS=ON` (add explicit deps). Reviewed By: yota9 Differential Revision: https://reviews.llvm.org/D119042
2022-02-05 07:04:01 +08:00
if ("X86" IN_LIST LLVM_TARGETS_TO_BUILD)
[BOLT] Fix AARCH64 registers aliasing The aarch64 platform has special registers like X0_X1_X2_X3_X4_X5_X6_X7. Using the downwards propagation this register will become a super register for all X0..X7 and its super registers which is not right. This patch replaces the downwards propagation with caching all the aliases using MCRegAliasIterator. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Reviewed By: maksfb Differential Revision: https://reviews.llvm.org/D117394
2022-01-28 06:04:31 +08:00
include_directories(
${LLVM_MAIN_SRC_DIR}/lib/Target/X86
${LLVM_BINARY_DIR}/lib/Target/X86
)
target_compile_definitions(CoreTests PRIVATE X86_AVAILABLE)
endif()