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llvm-project/llvm/test/MC/Disassembler/X86/avx512bf16-intel.txt

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Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data. VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data. VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision. For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Author: LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel Reviewed By: craig.topper Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60550 llvm-svn: 360017
2019-05-06 16:22:37 +08:00
# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s
# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmm4
0x62,0xf2,0x67,0x48,0x72,0xd4
# CHECK: vcvtne2ps2bf16 zmm2 {k7}, zmm3, zmm4
0x62,0xf2,0x67,0x4f,0x72,0xd4
# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, zmm4
0x62,0xf2,0x67,0xcf,0x72,0xd4
# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456]
0x62,0xf2,0x67,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10
# CHECK: vcvtne2ps2bf16 zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291]
0x62,0xf2,0x67,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00
# CHECK: vcvtne2ps2bf16 zmm2, zmm3, dword ptr [eax]{1to16}
0x62,0xf2,0x67,0x58,0x72,0x10
# CHECK: vcvtne2ps2bf16 zmm2, zmm3, zmmword ptr [2*ebp - 2048]
0x62,0xf2,0x67,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff
# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128]
0x62,0xf2,0x67,0xcf,0x72,0x51,0x7f
# CHECK: vcvtne2ps2bf16 zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16}
0x62,0xf2,0x67,0xdf,0x72,0x52,0x80
# CHECK: vcvtneps2bf16 ymm2, zmm3
0x62,0xf2,0x7e,0x48,0x72,0xd3
# CHECK: vcvtneps2bf16 ymm2 {k7}, zmm3
0x62,0xf2,0x7e,0x4f,0x72,0xd3
# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, zmm3
0x62,0xf2,0x7e,0xcf,0x72,0xd3
# CHECK: vcvtneps2bf16 ymm2, zmmword ptr [esp + 8*esi + 268435456]
0x62,0xf2,0x7e,0x48,0x72,0x94,0xf4,0x00,0x00,0x00,0x10
# CHECK: vcvtneps2bf16 ymm2 {k7}, zmmword ptr [edi + 4*eax + 291]
0x62,0xf2,0x7e,0x4f,0x72,0x94,0x87,0x23,0x01,0x00,0x00
# CHECK: vcvtneps2bf16 ymm2, dword ptr [eax]{1to16}
0x62,0xf2,0x7e,0x58,0x72,0x10
# CHECK: vcvtneps2bf16 ymm2, zmmword ptr [2*ebp - 2048]
0x62,0xf2,0x7e,0x48,0x72,0x14,0x6d,0x00,0xf8,0xff,0xff
# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, zmmword ptr [ecx + 8128]
0x62,0xf2,0x7e,0xcf,0x72,0x51,0x7f
# CHECK: vcvtneps2bf16 ymm2 {k7} {z}, dword ptr [edx - 512]{1to16}
0x62,0xf2,0x7e,0xdf,0x72,0x52,0x80
# CHECK: vdpbf16ps zmm2, zmm3, zmm4
0x62,0xf2,0x66,0x48,0x52,0xd4
# CHECK: vdpbf16ps zmm2 {k7}, zmm3, zmm4
0x62,0xf2,0x66,0x4f,0x52,0xd4
# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, zmm4
0x62,0xf2,0x66,0xcf,0x52,0xd4
# CHECK: vdpbf16ps zmm2, zmm3, zmmword ptr [esp + 8*esi + 268435456]
0x62,0xf2,0x66,0x48,0x52,0x94,0xf4,0x00,0x00,0x00,0x10
# CHECK: vdpbf16ps zmm2 {k7}, zmm3, zmmword ptr [edi + 4*eax + 291]
0x62,0xf2,0x66,0x4f,0x52,0x94,0x87,0x23,0x01,0x00,0x00
# CHECK: vdpbf16ps zmm2, zmm3, dword ptr [eax]{1to16}
0x62,0xf2,0x66,0x58,0x52,0x10
# CHECK: vdpbf16ps zmm2, zmm3, zmmword ptr [2*ebp - 2048]
0x62,0xf2,0x66,0x48,0x52,0x14,0x6d,0x00,0xf8,0xff,0xff
# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, zmmword ptr [ecx + 8128]
0x62,0xf2,0x66,0xcf,0x52,0x51,0x7f
# CHECK: vdpbf16ps zmm2 {k7} {z}, zmm3, dword ptr [edx - 512]{1to16}
0x62,0xf2,0x66,0xdf,0x52,0x52,0x80