maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/PowerPC/pr36292.ll

57 lines
1.8 KiB
LLVM
Raw Normal View History

[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[PowerPC] Do not produce invalid CTR loop with an FRem An FRem instruction inside a loop should prevent the loop from being converted into a CTR loop since this is not an operation that is legal on any PPC subtarget. This will always be a call to a library function which means the loop will be invalid if this instruction is in the body. Fixes PR36292. llvm-svn: 325739
2018-02-22 11:02:41 +08:00
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
; RUN: FileCheck %s --implicit-check-not=mtctr --implicit-check-not=bdnz
$test = comdat any
; No CTR loop due to frem (since it is always a call).
define void @test() #0 comdat {
; CHECK-LABEL: test:
[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK-NEXT: .cfi_def_cfa_offset 64
[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; CHECK-NEXT: .cfi_offset lr, 16
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK-NEXT: .cfi_offset r29, -24
; CHECK-NEXT: .cfi_offset r30, -16
; CHECK-NEXT: std 29, -24(1) # 8-byte Folded Spill
; CHECK-NEXT: std 30, -16(1) # 8-byte Folded Spill
[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; CHECK-NEXT: std 0, 16(1)
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK-NEXT: stdu 1, -64(1)
[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; CHECK-NEXT: ld 29, 0(3)
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK-NEXT: ld 30, 32(1)
[NFC][PowerPC] Update testcases using utils/update_llc_test_checks.py llvm-svn: 355945
2019-03-13 01:55:32 +08:00
; CHECK-NEXT: cmpld 30, 29
[PowerPC] Do not produce invalid CTR loop with an FRem An FRem instruction inside a loop should prevent the loop from being converted into a CTR loop since this is not an operation that is legal on any PPC subtarget. This will always be a call to a library function which means the loop will be invalid if this instruction is in the body. Fixes PR36292. llvm-svn: 325739
2018-02-22 11:02:41 +08:00
; CHECK-NEXT: bge- 0, .LBB0_2
; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_1: # %bounds.ok
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK: lfsx 2, 0, 3
; CHECK-NEXT: xxlxor 1, 1, 1
[PowerPC] Do not produce invalid CTR loop with an FRem An FRem instruction inside a loop should prevent the loop from being converted into a CTR loop since this is not an operation that is legal on any PPC subtarget. This will always be a call to a library function which means the loop will be invalid if this instruction is in the body. Fixes PR36292. llvm-svn: 325739
2018-02-22 11:02:41 +08:00
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: nop
; CHECK-NEXT: addi 30, 30, 1
; CHECK-NEXT: stfsx 1, 0, 3
; CHECK-NEXT: cmpld 30, 29
; CHECK-NEXT: blt+ 0, .LBB0_1
; CHECK-NEXT: .LBB0_2: # %bounds.fail
Set useful flags for vector imm setting instructions Vector imm setting instructions like XXLXORz/XXLXORspz/XXLXORdpz Should behave like LI8. We should set corresponding flags to allow rematerialization and other opts in LICM, RA, Scheduling etc. Differential Revision: https://reviews.llvm.org/D58645 llvm-svn: 355948
2019-03-13 02:27:09 +08:00
; CHECK-NEXT: std 30, 32(1)
[PowerPC] Do not produce invalid CTR loop with an FRem An FRem instruction inside a loop should prevent the loop from being converted into a CTR loop since this is not an operation that is legal on any PPC subtarget. This will always be a call to a library function which means the loop will be invalid if this instruction is in the body. Fixes PR36292. llvm-svn: 325739
2018-02-22 11:02:41 +08:00
%pos = alloca i64, align 8
br label %forcond
forcond: ; preds = %bounds.ok, %0
%1 = load i64, i64* %pos
%.len1 = load i64, i64* undef
%bounds.cmp = icmp ult i64 %1, %.len1
br i1 %bounds.cmp, label %bounds.ok, label %bounds.fail
bounds.ok: ; preds = %forcond
%2 = load float, float* undef
%3 = frem float 0.000000e+00, %2
store float %3, float* undef
%4 = load i64, i64* %pos
%5 = add i64 %4, 1
store i64 %5, i64* %pos
br label %forcond
bounds.fail: ; preds = %forcond
unreachable
}