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llvm-project/llvm/test/CodeGen/AArch64/hints.ll

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AArch64: add support for llvm.aarch64.hint intrinsic This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to support the various hint intrinsic functions in the ACLE. Add an optional pattern field that permits the subclass to specify the pattern that matches the selection. The intrinsic pattern is set as mayLoad, mayStore, so overload the value for the definition of the hint instruction. llvm-svn: 212883
2014-07-13 05:20:49 +08:00
; RUN: llc -mtriple aarch64-eabi -o - %s | FileCheck %s
declare void @llvm.aarch64.hint(i32) nounwind
define void @hint_nop() {
entry:
tail call void @llvm.aarch64.hint(i32 0) nounwind
ret void
}
; CHECK-LABEL: hint_nop
; CHECK: nop
define void @hint_yield() {
entry:
tail call void @llvm.aarch64.hint(i32 1) nounwind
ret void
}
; CHECK-LABEL: hint_yield
; CHECK: yield
define void @hint_wfe() {
entry:
tail call void @llvm.aarch64.hint(i32 2) nounwind
ret void
}
; CHECK-LABEL: hint_wfe
; CHECK: wfe
define void @hint_wfi() {
entry:
tail call void @llvm.aarch64.hint(i32 3) nounwind
ret void
}
; CHECK-LABEL: hint_wfi
; CHECK: wfi
define void @hint_sev() {
entry:
tail call void @llvm.aarch64.hint(i32 4) nounwind
ret void
}
; CHECK-LABEL: hint_sev
; CHECK: sev
define void @hint_sevl() {
entry:
tail call void @llvm.aarch64.hint(i32 5) nounwind
ret void
}
; CHECK-LABEL: hint_sevl
; CHECK: sevl
define void @hint_undefined() {
entry:
tail call void @llvm.aarch64.hint(i32 8) nounwind
ret void
}
; CHECK-LABEL: hint_undefined
add support for -print-imm-hex for AArch64 Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
2016-05-14 02:00:09 +08:00
; CHECK: hint #8
AArch64: add support for llvm.aarch64.hint intrinsic This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to support the various hint intrinsic functions in the ACLE. Add an optional pattern field that permits the subclass to specify the pattern that matches the selection. The intrinsic pattern is set as mayLoad, mayStore, so overload the value for the definition of the hint instruction. llvm-svn: 212883
2014-07-13 05:20:49 +08:00