2016-08-04 02:17:35 +08:00
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; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -fast-isel=false < %s | FileCheck %s
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This patch addresses a PPC64 ELF issue with passing parameters consisting of
structs having size 3, 5, 6, or 7. Such a struct must be passed and received
as right-justified within its register or memory slot. The problem is only
present for structs that are passed in registers.
Previously, as part of a patch handling all structs of size less than 8, I
added logic to rotate the incoming register so that the struct was left-
justified prior to storing the whole register. This was incorrect because
the address of the parameter had already been adjusted earlier to point to
the right-adjusted value in the storage slot. Essentially I had accidentally
accounted for the right-adjustment twice.
In this patch, I removed the incorrect logic and reorganized the code to make
the flow clearer.
The removal of the rotates changes the expected code generation, so test case
structsinregs.ll has been modified to reflect this. I also added a new test
case, jaggedstructs.ll, to demonstrate that structs of these sizes can now
be properly received and passed.
I've built and tested the code on powerpc64-unknown-linux-gnu with no new
regressions. I also ran the GCC compatibility test suite and verified that
earlier problems with these structs are now resolved, with no new regressions.
llvm-svn: 166680
2012-10-25 21:38:09 +08:00
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; This tests receiving and re-passing parameters consisting of structures
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; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
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; the parameter registers.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.S3 = type { [3 x i8] }
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%struct.S5 = type { [5 x i8] }
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%struct.S6 = type { [6 x i8] }
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%struct.S7 = type { [7 x i8] }
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define void @test(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) nounwind {
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entry:
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call void @check(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7)
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ret void
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}
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In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
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; CHECK-DAG: std 3, 160(1)
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; CHECK-DAG: std 6, 184(1)
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; CHECK-DAG: std 5, 176(1)
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; CHECK-DAG: std 4, 168(1)
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; CHECK-DAG: lbz {{[0-9]+}}, 167(1)
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; CHECK-DAG: lhz {{[0-9]+}}, 165(1)
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; CHECK-DAG: stb {{[0-9]+}}, 55(1)
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; CHECK-DAG-DAG: sth {{[0-9]+}}, 53(1)
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; CHECK-DAG: lbz {{[0-9]+}}, 175(1)
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; CHECK-DAG: lwz {{[0-9]+}}, 171(1)
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; CHECK-DAG: stb {{[0-9]+}}, 63(1)
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; CHECK-DAG: stw {{[0-9]+}}, 59(1)
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; CHECK-DAG: lhz {{[0-9]+}}, 182(1)
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; CHECK-DAG: lwz {{[0-9]+}}, 178(1)
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; CHECK-DAG: sth {{[0-9]+}}, 70(1)
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; CHECK-DAG: stw {{[0-9]+}}, 66(1)
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; CHECK-DAG: lbz {{[0-9]+}}, 191(1)
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; CHECK-DAG: lhz {{[0-9]+}}, 189(1)
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; CHECK-DAG: lwz {{[0-9]+}}, 185(1)
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; CHECK-DAG: stb {{[0-9]+}}, 79(1)
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; CHECK-DAG: sth {{[0-9]+}}, 77(1)
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; CHECK-DAG: stw {{[0-9]+}}, 73(1)
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; CHECK-DAG: ld 6, 72(1)
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; CHECK-DAG: ld 5, 64(1)
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; CHECK-DAG: ld 4, 56(1)
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; CHECK-DAG: ld 3, 48(1)
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This patch addresses a PPC64 ELF issue with passing parameters consisting of
structs having size 3, 5, 6, or 7. Such a struct must be passed and received
as right-justified within its register or memory slot. The problem is only
present for structs that are passed in registers.
Previously, as part of a patch handling all structs of size less than 8, I
added logic to rotate the incoming register so that the struct was left-
justified prior to storing the whole register. This was incorrect because
the address of the parameter had already been adjusted earlier to point to
the right-adjusted value in the storage slot. Essentially I had accidentally
accounted for the right-adjustment twice.
In this patch, I removed the incorrect logic and reorganized the code to make
the flow clearer.
The removal of the rotates changes the expected code generation, so test case
structsinregs.ll has been modified to reflect this. I also added a new test
case, jaggedstructs.ll, to demonstrate that structs of these sizes can now
be properly received and passed.
I've built and tested the code on powerpc64-unknown-linux-gnu with no new
regressions. I also ran the GCC compatibility test suite and verified that
earlier problems with these structs are now resolved, with no new regressions.
llvm-svn: 166680
2012-10-25 21:38:09 +08:00
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declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval)
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