forked from OSchip/llvm-project
82 lines
2.1 KiB
LLVM
82 lines
2.1 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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; Check the latency for ALU shifted operand variants.
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;
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; CHECK: ********** MI Scheduling **********
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; CHECK: foo:BB#0 entry
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; ALU, basic - 1 cyc I0/I1
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; CHECK: EORrr
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 1
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; ALU, shift by immed - 2 cyc M
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; CHECK: ADDrsi
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 2
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; ALU, shift by register, unconditional - 2 cyc M
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; CHECK: RSBrsr
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 2
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; ALU, shift by register, conditional - 2 cyc I0/I1
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; CHECK: ANDrsr
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 2
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; Checking scheduling units
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; Skipping COPY
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; CHECK: Scheduling
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; CHECK-SAME: ANDrsr
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; CHECK: Ready
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; CHECK-NEXT: A57UnitI
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; CHECK: Scheduling
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; CHECK-SAME: CMPri
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; CHECK: Ready
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; CHECK-NEXT: A57UnitI
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; CHECK: Scheduling
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; CHECK-SAME: RSBrsr
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; CHECK: Ready
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; CHECK-NEXT: A57UnitM
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; CHECK: Scheduling
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; CHECK-SAME: ADDrsi
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; CHECK: Ready
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; CHECK-NEXT: A57UnitM
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; CHECK: ** ScheduleDAGMILive::schedule picking next node
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; CHECK: Scheduling
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; CHECK-SAME: EORrr
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; CHECK: Ready
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; CHECK-NEXT: A57UnitI
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8r-arm-none-eabi"
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; Function Attrs: norecurse nounwind readnone
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define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 {
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entry:
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%xor = xor i32 %a, %b
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%xor_shl = shl i32 %xor, 2
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%add = add i32 %xor_shl, %d
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%add_ashr = ashr i32 %add, %a
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%sub = sub i32 %add_ashr, %a
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%sub_lshr_pred = lshr i32 %sub, %c
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%pred = icmp sgt i32 %a, 4
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%and = and i32 %sub_lshr_pred, %b
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%rv = select i1 %pred, i32 %and, i32 %d
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ret i32 %rv
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}
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