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llvm-project/llvm/test/CodeGen/AArch64/xor.ll

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[AArch64, x86] add tests for shift-not (PR39657); NFC llvm-svn: 347316
2018-11-20 23:49:42 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
define i32 @PR39657(i8* %p, i64 %x) {
; CHECK-LABEL: PR39657:
; CHECK: // %bb.0:
[DAGCombiner] form 'not' ops ahead of shifts (PR39657) We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'), but that would not matter without this patch because DAGCombiner was reversing that transform. I think we need this transform in the backend regardless of what happens in IR to catch cases where the shift-xor is formed late from GEP or other ops. https://rise4fun.com/Alive/NC1 Name: shl Pre: (-1 << C2) == C1 %shl = shl i8 %x, C2 %r = xor i8 %shl, C1 => %not = xor i8 %x, -1 %r = shl i8 %not, C2 Name: shr Pre: (-1 u>> C2) == C1 %sh = lshr i8 %x, C2 %r = xor i8 %sh, C1 => %not = xor i8 %x, -1 %r = lshr i8 %not, C2 https://bugs.llvm.org/show_bug.cgi?id=39657 llvm-svn: 347478
2018-11-23 03:24:10 +08:00
; CHECK-NEXT: mvn x8, x1
; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
[AArch64, x86] add tests for shift-not (PR39657); NFC llvm-svn: 347316
2018-11-20 23:49:42 +08:00
; CHECK-NEXT: ret
%sh = shl i64 %x, 2
%mul = xor i64 %sh, -4
%add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
%bc = bitcast i8* %add.ptr to i32*
%load = load i32, i32* %bc, align 4
ret i32 %load
}