forked from OSchip/llvm-project
31 lines
1.3 KiB
LLVM
31 lines
1.3 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s
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; This test makes sure spills of 64-bit pairs in Thumb mode actually
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; generate thumb instructions. Previously we were inserting an ARM
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; STMIA which happened to have the same encoding.
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define void @foo(i64* %addr) {
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%val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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; Make sure we are actually creating the Thumb versions of the spill
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; instructions.
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; CHECK: t2STRDi8
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; CHECK: t2LDRDi8
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store volatile i64 %val1, i64* %addr
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store volatile i64 %val2, i64* %addr
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store volatile i64 %val3, i64* %addr
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store volatile i64 %val4, i64* %addr
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store volatile i64 %val5, i64* %addr
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store volatile i64 %val6, i64* %addr
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store volatile i64 %val7, i64* %addr
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ret void
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}
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