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llvm-project/llvm/test/CodeGen/X86/test-shrink.ll

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Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=CHECK-LINUX64
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=CHECK-WIN32-64
; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=CHECK-X86
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g64xh(i64 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g64xh:
; CHECK-LINUX64: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-LINUX64-NEXT: testl $2048, %edi # imm = 0x800
; CHECK-LINUX64-NEXT: jne .LBB0_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB0_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g64xh:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-WIN32-64-NEXT: testl $2048, %ecx # imm = 0x800
; CHECK-WIN32-64-NEXT: jne .LBB0_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB0_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g64xh:
; CHECK-X86: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB0_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB0_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i64 %x, 2048
%s = icmp eq i64 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g64xl(i64 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g64xl:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testb $8, %dil
; CHECK-LINUX64-NEXT: jne .LBB1_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB1_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g64xl:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testb $8, %cl
; CHECK-WIN32-64-NEXT: jne .LBB1_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB1_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g64xl:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB1_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB1_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i64 %x, 8
%s = icmp eq i64 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g32xh(i32 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g32xh:
; CHECK-LINUX64: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-LINUX64-NEXT: testl $2048, %edi # imm = 0x800
; CHECK-LINUX64-NEXT: jne .LBB2_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB2_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g32xh:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-WIN32-64-NEXT: testl $2048, %ecx # imm = 0x800
; CHECK-WIN32-64-NEXT: jne .LBB2_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB2_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g32xh:
; CHECK-X86: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB2_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB2_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i32 %x, 2048
%s = icmp eq i32 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g32xl(i32 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g32xl:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testb $8, %dil
; CHECK-LINUX64-NEXT: jne .LBB3_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB3_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g32xl:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testb $8, %cl
; CHECK-WIN32-64-NEXT: jne .LBB3_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB3_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g32xl:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB3_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB3_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i32 %x, 8
%s = icmp eq i32 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g16xh(i16 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g16xh:
; CHECK-LINUX64: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-LINUX64-NEXT: testl $2048, %edi # imm = 0x800
; CHECK-LINUX64-NEXT: jne .LBB4_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB4_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g16xh:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; CHECK-WIN32-64-NEXT: # kill: def $cx killed $cx def $ecx
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-WIN32-64-NEXT: testl $2048, %ecx # imm = 0x800
; CHECK-WIN32-64-NEXT: jne .LBB4_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB4_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g16xh:
; CHECK-X86: # %bb.0:
[X86] Only reorder srl/and on last DAG combiner run This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST. We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering. Differential Revision: https://reviews.llvm.org/D43201 llvm-svn: 325371
2018-02-17 02:51:09 +08:00
; CHECK-X86-NEXT: testl $2048, %eax # imm = 0x800
; CHECK-X86-NEXT: jne .LBB4_2
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB4_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i16 %x, 2048
%s = icmp eq i16 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g16xl(i16 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g16xl:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testb $8, %dil
; CHECK-LINUX64-NEXT: jne .LBB5_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB5_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g16xl:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; CHECK-WIN32-64-NEXT: # kill: def $cx killed $cx def $ecx
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-WIN32-64-NEXT: testb $8, %cl
; CHECK-WIN32-64-NEXT: jne .LBB5_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB5_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g16xl:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testb $8, %al
; CHECK-X86-NEXT: jne .LBB5_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB5_2: # %no
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i16 %x, 8
%s = icmp eq i16 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g64x16(i64 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g64x16:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testl $32896, %edi # imm = 0x8080
; CHECK-LINUX64-NEXT: je .LBB6_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB6_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g64x16:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testl $32896, %ecx # imm = 0x8080
; CHECK-WIN32-64-NEXT: je .LBB6_1
; CHECK-WIN32-64-NEXT: # %bb.2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
; CHECK-WIN32-64-NEXT: .LBB6_1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g64x16:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testl $32896, %eax # imm = 0x8080
; CHECK-X86-NEXT: je .LBB6_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB6_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i64 %x, 32896
%s = icmp eq i64 %t, 0
br i1 %s, label %yes, label %no
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
define void @g64x16minsize(i64 inreg %x) nounwind minsize {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g64x16minsize:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testw $-32640, %di # imm = 0x8080
; CHECK-LINUX64-NEXT: je .LBB7_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB7_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g64x16minsize:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testw $-32640, %cx # imm = 0x8080
; CHECK-WIN32-64-NEXT: jne .LBB7_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB7_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g64x16minsize:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testw $-32640, %ax # imm = 0x8080
; CHECK-X86-NEXT: je .LBB7_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB7_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
%t = and i64 %x, 32896
%s = icmp eq i64 %t, 0
br i1 %s, label %yes, label %no
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g32x16(i32 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g32x16:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testl $32896, %edi # imm = 0x8080
; CHECK-LINUX64-NEXT: je .LBB8_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB8_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g32x16:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testl $32896, %ecx # imm = 0x8080
; CHECK-WIN32-64-NEXT: je .LBB8_1
; CHECK-WIN32-64-NEXT: # %bb.2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
; CHECK-WIN32-64-NEXT: .LBB8_1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g32x16:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testl $32896, %eax # imm = 0x8080
; CHECK-X86-NEXT: je .LBB8_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB8_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i32 %x, 32896
%s = icmp eq i32 %t, 0
br i1 %s, label %yes, label %no
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
define void @g32x16minsize(i32 inreg %x) nounwind minsize {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g32x16minsize:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testw $-32640, %di # imm = 0x8080
; CHECK-LINUX64-NEXT: je .LBB9_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB9_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g32x16minsize:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testw $-32640, %cx # imm = 0x8080
; CHECK-WIN32-64-NEXT: jne .LBB9_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB9_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g32x16minsize:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testw $-32640, %ax # imm = 0x8080
; CHECK-X86-NEXT: je .LBB9_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB9_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
[X86] Don't select (cmp (and, imm), 0) to testw Summary: X86ISelDAGToDAG tries to analyze ANDs compared with 0 to optimize to narrower immediates using subregisters. I don't think we should be optimizing to 16-bit test instructions. It goes against our normal behavior of promoting i16 operations to i32. It only saves one byte due to the need to add a 0x66 prefix. I think it would also be subject to a length changing prefix penalty in the decoders on Intel CPUs. Reviewers: RKSimon, zvi, spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38273 llvm-svn: 314474
2017-09-29 07:35:36 +08:00
%t = and i32 %x, 32896
%s = icmp eq i32 %t, 0
br i1 %s, label %yes, label %no
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
yes:
call void @bar()
ret void
no:
ret void
}
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
define void @g64x32(i64 inreg %x) nounwind {
Regenerate test-shrink.ll test results. NFC llvm-svn: 320602
2017-12-14 02:04:57 +08:00
; CHECK-LINUX64-LABEL: g64x32:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testl $268468352, %edi # imm = 0x10008080
; CHECK-LINUX64-NEXT: je .LBB10_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB10_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: g64x32:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testl $268468352, %ecx # imm = 0x10008080
; CHECK-WIN32-64-NEXT: je .LBB10_1
; CHECK-WIN32-64-NEXT: # %bb.2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
; CHECK-WIN32-64-NEXT: .LBB10_1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: g64x32:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testl $268468352, %eax # imm = 0x10008080
; CHECK-X86-NEXT: je .LBB10_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB10_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
%t = and i64 %x, 268468352
%s = icmp eq i64 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Add test case for truncated and promotion to test. NFC llvm-svn: 323663
2018-01-30 00:13:01 +08:00
define void @truncand32(i16 inreg %x) nounwind {
; CHECK-LINUX64-LABEL: truncand32:
; CHECK-LINUX64: # %bb.0:
[X86] Generate testl instruction through truncates. Summary: This was introduced in D42646 but ended up being reverted because the original implementation was buggy. Depends on D42646 Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42741 llvm-svn: 323899
2018-02-01 03:20:06 +08:00
; CHECK-LINUX64-NEXT: testl $2049, %edi # imm = 0x801
Add test case for truncated and promotion to test. NFC llvm-svn: 323663
2018-01-30 00:13:01 +08:00
; CHECK-LINUX64-NEXT: je .LBB11_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB11_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: truncand32:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; CHECK-WIN32-64-NEXT: # kill: def $cx killed $cx def $ecx
[X86] Generate testl instruction through truncates. Summary: This was introduced in D42646 but ended up being reverted because the original implementation was buggy. Depends on D42646 Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42741 llvm-svn: 323899
2018-02-01 03:20:06 +08:00
; CHECK-WIN32-64-NEXT: testl $2049, %ecx # imm = 0x801
Add test case for truncated and promotion to test. NFC llvm-svn: 323663
2018-01-30 00:13:01 +08:00
; CHECK-WIN32-64-NEXT: je .LBB11_1
; CHECK-WIN32-64-NEXT: # %bb.2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
; CHECK-WIN32-64-NEXT: .LBB11_1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: truncand32:
; CHECK-X86: # %bb.0:
[X86] Generate testl instruction through truncates. Summary: This was introduced in D42646 but ended up being reverted because the original implementation was buggy. Depends on D42646 Reviewers: craig.topper, niravd, spatel, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42741 llvm-svn: 323899
2018-02-01 03:20:06 +08:00
; CHECK-X86-NEXT: testl $2049, %eax # imm = 0x801
Add test case for truncated and promotion to test. NFC llvm-svn: 323663
2018-01-30 00:13:01 +08:00
; CHECK-X86-NEXT: je .LBB11_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB11_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
%t = and i16 %x, 2049
%s = icmp eq i16 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
[X86] Add test case to ensure testw is generated when optimizing for size. NFC llvm-svn: 323687
2018-01-30 04:22:46 +08:00
define void @testw(i16 inreg %x) nounwind minsize {
; CHECK-LINUX64-LABEL: testw:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testw $2049, %di # imm = 0x801
; CHECK-LINUX64-NEXT: je .LBB12_1
; CHECK-LINUX64-NEXT: # %bb.2: # %no
; CHECK-LINUX64-NEXT: retq
; CHECK-LINUX64-NEXT: .LBB12_1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: testw:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32 Summary: Re-lands r328386 and r328443, reverting r328482. Incorporates fixes from @mstorsjo in D44876 (thanks!) so that small parameters in i8 and i16 do not end up in the SysV register parameters (EDI, ESI, etc). I added tests for how we receive small parameters, since that is the important part. It's always safe to store more bytes than will be read, but the assumptions you make when loading them are what really matter. I also tested this by self-hosting clang and it passed tests on win64. Reviewers: mstorsjo, hans Subscribers: hiraditya, mstorsjo, llvm-commits Differential Revision: https://reviews.llvm.org/D44900 llvm-svn: 328570
2018-03-27 02:49:48 +08:00
; CHECK-WIN32-64-NEXT: # kill: def $cx killed $cx def $ecx
[X86] Add test case to ensure testw is generated when optimizing for size. NFC llvm-svn: 323687
2018-01-30 04:22:46 +08:00
; CHECK-WIN32-64-NEXT: testw $2049, %cx # imm = 0x801
; CHECK-WIN32-64-NEXT: jne .LBB12_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB12_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: testw:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testw $2049, %ax # imm = 0x801
; CHECK-X86-NEXT: je .LBB12_1
; CHECK-X86-NEXT: # %bb.2: # %no
; CHECK-X86-NEXT: retl
; CHECK-X86-NEXT: .LBB12_1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: retl
%t = and i16 %x, 2049
%s = icmp eq i16 %t, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
define void @and16_trunc_8_sign(i16 %x) nounwind {
; CHECK-LINUX64-LABEL: and16_trunc_8_sign:
; CHECK-LINUX64: # %bb.0:
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-LINUX64-NEXT: testb $-128, %dil
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-NEXT: jg .LBB13_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB13_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and16_trunc_8_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-WIN32-64-NEXT: testb $-128, %cl
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB13_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB13_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and16_trunc_8_sign:
; CHECK-X86: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: jg .LBB13_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB13_2: # %no
; CHECK-X86-NEXT: retl
%t = and i16 %x, 128
%r = trunc i16 %t to i8
%s = icmp sle i8 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
define void @and32_trunc_8_sign(i32 %x) nounwind {
; CHECK-LINUX64-LABEL: and32_trunc_8_sign:
; CHECK-LINUX64: # %bb.0:
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-LINUX64-NEXT: testb $-128, %dil
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-NEXT: jg .LBB14_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB14_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and32_trunc_8_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-WIN32-64-NEXT: testb $-128, %cl
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB14_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB14_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and32_trunc_8_sign:
; CHECK-X86: # %bb.0:
Recommit r343499 "[X86] Enable load folding in the test shrinking code" Original message: This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669 llvm-svn: 343540
2018-10-02 05:35:28 +08:00
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: jg .LBB14_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB14_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 128
%r = trunc i32 %t to i8
%s = icmp sle i8 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
define void @and64_trunc_8_sign(i64 %x) nounwind {
; CHECK-LINUX64-LABEL: and64_trunc_8_sign:
; CHECK-LINUX64: # %bb.0:
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-LINUX64-NEXT: testb $-128, %dil
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-NEXT: jg .LBB15_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB15_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and64_trunc_8_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-WIN32-64-NEXT: testb $-128, %cl
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB15_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB15_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and64_trunc_8_sign:
; CHECK-X86: # %bb.0:
Recommit r343499 "[X86] Enable load folding in the test shrinking code" Original message: This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669 llvm-svn: 343540
2018-10-02 05:35:28 +08:00
; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: jg .LBB15_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB15_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 128
%r = trunc i64 %t to i8
%s = icmp sle i8 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
define void @and32_trunc_16_sign(i32 %x) nounwind {
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-LABEL: and32_trunc_16_sign:
; CHECK-LINUX64: # %bb.0:
Revert r343499 and r343498. X86 test improvements There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize. I'll be adding more test cases and trying to find a fix. llvm-svn: 343516
2018-10-02 02:40:44 +08:00
; CHECK-LINUX64-NEXT: andl $32768, %edi # imm = 0x8000
; CHECK-LINUX64-NEXT: testw %di, %di
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-NEXT: jg .LBB16_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB16_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and32_trunc_16_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Revert r343499 and r343498. X86 test improvements There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize. I'll be adding more test cases and trying to find a fix. llvm-svn: 343516
2018-10-02 02:40:44 +08:00
; CHECK-WIN32-64-NEXT: andl $32768, %ecx # imm = 0x8000
; CHECK-WIN32-64-NEXT: testw %cx, %cx
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB16_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB16_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and32_trunc_16_sign:
; CHECK-X86: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; CHECK-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-X86-NEXT: andl $32768, %eax # imm = 0x8000
Revert r343499 and r343498. X86 test improvements There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize. I'll be adding more test cases and trying to find a fix. llvm-svn: 343516
2018-10-02 02:40:44 +08:00
; CHECK-X86-NEXT: testw %ax, %ax
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: jg .LBB16_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB16_2: # %no
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32768
%r = trunc i32 %t to i16
%s = icmp sle i16 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
define void @and32_trunc_16_sign_minsize(i32 %x) minsize nounwind {
; CHECK-LINUX64-LABEL: and32_trunc_16_sign_minsize:
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64: # %bb.0:
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-LINUX64-NEXT: testw $-32768, %di # imm = 0x8000
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-LINUX64-NEXT: jg .LBB17_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB17_2: # %no
; CHECK-LINUX64-NEXT: retq
;
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-WIN32-64-LABEL: and32_trunc_16_sign_minsize:
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-WIN32-64-NEXT: testw $-32768, %cx # imm = 0x8000
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB17_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB17_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-X86-LABEL: and32_trunc_16_sign_minsize:
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86: # %bb.0:
[DAGCombiner] re-enable truncation of binops This is effectively re-committing the changes from: rL347917 (D54640) rL348195 (D55126) ...which were effectively reverted here: rL348604 ...because the code had a bug that could induce infinite looping or eventual out-of-memory compilation. The bug was that this code did not guard against transforming opaque constants. More details are in the post-commit mailing list thread for r347917. A reduced test for that is included in the x86 bool-math.ll file. (I wasn't able to reduce a PPC backend test for this, but it was almost the same pattern.) Original commit message for r347917: The motivating case for this is shown in: https://bugs.llvm.org/show_bug.cgi?id=32023 and the corresponding rot16.ll regression tests. Because x86 scalar shift amounts are i8 values, we can end up with trunc-binop-trunc sequences that don't get folded in IR. As the TODO comments suggest, there will be regressions if we extend this (for x86, we mostly seem to be missing LEA opportunities, but there are likely vector folds missing too). I think those should be considered existing bugs because this is the same transform that we do as an IR canonicalization in instcombine. We just need more tests to make those visible independent of this patch. llvm-svn: 348706
2018-12-09 00:07:38 +08:00
; CHECK-X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-X86-NEXT: testw $-32768, %ax # imm = 0x8000
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: jg .LBB17_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB17_2: # %no
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-X86-NEXT: retl
%t = and i32 %x, 32768
%r = trunc i32 %t to i16
%s = icmp sle i16 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
define void @and64_trunc_16_sign(i64 %x) nounwind {
; CHECK-LINUX64-LABEL: and64_trunc_16_sign:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: andl $32768, %edi # imm = 0x8000
; CHECK-LINUX64-NEXT: testw %di, %di
; CHECK-LINUX64-NEXT: jg .LBB18_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB18_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and64_trunc_16_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: andl $32768, %ecx # imm = 0x8000
; CHECK-WIN32-64-NEXT: testw %cx, %cx
; CHECK-WIN32-64-NEXT: jg .LBB18_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB18_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and64_trunc_16_sign:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: movl $32768, %eax # imm = 0x8000
; CHECK-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; CHECK-X86-NEXT: testw %ax, %ax
; CHECK-X86-NEXT: jg .LBB18_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB18_2: # %no
[X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used. The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this. llvm-svn: 343355
2018-09-29 03:06:28 +08:00
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32768
%r = trunc i64 %t to i16
%s = icmp sle i16 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
define void @and64_trunc_16_sign_minsize(i64 %x) minsize nounwind {
; CHECK-LINUX64-LABEL: and64_trunc_16_sign_minsize:
; CHECK-LINUX64: # %bb.0:
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-LINUX64-NEXT: testw $-32768, %di # imm = 0x8000
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-LINUX64-NEXT: jg .LBB19_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB19_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and64_trunc_16_sign_minsize:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated." This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used. Original commit message: Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive. It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch. llvm-svn: 343539
2018-10-02 05:35:26 +08:00
; CHECK-WIN32-64-NEXT: testw $-32768, %cx # imm = 0x8000
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-WIN32-64-NEXT: jg .LBB19_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB19_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and64_trunc_16_sign_minsize:
; CHECK-X86: # %bb.0:
Recommit r343499 "[X86] Enable load folding in the test shrinking code" Original message: This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669 llvm-svn: 343540
2018-10-02 05:35:28 +08:00
; CHECK-X86-NEXT: testw $-32768, {{[0-9]+}}(%esp) # imm = 0x8000
[X86] Add more test shrinking with truncate and sign bit usage tests. NFC llvm-svn: 343519
2018-10-02 02:52:19 +08:00
; CHECK-X86-NEXT: jg .LBB19_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB19_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 32768
%r = trunc i64 %t to i16
%s = icmp sle i16 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
define void @and64_trunc_32_sign(i64 %x) nounwind {
; CHECK-LINUX64-LABEL: and64_trunc_32_sign:
; CHECK-LINUX64: # %bb.0:
; CHECK-LINUX64-NEXT: testl $-2147483648, %edi # imm = 0x80000000
; CHECK-LINUX64-NEXT: jg .LBB20_2
; CHECK-LINUX64-NEXT: # %bb.1: # %yes
; CHECK-LINUX64-NEXT: pushq %rax
; CHECK-LINUX64-NEXT: callq bar
; CHECK-LINUX64-NEXT: popq %rax
; CHECK-LINUX64-NEXT: .LBB20_2: # %no
; CHECK-LINUX64-NEXT: retq
;
; CHECK-WIN32-64-LABEL: and64_trunc_32_sign:
; CHECK-WIN32-64: # %bb.0:
; CHECK-WIN32-64-NEXT: subq $40, %rsp
; CHECK-WIN32-64-NEXT: testl $-2147483648, %ecx # imm = 0x80000000
; CHECK-WIN32-64-NEXT: jg .LBB20_2
; CHECK-WIN32-64-NEXT: # %bb.1: # %yes
; CHECK-WIN32-64-NEXT: callq bar
; CHECK-WIN32-64-NEXT: .LBB20_2: # %no
; CHECK-WIN32-64-NEXT: addq $40, %rsp
; CHECK-WIN32-64-NEXT: retq
;
; CHECK-X86-LABEL: and64_trunc_32_sign:
; CHECK-X86: # %bb.0:
; CHECK-X86-NEXT: testl $-2147483648, {{[0-9]+}}(%esp) # imm = 0x80000000
; CHECK-X86-NEXT: jg .LBB20_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
; CHECK-X86-NEXT: .LBB20_2: # %no
; CHECK-X86-NEXT: retl
%t = and i64 %x, 2147483648
%r = trunc i64 %t to i32
%s = icmp sle i32 %r, 0
br i1 %s, label %yes, label %no
yes:
call void @bar()
ret void
no:
ret void
}
Add an x86 peep that narrows TEST instructions to forms that use a smaller encoding. These kinds of patterns are very frequent in sqlite3, for example. llvm-svn: 79439
2009-08-20 02:16:17 +08:00
declare void @bar()