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llvm-project/llvm/test/CodeGen/X86/slow-incdec.ll

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[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=-slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=INCDEC %s
; RUN: llc -mtriple=i386-unknown-linux-gnu -mattr=+slow-incdec < %s | FileCheck -check-prefix=CHECK -check-prefix=ADD %s
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @inc(i32 %x) {
; INCDEC-LABEL: inc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; INCDEC: # %bb.0:
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl %eax
; INCDEC-NEXT: retl
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
;
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; ADD-LABEL: inc:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ADD: # %bb.0:
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, %eax
; ADD-NEXT: retl
%r = add i32 %x, 1
ret i32 %r
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
}
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @dec(i32 %x) {
; INCDEC-LABEL: dec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; INCDEC: # %bb.0:
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: decl %eax
; INCDEC-NEXT: retl
;
; ADD-LABEL: dec:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; ADD: # %bb.0:
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $-1, %eax
; ADD-NEXT: retl
%r = add i32 %x, -1
ret i32 %r
}
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @inc_size(i32 %x) optsize {
[X86] Don't disable slow INC/DEC if optimizing for size Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
2017-09-10 01:11:59 +08:00
; CHECK-LABEL: inc_size:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Don't disable slow INC/DEC if optimizing for size Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
2017-09-10 01:11:59 +08:00
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: incl %eax
; CHECK-NEXT: retl
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
%r = add i32 %x, 1
ret i32 %r
[X86] Use ADD/SUB instead of INC/DEC for Haswell and Broadwell CPUs Differential Revision: http://reviews.llvm.org/D5934 llvm-svn: 222141
2014-11-18 00:17:51 +08:00
}
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
define i32 @dec_size(i32 %x) optsize {
[X86] Don't disable slow INC/DEC if optimizing for size Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
2017-09-10 01:11:59 +08:00
; CHECK-LABEL: dec_size:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Don't disable slow INC/DEC if optimizing for size Summary: Just because INC/DEC is a little slow on some processors doesn't mean we shouldn't prefer it when optimizing for size. This appears to match gcc behavior. Reviewers: chandlerc, zvi, RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37177 llvm-svn: 312866
2017-09-10 01:11:59 +08:00
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: decl %eax
; CHECK-NEXT: retl
[X86] Simplify the slow-incdec test and add test cases with optsize. I think we want to consider using inc/dec with optsize. llvm-svn: 312804
2017-09-09 01:33:54 +08:00
%r = add i32 %x, -1
ret i32 %r
}
[x86] add test for missed opportunity to use 'inc'; NFC llvm-svn: 352805
2019-02-01 06:33:11 +08:00
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
declare void @other(i32* ) nounwind;
define void @cond_ae_to_cond_ne(i32* %p) nounwind {
[X86] Lower ISD::UADDO to use the Z flag instead of C flag when the RHS is a constant 1 to encourage INC formation. Summary: Add an additional combine to combineCarryThroughADD to reverse it back to the C flag to avoid regressions. I believe this catches the cases that D57547 got. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57637 llvm-svn: 352984
2019-02-03 15:25:06 +08:00
; INCDEC-LABEL: cond_ae_to_cond_ne:
; INCDEC: # %bb.0: # %entry
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl (%eax)
; INCDEC-NEXT: jne .LBB4_1
; INCDEC-NEXT: # %bb.2: # %if.end4
; INCDEC-NEXT: jmp other # TAILCALL
; INCDEC-NEXT: .LBB4_1: # %return
; INCDEC-NEXT: retl
;
; ADD-LABEL: cond_ae_to_cond_ne:
; ADD: # %bb.0: # %entry
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, (%eax)
; ADD-NEXT: jne .LBB4_1
; ADD-NEXT: # %bb.2: # %if.end4
; ADD-NEXT: jmp other # TAILCALL
; ADD-NEXT: .LBB4_1: # %return
; ADD-NEXT: retl
[x86] add test for missed opportunity to use 'inc'; NFC llvm-svn: 352805
2019-02-01 06:33:11 +08:00
entry:
%t0 = load i32, i32* %p, align 8
%add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %t0, i32 1)
%inc = extractvalue { i32, i1 } %add_ov, 0
store i32 %inc, i32* %p, align 8
%ov = extractvalue { i32, i1 } %add_ov, 1
br i1 %ov, label %if.end4, label %return
if.end4:
tail call void @other(i32* %p) nounwind
br label %return
return:
ret void
}
[x86] add test for missed opportunity to use 'inc'; NFC Another pattern exposed in D57516. llvm-svn: 352820
2019-02-01 07:46:58 +08:00
@a = common global i8 0, align 1
@d = common global i8 0, align 1
declare void @external_a()
declare void @external_b()
declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8)
[x86] adjust test to show both add/inc options; NFC If we're optimizing for size, that overrides the subtarget feature, so we would always produce 'inc' if we matched this pattern. llvm-svn: 352821
2019-02-01 08:07:20 +08:00
define void @test_tail_call(i32* %ptr) nounwind {
[X86] Lower ISD::UADDO to use the Z flag instead of C flag when the RHS is a constant 1 to encourage INC formation. Summary: Add an additional combine to combineCarryThroughADD to reverse it back to the C flag to avoid regressions. I believe this catches the cases that D57547 got. Reviewers: RKSimon, spatel Reviewed By: spatel Subscribers: javed.absar, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57637 llvm-svn: 352984
2019-02-03 15:25:06 +08:00
; INCDEC-LABEL: test_tail_call:
; INCDEC: # %bb.0: # %entry
; INCDEC-NEXT: movl {{[0-9]+}}(%esp), %eax
; INCDEC-NEXT: incl (%eax)
; INCDEC-NEXT: setne %al
; INCDEC-NEXT: incb a
; INCDEC-NEXT: sete d
; INCDEC-NEXT: testb %al, %al
; INCDEC-NEXT: jne .LBB5_2
; INCDEC-NEXT: # %bb.1: # %then
; INCDEC-NEXT: jmp external_a # TAILCALL
; INCDEC-NEXT: .LBB5_2: # %else
; INCDEC-NEXT: jmp external_b # TAILCALL
;
; ADD-LABEL: test_tail_call:
; ADD: # %bb.0: # %entry
; ADD-NEXT: movl {{[0-9]+}}(%esp), %eax
; ADD-NEXT: addl $1, (%eax)
; ADD-NEXT: setne %al
; ADD-NEXT: addb $1, a
; ADD-NEXT: sete d
; ADD-NEXT: testb %al, %al
; ADD-NEXT: jne .LBB5_2
; ADD-NEXT: # %bb.1: # %then
; ADD-NEXT: jmp external_a # TAILCALL
; ADD-NEXT: .LBB5_2: # %else
; ADD-NEXT: jmp external_b # TAILCALL
[x86] add test for missed opportunity to use 'inc'; NFC Another pattern exposed in D57516. llvm-svn: 352820
2019-02-01 07:46:58 +08:00
entry:
%val = load i32, i32* %ptr
%add_ov = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val, i32 1)
%inc = extractvalue { i32, i1 } %add_ov, 0
store i32 %inc, i32* %ptr
%cmp = extractvalue { i32, i1 } %add_ov, 1
%aval = load volatile i8, i8* @a
%add_ov2 = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %aval, i8 1)
%inc2 = extractvalue { i8, i1 } %add_ov2, 0
store volatile i8 %inc2, i8* @a
%cmp2 = extractvalue { i8, i1 } %add_ov2, 1
%conv5 = zext i1 %cmp2 to i8
store i8 %conv5, i8* @d
br i1 %cmp, label %then, label %else
then:
tail call void @external_a()
ret void
else:
tail call void @external_b()
ret void
}