2015-11-11 16:00:39 +08:00
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/*===---- avx512vldqintrin.h - AVX512VL and AVX512DQ intrinsics ------------===
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2015-04-30 17:24:29 +08:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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2015-09-12 10:55:19 +08:00
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2015-04-30 17:24:29 +08:00
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#ifndef __IMMINTRIN_H
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#error "Never use <avx512vldqintrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __AVX512VLDQINTRIN_H
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#define __AVX512VLDQINTRIN_H
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2015-06-17 15:09:20 +08:00
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/* Define the default attributes for the functions in this file. */
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2015-06-30 21:36:19 +08:00
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#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512dq")))
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2015-04-30 17:24:29 +08:00
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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2015-04-30 17:24:29 +08:00
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_mm256_mullo_epi64 (__m256i __A, __m256i __B) {
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2016-06-04 13:43:41 +08:00
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return (__m256i) ((__v4du) __A * (__v4du) __B);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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2016-09-04 03:19:49 +08:00
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_mm256_mask_mullo_epi64(__m256i __W, __mmask8 __U, __m256i __A, __m256i __B) {
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return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
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(__v4di)_mm256_mullo_epi64(__A, __B),
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(__v4di)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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2016-09-04 03:19:49 +08:00
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_mm256_maskz_mullo_epi64(__mmask8 __U, __m256i __A, __m256i __B) {
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return (__m256i)__builtin_ia32_selectq_256((__mmask8)__U,
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(__v4di)_mm256_mullo_epi64(__A, __B),
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(__v4di)_mm256_setzero_si256());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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2015-04-30 17:24:29 +08:00
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_mm_mullo_epi64 (__m128i __A, __m128i __B) {
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2016-06-04 13:43:41 +08:00
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return (__m128i) ((__v2du) __A * (__v2du) __B);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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2016-09-04 03:19:49 +08:00
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_mm_mask_mullo_epi64(__m128i __W, __mmask8 __U, __m128i __A, __m128i __B) {
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return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
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(__v2di)_mm_mullo_epi64(__A, __B),
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(__v2di)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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2016-09-04 03:19:49 +08:00
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_mm_maskz_mullo_epi64(__mmask8 __U, __m128i __A, __m128i __B) {
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return (__m128i)__builtin_ia32_selectq_128((__mmask8)__U,
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(__v2di)_mm_mullo_epi64(__A, __B),
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(__v2di)_mm_setzero_si128());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_andnot_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_andnot_pd(__A, __B),
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(__v4df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_andnot_pd(__mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_andnot_pd(__A, __B),
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(__v4df)_mm256_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_mask_andnot_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_andnot_pd(__A, __B),
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(__v2df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_maskz_andnot_pd(__mmask8 __U, __m128d __A, __m128d __B) {
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_andnot_pd(__A, __B),
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(__v2df)_mm_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_andnot_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_andnot_ps(__A, __B),
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(__v8sf)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_andnot_ps(__mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_andnot_ps(__A, __B),
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(__v8sf)_mm256_setzero_ps());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_mask_andnot_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_andnot_ps(__A, __B),
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(__v4sf)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_maskz_andnot_ps(__mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_andnot_ps(__A, __B),
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(__v4sf)_mm_setzero_ps());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_and_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_and_pd(__A, __B),
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(__v4df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_and_pd(__mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_and_pd(__A, __B),
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(__v4df)_mm256_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_mask_and_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_and_pd(__A, __B),
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(__v2df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_maskz_and_pd(__mmask8 __U, __m128d __A, __m128d __B) {
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_and_pd(__A, __B),
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(__v2df)_mm_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_and_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_and_ps(__A, __B),
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(__v8sf)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_and_ps(__mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_and_ps(__A, __B),
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(__v8sf)_mm256_setzero_ps());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_mask_and_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_and_ps(__A, __B),
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(__v4sf)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_maskz_and_ps(__mmask8 __U, __m128 __A, __m128 __B) {
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return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
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(__v4sf)_mm_and_ps(__A, __B),
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(__v4sf)_mm_setzero_ps());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_xor_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_xor_pd(__A, __B),
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(__v4df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_xor_pd(__mmask8 __U, __m256d __A, __m256d __B) {
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return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
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(__v4df)_mm256_xor_pd(__A, __B),
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(__v4df)_mm256_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm_mask_xor_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_xor_pd(__A, __B),
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(__v2df)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128d __DEFAULT_FN_ATTRS
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2015-04-30 17:24:29 +08:00
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_mm_maskz_xor_pd (__mmask8 __U, __m128d __A, __m128d __B) {
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2016-08-31 13:38:58 +08:00
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return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
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(__v2df)_mm_xor_pd(__A, __B),
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(__v2df)_mm_setzero_pd());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_mask_xor_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_xor_ps(__A, __B),
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(__v8sf)__W);
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m256 __DEFAULT_FN_ATTRS
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2016-08-31 13:38:58 +08:00
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_mm256_maskz_xor_ps(__mmask8 __U, __m256 __A, __m256 __B) {
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return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
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(__v8sf)_mm256_xor_ps(__A, __B),
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(__v8sf)_mm256_setzero_ps());
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2015-04-30 17:24:29 +08:00
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}
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2015-06-30 21:36:19 +08:00
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static __inline__ __m128 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_mask_xor_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
|
|
|
|
|
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
|
|
|
|
|
(__v4sf)_mm_xor_ps(__A, __B),
|
|
|
|
|
(__v4sf)__W);
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_maskz_xor_ps(__mmask8 __U, __m128 __A, __m128 __B) {
|
|
|
|
|
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
|
|
|
|
|
(__v4sf)_mm_xor_ps(__A, __B),
|
|
|
|
|
(__v4sf)_mm_setzero_ps());
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm256_mask_or_pd(__m256d __W, __mmask8 __U, __m256d __A, __m256d __B) {
|
|
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_or_pd(__A, __B),
|
|
|
|
|
(__v4df)__W);
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm256_maskz_or_pd(__mmask8 __U, __m256d __A, __m256d __B) {
|
|
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_or_pd(__A, __B),
|
|
|
|
|
(__v4df)_mm256_setzero_pd());
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_mask_or_pd(__m128d __W, __mmask8 __U, __m128d __A, __m128d __B) {
|
|
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_or_pd(__A, __B),
|
|
|
|
|
(__v2df)__W);
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_maskz_or_pd(__mmask8 __U, __m128d __A, __m128d __B) {
|
|
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_or_pd(__A, __B),
|
|
|
|
|
(__v2df)_mm_setzero_pd());
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m256 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm256_mask_or_ps(__m256 __W, __mmask8 __U, __m256 __A, __m256 __B) {
|
|
|
|
|
return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
|
|
|
|
|
(__v8sf)_mm256_or_ps(__A, __B),
|
|
|
|
|
(__v8sf)__W);
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m256 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm256_maskz_or_ps(__mmask8 __U, __m256 __A, __m256 __B) {
|
|
|
|
|
return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
|
|
|
|
|
(__v8sf)_mm256_or_ps(__A, __B),
|
|
|
|
|
(__v8sf)_mm256_setzero_ps());
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_mask_or_ps(__m128 __W, __mmask8 __U, __m128 __A, __m128 __B) {
|
|
|
|
|
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
|
|
|
|
|
(__v4sf)_mm_or_ps(__A, __B),
|
|
|
|
|
(__v4sf)__W);
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
2016-08-31 13:38:58 +08:00
|
|
|
_mm_maskz_or_ps(__mmask8 __U, __m128 __A, __m128 __B) {
|
|
|
|
|
return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
|
|
|
|
|
(__v4sf)_mm_or_ps(__A, __B),
|
|
|
|
|
(__v4sf)_mm_setzero_ps());
|
2015-04-30 17:24:29 +08:00
|
|
|
}
|
|
|
|
|
|
2015-08-02 20:43:08 +08:00
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtpd_epi64 (__m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtpd_epi64 (__m128i __W, __mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtpd_epi64 (__mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtpd_epi64 (__m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtpd_epi64 (__mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtpd_epu64 (__m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtpd_epu64 (__m128i __W, __mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtpd_epu64 (__mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtpd_epu64 (__m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtpd_epu64 (__mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtps_epi64 (__m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtps_epi64 (__m128i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtps_epi64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtps_epi64 (__m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtps_epi64 (__m256i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtps_epi64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtps_epu64 (__m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtps_epu64 (__m128i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtps_epu64 (__m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtps_epu64 (__m256i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtps_epu64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtepi64_pd (__m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_convertvector((__v2di)__A, __v2df);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtepi64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_cvtepi64_pd(__A),
|
|
|
|
|
(__v2df)__W);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtepi64_pd (__mmask8 __U, __m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_cvtepi64_pd(__A),
|
|
|
|
|
(__v2df)_mm_setzero_pd());
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtepi64_pd (__m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_convertvector((__v4di)__A, __v4df);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtepi64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_cvtepi64_pd(__A),
|
|
|
|
|
(__v4df)__W);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtepi64_pd (__mmask8 __U, __m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_cvtepi64_pd(__A),
|
|
|
|
|
(__v4df)_mm256_setzero_pd());
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtepi64_ps (__m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtepi64_ps (__m128 __W, __mmask8 __U, __m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtepi64_ps (__mmask8 __U, __m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtepi64_ps (__m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtepi64_ps (__m128 __W, __mmask8 __U, __m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtepi64_ps (__mmask8 __U, __m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvttpd_epi64 (__m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvttpd_epi64 (__m128i __W, __mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvttpd_epi64 (__mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2qq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvttpd_epi64 (__m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvttpd_epi64 (__m256i __W, __mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvttpd_epi64 (__mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2qq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvttpd_epu64 (__m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvttpd_epu64 (__m128i __W, __mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvttpd_epu64 (__mmask8 __U, __m128d __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttpd2uqq128_mask ((__v2df) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvttpd_epu64 (__m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvttpd_epu64 (__m256i __W, __mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvttpd_epu64 (__mmask8 __U, __m256d __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttpd2uqq256_mask ((__v4df) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvttps_epi64 (__m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvttps_epi64 (__m128i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvttps_epi64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2qq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvttps_epi64 (__m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvttps_epi64 (__m256i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvttps_epi64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2qq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvttps_epu64 (__m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvttps_epu64 (__m128i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m128i) __builtin_ia32_cvttps2uqq128_mask ((__v4sf) __A,
|
|
|
|
|
(__v2di) _mm_setzero_si128(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvttps_epu64 (__m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvttps_epu64 (__m256i __W, __mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvttps_epu64 (__mmask8 __U, __m128 __A) {
|
|
|
|
|
return (__m256i) __builtin_ia32_cvttps2uqq256_mask ((__v4sf) __A,
|
|
|
|
|
(__v4di) _mm256_setzero_si256(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtepu64_pd (__m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_convertvector((__v2du)__A, __v2df);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtepu64_pd (__m128d __W, __mmask8 __U, __m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_cvtepu64_pd(__A),
|
|
|
|
|
(__v2df)__W);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtepu64_pd (__mmask8 __U, __m128i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m128d)__builtin_ia32_selectpd_128((__mmask8)__U,
|
|
|
|
|
(__v2df)_mm_cvtepu64_pd(__A),
|
|
|
|
|
(__v2df)_mm_setzero_pd());
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtepu64_pd (__m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_convertvector((__v4du)__A, __v4df);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtepu64_pd (__m256d __W, __mmask8 __U, __m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_cvtepu64_pd(__A),
|
|
|
|
|
(__v4df)__W);
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtepu64_pd (__mmask8 __U, __m256i __A) {
|
2018-05-22 04:19:17 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__U,
|
|
|
|
|
(__v4df)_mm256_cvtepu64_pd(__A),
|
|
|
|
|
(__v4df)_mm256_setzero_pd());
|
2015-08-02 20:43:08 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_cvtepu64_ps (__m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_mask_cvtepu64_ps (__m128 __W, __mmask8 __U, __m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_maskz_cvtepu64_ps (__mmask8 __U, __m128i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps128_mask ((__v2di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_cvtepu64_ps (__m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) -1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_cvtepu64_ps (__m128 __W, __mmask8 __U, __m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) __W,
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_cvtepu64_ps (__mmask8 __U, __m256i __A) {
|
|
|
|
|
return (__m128) __builtin_ia32_cvtuqq2ps256_mask ((__v4di) __A,
|
|
|
|
|
(__v4sf) _mm_setzero_ps(),
|
|
|
|
|
(__mmask8) __U);
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-17 12:41:46 +08:00
|
|
|
#define _mm_range_pd(A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
|
|
|
|
|
(__v2df)(__m128d)(B), (int)(C), \
|
|
|
|
|
(__v2df)_mm_setzero_pd(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm_mask_range_pd(W, U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
|
|
|
|
|
(__v2df)(__m128d)(B), (int)(C), \
|
|
|
|
|
(__v2df)(__m128d)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_maskz_range_pd(U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_rangepd128_mask((__v2df)(__m128d)(A), \
|
|
|
|
|
(__v2df)(__m128d)(B), (int)(C), \
|
|
|
|
|
(__v2df)_mm_setzero_pd(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_range_pd(A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
|
|
|
|
|
(__v4df)(__m256d)(B), (int)(C), \
|
|
|
|
|
(__v4df)_mm256_setzero_pd(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_range_pd(W, U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
|
|
|
|
|
(__v4df)(__m256d)(B), (int)(C), \
|
|
|
|
|
(__v4df)(__m256d)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_maskz_range_pd(U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_rangepd256_mask((__v4df)(__m256d)(A), \
|
|
|
|
|
(__v4df)(__m256d)(B), (int)(C), \
|
|
|
|
|
(__v4df)_mm256_setzero_pd(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_range_ps(A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
|
|
|
|
|
(__v4sf)(__m128)(B), (int)(C), \
|
|
|
|
|
(__v4sf)_mm_setzero_ps(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm_mask_range_ps(W, U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
|
|
|
|
|
(__v4sf)(__m128)(B), (int)(C), \
|
|
|
|
|
(__v4sf)(__m128)(W), (__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_maskz_range_ps(U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_rangeps128_mask((__v4sf)(__m128)(A), \
|
|
|
|
|
(__v4sf)(__m128)(B), (int)(C), \
|
|
|
|
|
(__v4sf)_mm_setzero_ps(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_range_ps(A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
|
|
|
|
|
(__v8sf)(__m256)(B), (int)(C), \
|
|
|
|
|
(__v8sf)_mm256_setzero_ps(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_range_ps(W, U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
|
|
|
|
|
(__v8sf)(__m256)(B), (int)(C), \
|
|
|
|
|
(__v8sf)(__m256)(W), (__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_maskz_range_ps(U, A, B, C) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_rangeps256_mask((__v8sf)(__m256)(A), \
|
|
|
|
|
(__v8sf)(__m256)(B), (int)(C), \
|
|
|
|
|
(__v8sf)_mm256_setzero_ps(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_reduce_pd(A, B) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
|
|
|
|
|
(__v2df)_mm_setzero_pd(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm_mask_reduce_pd(W, U, A, B) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
|
|
|
|
|
(__v2df)(__m128d)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_maskz_reduce_pd(U, A, B) __extension__ ({ \
|
|
|
|
|
(__m128d)__builtin_ia32_reducepd128_mask((__v2df)(__m128d)(A), (int)(B), \
|
|
|
|
|
(__v2df)_mm_setzero_pd(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_reduce_pd(A, B) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
|
|
|
|
|
(__v4df)_mm256_setzero_pd(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_reduce_pd(W, U, A, B) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
|
|
|
|
|
(__v4df)(__m256d)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_maskz_reduce_pd(U, A, B) __extension__ ({ \
|
|
|
|
|
(__m256d)__builtin_ia32_reducepd256_mask((__v4df)(__m256d)(A), (int)(B), \
|
|
|
|
|
(__v4df)_mm256_setzero_pd(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_reduce_ps(A, B) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
|
|
|
|
|
(__v4sf)_mm_setzero_ps(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm_mask_reduce_ps(W, U, A, B) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
|
|
|
|
|
(__v4sf)(__m128)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_maskz_reduce_ps(U, A, B) __extension__ ({ \
|
|
|
|
|
(__m128)__builtin_ia32_reduceps128_mask((__v4sf)(__m128)(A), (int)(B), \
|
|
|
|
|
(__v4sf)_mm_setzero_ps(), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_reduce_ps(A, B) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
|
|
|
|
|
(__v8sf)_mm256_setzero_ps(), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_reduce_ps(W, U, A, B) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
|
|
|
|
|
(__v8sf)(__m256)(W), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_maskz_reduce_ps(U, A, B) __extension__ ({ \
|
|
|
|
|
(__m256)__builtin_ia32_reduceps256_mask((__v8sf)(__m256)(A), (int)(B), \
|
|
|
|
|
(__v8sf)_mm256_setzero_ps(), \
|
|
|
|
|
(__mmask8)(U)); })
|
2015-08-02 20:43:08 +08:00
|
|
|
|
2016-04-13 18:49:37 +08:00
|
|
|
static __inline__ __mmask8 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_movepi32_mask (__m128i __A)
|
|
|
|
|
{
|
|
|
|
|
return (__mmask8) __builtin_ia32_cvtd2mask128 ((__v4si) __A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __mmask8 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_movepi32_mask (__m256i __A)
|
|
|
|
|
{
|
|
|
|
|
return (__mmask8) __builtin_ia32_cvtd2mask256 ((__v8si) __A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_movm_epi32 (__mmask8 __A)
|
|
|
|
|
{
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtmask2d128 (__A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_movm_epi32 (__mmask8 __A)
|
|
|
|
|
{
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtmask2d256 (__A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m128i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_movm_epi64 (__mmask8 __A)
|
|
|
|
|
{
|
|
|
|
|
return (__m128i) __builtin_ia32_cvtmask2q128 (__A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_movm_epi64 (__mmask8 __A)
|
|
|
|
|
{
|
|
|
|
|
return (__m256i) __builtin_ia32_cvtmask2q256 (__A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __mmask8 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm_movepi64_mask (__m128i __A)
|
|
|
|
|
{
|
|
|
|
|
return (__mmask8) __builtin_ia32_cvtq2mask128 ((__v2di) __A);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __mmask8 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_movepi64_mask (__m256i __A)
|
|
|
|
|
{
|
|
|
|
|
return (__mmask8) __builtin_ia32_cvtq2mask256 ((__v4di) __A);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-13 20:58:01 +08:00
|
|
|
static __inline__ __m256 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_broadcast_f32x2 (__m128 __A)
|
|
|
|
|
{
|
2017-08-31 00:15:12 +08:00
|
|
|
return (__m256)__builtin_shufflevector((__v4sf)__A,
|
|
|
|
|
(__v4sf)_mm_undefined_ps(),
|
|
|
|
|
0, 1, 0, 1, 0, 1, 0, 1);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_mask_broadcast_f32x2 (__m256 __O, __mmask8 __M, __m128 __A)
|
|
|
|
|
{
|
2017-08-31 00:15:12 +08:00
|
|
|
return (__m256)__builtin_ia32_selectps_256((__mmask8)__M,
|
|
|
|
|
(__v8sf)_mm256_broadcast_f32x2(__A),
|
|
|
|
|
(__v8sf)__O);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256 __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_broadcast_f32x2 (__mmask8 __M, __m128 __A)
|
|
|
|
|
{
|
2017-08-31 00:15:12 +08:00
|
|
|
return (__m256)__builtin_ia32_selectps_256((__mmask8)__M,
|
|
|
|
|
(__v8sf)_mm256_broadcast_f32x2(__A),
|
|
|
|
|
(__v8sf)_mm256_setzero_ps());
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
2017-01-18 10:17:10 +08:00
|
|
|
_mm256_broadcast_f64x2(__m128d __A)
|
2016-04-13 20:58:01 +08:00
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
|
|
return (__m256d)__builtin_shufflevector((__v2df)__A, (__v2df)__A,
|
|
|
|
|
0, 1, 0, 1);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static __inline__ __m256d __DEFAULT_FN_ATTRS
|
2017-01-18 10:17:10 +08:00
|
|
|
_mm256_mask_broadcast_f64x2(__m256d __O, __mmask8 __M, __m128d __A)
|
2016-04-13 20:58:01 +08:00
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__M,
|
|
|
|
|
(__v4df)_mm256_broadcast_f64x2(__A),
|
|
|
|
|
(__v4df)__O);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
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|
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static __inline__ __m256d __DEFAULT_FN_ATTRS
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|
_mm256_maskz_broadcast_f64x2 (__mmask8 __M, __m128d __A)
|
|
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
|
|
return (__m256d)__builtin_ia32_selectpd_256((__mmask8)__M,
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|
(__v4df)_mm256_broadcast_f64x2(__A),
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|
(__v4df)_mm256_setzero_pd());
|
2016-04-13 20:58:01 +08:00
|
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|
}
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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_mm_broadcast_i32x2 (__m128i __A)
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|
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|
{
|
2017-08-31 00:15:12 +08:00
|
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|
return (__m128i)__builtin_shufflevector((__v4si)__A,
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(__v4si)_mm_undefined_si128(),
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0, 1, 0, 1);
|
2016-04-13 20:58:01 +08:00
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|
}
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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_mm_mask_broadcast_i32x2 (__m128i __O, __mmask8 __M, __m128i __A)
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{
|
2017-08-31 00:15:12 +08:00
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|
return (__m128i)__builtin_ia32_selectd_128((__mmask8)__M,
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(__v4si)_mm_broadcast_i32x2(__A),
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(__v4si)__O);
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2016-04-13 20:58:01 +08:00
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}
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static __inline__ __m128i __DEFAULT_FN_ATTRS
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_mm_maskz_broadcast_i32x2 (__mmask8 __M, __m128i __A)
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{
|
2017-08-31 00:15:12 +08:00
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|
return (__m128i)__builtin_ia32_selectd_128((__mmask8)__M,
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(__v4si)_mm_broadcast_i32x2(__A),
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(__v4si)_mm_setzero_si128());
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2016-04-13 20:58:01 +08:00
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}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_broadcast_i32x2 (__m128i __A)
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|
{
|
2017-08-31 00:15:12 +08:00
|
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|
return (__m256i)__builtin_shufflevector((__v4si)__A,
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(__v4si)_mm_undefined_si128(),
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0, 1, 0, 1, 0, 1, 0, 1);
|
2016-04-13 20:58:01 +08:00
|
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|
}
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static __inline__ __m256i __DEFAULT_FN_ATTRS
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|
_mm256_mask_broadcast_i32x2 (__m256i __O, __mmask8 __M, __m128i __A)
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{
|
2017-08-31 00:15:12 +08:00
|
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|
return (__m256i)__builtin_ia32_selectd_256((__mmask8)__M,
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(__v8si)_mm256_broadcast_i32x2(__A),
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(__v8si)__O);
|
2016-04-13 20:58:01 +08:00
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|
}
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|
static __inline__ __m256i __DEFAULT_FN_ATTRS
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_mm256_maskz_broadcast_i32x2 (__mmask8 __M, __m128i __A)
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{
|
2017-08-31 00:15:12 +08:00
|
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|
return (__m256i)__builtin_ia32_selectd_256((__mmask8)__M,
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(__v8si)_mm256_broadcast_i32x2(__A),
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|
(__v8si)_mm256_setzero_si256());
|
2016-04-13 20:58:01 +08:00
|
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|
}
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|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
2017-01-18 10:17:10 +08:00
|
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|
_mm256_broadcast_i64x2(__m128i __A)
|
2016-04-13 20:58:01 +08:00
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
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|
return (__m256i)__builtin_shufflevector((__v2di)__A, (__v2di)__A,
|
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|
0, 1, 0, 1);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
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|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
2017-01-18 10:17:10 +08:00
|
|
|
_mm256_mask_broadcast_i64x2(__m256i __O, __mmask8 __M, __m128i __A)
|
2016-04-13 20:58:01 +08:00
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
|
|
return (__m256i)__builtin_ia32_selectq_256((__mmask8)__M,
|
|
|
|
|
(__v4di)_mm256_broadcast_i64x2(__A),
|
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|
|
(__v4di)__O);
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
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|
|
|
|
|
|
static __inline__ __m256i __DEFAULT_FN_ATTRS
|
|
|
|
|
_mm256_maskz_broadcast_i64x2 (__mmask8 __M, __m128i __A)
|
|
|
|
|
{
|
2017-01-18 10:17:10 +08:00
|
|
|
return (__m256i)__builtin_ia32_selectq_256((__mmask8)__M,
|
|
|
|
|
(__v4di)_mm256_broadcast_i64x2(__A),
|
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|
|
|
(__v4di)_mm256_setzero_si256());
|
2016-04-13 20:58:01 +08:00
|
|
|
}
|
|
|
|
|
|
2016-05-17 12:41:46 +08:00
|
|
|
#define _mm256_extractf64x2_pd(A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128d)__builtin_shufflevector((__v4df)(__m256d)(A), \
|
|
|
|
|
(__v4df)_mm256_undefined_pd(), \
|
|
|
|
|
((imm) & 1) ? 2 : 0, \
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|
|
|
((imm) & 1) ? 3 : 1); })
|
2016-05-17 12:41:46 +08:00
|
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|
|
|
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|
|
#define _mm256_mask_extractf64x2_pd(W, U, A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128d)__builtin_ia32_selectpd_128((__mmask8)(U), \
|
|
|
|
|
(__v2df)_mm256_extractf64x2_pd((A), (imm)), \
|
|
|
|
|
(__v2df)(W)); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_maskz_extractf64x2_pd(U, A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128d)__builtin_ia32_selectpd_128((__mmask8)(U), \
|
|
|
|
|
(__v2df)_mm256_extractf64x2_pd((A), (imm)), \
|
|
|
|
|
(__v2df)_mm_setzero_pd()); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_extracti64x2_epi64(A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128i)__builtin_shufflevector((__v4di)(__m256i)(A), \
|
|
|
|
|
(__v4di)_mm256_undefined_si256(), \
|
|
|
|
|
((imm) & 1) ? 2 : 0, \
|
|
|
|
|
((imm) & 1) ? 3 : 1); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_mask_extracti64x2_epi64(W, U, A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
|
|
|
|
|
(__v2di)_mm256_extracti64x2_epi64((A), (imm)), \
|
|
|
|
|
(__v2di)(W)); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_maskz_extracti64x2_epi64(U, A, imm) __extension__ ({ \
|
2016-10-31 12:30:56 +08:00
|
|
|
(__m128i)__builtin_ia32_selectq_128((__mmask8)(U), \
|
|
|
|
|
(__v2di)_mm256_extracti64x2_epi64((A), (imm)), \
|
2018-05-31 02:02:11 +08:00
|
|
|
(__v2di)_mm_setzero_si128()); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_insertf64x2(A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256d)__builtin_shufflevector((__v4df)(A), \
|
|
|
|
|
(__v4df)_mm256_castpd128_pd256((__m128d)(B)), \
|
|
|
|
|
((imm) & 0x1) ? 0 : 4, \
|
|
|
|
|
((imm) & 0x1) ? 1 : 5, \
|
|
|
|
|
((imm) & 0x1) ? 4 : 2, \
|
|
|
|
|
((imm) & 0x1) ? 5 : 3); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_mask_insertf64x2(W, U, A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
|
|
|
|
|
(__v4df)_mm256_insertf64x2((A), (B), (imm)), \
|
|
|
|
|
(__v4df)(W)); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_maskz_insertf64x2(U, A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256d)__builtin_ia32_selectpd_256((__mmask8)(U), \
|
|
|
|
|
(__v4df)_mm256_insertf64x2((A), (B), (imm)), \
|
|
|
|
|
(__v4df)_mm256_setzero_pd()); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_inserti64x2(A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256i)__builtin_shufflevector((__v4di)(A), \
|
|
|
|
|
(__v4di)_mm256_castsi128_si256((__m128i)(B)), \
|
|
|
|
|
((imm) & 0x1) ? 0 : 4, \
|
|
|
|
|
((imm) & 0x1) ? 1 : 5, \
|
|
|
|
|
((imm) & 0x1) ? 4 : 2, \
|
|
|
|
|
((imm) & 0x1) ? 5 : 3); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_mask_inserti64x2(W, U, A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
|
|
|
|
|
(__v4di)_mm256_inserti64x2((A), (B), (imm)), \
|
|
|
|
|
(__v4di)(W)); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm256_maskz_inserti64x2(U, A, B, imm) __extension__ ({ \
|
2016-11-01 13:47:56 +08:00
|
|
|
(__m256i)__builtin_ia32_selectq_256((__mmask8)(U), \
|
|
|
|
|
(__v4di)_mm256_inserti64x2((A), (B), (imm)), \
|
|
|
|
|
(__v4di)_mm256_setzero_si256()); })
|
2016-05-17 12:41:46 +08:00
|
|
|
|
|
|
|
|
#define _mm_mask_fpclass_pd_mask(U, A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclasspd128_mask((__v2df)(__m128d)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_fpclass_pd_mask(A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclasspd128_mask((__v2df)(__m128d)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_fpclass_pd_mask(U, A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclasspd256_mask((__v4df)(__m256d)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_fpclass_pd_mask(A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclasspd256_mask((__v4df)(__m256d)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm_mask_fpclass_ps_mask(U, A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclassps128_mask((__v4sf)(__m128)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm_fpclass_ps_mask(A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclassps128_mask((__v4sf)(__m128)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)-1); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_mask_fpclass_ps_mask(U, A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclassps256_mask((__v8sf)(__m256)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
|
|
#define _mm256_fpclass_ps_mask(A, imm) __extension__ ({ \
|
|
|
|
|
(__mmask8)__builtin_ia32_fpclassps256_mask((__v8sf)(__m256)(A), (int)(imm), \
|
|
|
|
|
(__mmask8)-1); })
|
2016-04-25 22:48:23 +08:00
|
|
|
|
2015-06-30 21:36:19 +08:00
|
|
|
#undef __DEFAULT_FN_ATTRS
|
2015-06-17 15:09:20 +08:00
|
|
|
|
2015-04-30 17:24:29 +08:00
|
|
|
#endif
|
