[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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/*===------------- avx512vbmi2intrin.h - VBMI2 intrinsics ------------------===
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*
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __IMMINTRIN_H
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#error "Never use <avx512vbmi2intrin.h> directly; include <immintrin.h> instead."
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#endif
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#ifndef __AVX512VBMI2INTRIN_H
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#define __AVX512VBMI2INTRIN_H
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/* Define the default attributes for the functions in this file. */
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#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2")))
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
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(__v32hi) __S,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_compress_epi16(__mmask32 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi) __D,
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2018-05-31 02:02:11 +08:00
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(__v32hi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_compress_epi8(__m512i __S, __mmask64 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
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(__v64qi) __S,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_compress_epi8(__mmask64 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi) __D,
|
2018-05-31 02:02:11 +08:00
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(__v64qi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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__U);
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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_mm512_mask_compressstoreu_epi16(void *__P, __mmask32 __U, __m512i __D)
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{
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__builtin_ia32_compressstorehi512_mask ((__v32hi *) __P, (__v32hi) __D,
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__U);
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}
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static __inline__ void __DEFAULT_FN_ATTRS
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_mm512_mask_compressstoreu_epi8(void *__P, __mmask64 __U, __m512i __D)
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{
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__builtin_ia32_compressstoreqi512_mask ((__v64qi *) __P, (__v64qi) __D,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_expand_epi16(__m512i __S, __mmask32 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
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(__v32hi) __S,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_expand_epi16(__mmask32 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_expandhi512_mask ((__v32hi) __D,
|
2018-05-31 02:02:11 +08:00
|
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(__v32hi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_expand_epi8(__m512i __S, __mmask64 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
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(__v64qi) __S,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_expand_epi8(__mmask64 __U, __m512i __D)
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{
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return (__m512i) __builtin_ia32_expandqi512_mask ((__v64qi) __D,
|
2018-05-31 02:02:11 +08:00
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|
(__v64qi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
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|
__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_expandloadu_epi16(__m512i __S, __mmask32 __U, void const *__P)
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{
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return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *)__P,
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(__v32hi) __S,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_expandloadu_epi16(__mmask32 __U, void const *__P)
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|
{
|
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|
return (__m512i) __builtin_ia32_expandloadhi512_mask ((const __v32hi *)__P,
|
2018-05-31 02:02:11 +08:00
|
|
|
(__v32hi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
__U);
|
|
|
|
}
|
|
|
|
|
|
|
|
static __inline__ __m512i __DEFAULT_FN_ATTRS
|
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|
|
_mm512_mask_expandloadu_epi8(__m512i __S, __mmask64 __U, void const *__P)
|
|
|
|
{
|
|
|
|
return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *)__P,
|
|
|
|
(__v64qi) __S,
|
|
|
|
__U);
|
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|
|
}
|
|
|
|
|
|
|
|
static __inline__ __m512i __DEFAULT_FN_ATTRS
|
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|
|
_mm512_maskz_expandloadu_epi8(__mmask64 __U, void const *__P)
|
|
|
|
{
|
|
|
|
return (__m512i) __builtin_ia32_expandloadqi512_mask ((const __v64qi *)__P,
|
2018-05-31 02:02:11 +08:00
|
|
|
(__v64qi) _mm512_setzero_si512(),
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
__U);
|
|
|
|
}
|
|
|
|
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|
#define _mm512_mask_shldi_epi64(S, U, A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_vpshldq512_mask((__v8di)(A), \
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|
(__v8di)(B), \
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|
(int)(I), \
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(__v8di)(S), \
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(__mmask8)(U)); })
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|
|
#define _mm512_maskz_shldi_epi64(U, A, B, I) \
|
2018-05-31 02:02:11 +08:00
|
|
|
_mm512_mask_shldi_epi64(_mm512_setzero_si512(), (U), (A), (B), (I))
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
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|
|
|
|
|
#define _mm512_shldi_epi64(A, B, I) \
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_mm512_mask_shldi_epi64(_mm512_undefined(), (__mmask8)(-1), (A), (B), (I))
|
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#define _mm512_mask_shldi_epi32(S, U, A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_vpshldd512_mask((__v16si)(A), \
|
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|
(__v16si)(B), \
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|
|
(int)(I), \
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(__v16si)(S), \
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(__mmask16)(U)); })
|
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|
#define _mm512_maskz_shldi_epi32(U, A, B, I) \
|
2018-05-31 02:02:11 +08:00
|
|
|
_mm512_mask_shldi_epi32(_mm512_setzero_si512(), (U), (A), (B), (I))
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
|
|
|
|
#define _mm512_shldi_epi32(A, B, I) \
|
|
|
|
_mm512_mask_shldi_epi32(_mm512_undefined(), (__mmask16)(-1), (A), (B), (I))
|
|
|
|
|
|
|
|
#define _mm512_mask_shldi_epi16(S, U, A, B, I) __extension__ ({ \
|
|
|
|
(__m512i)__builtin_ia32_vpshldw512_mask((__v32hi)(A), \
|
|
|
|
(__v32hi)(B), \
|
|
|
|
(int)(I), \
|
|
|
|
(__v32hi)(S), \
|
|
|
|
(__mmask32)(U)); })
|
|
|
|
|
|
|
|
#define _mm512_maskz_shldi_epi16(U, A, B, I) \
|
2018-05-31 02:02:11 +08:00
|
|
|
_mm512_mask_shldi_epi16(_mm512_setzero_si512(), (U), (A), (B), (I))
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
|
|
|
|
#define _mm512_shldi_epi16(A, B, I) \
|
|
|
|
_mm512_mask_shldi_epi16(_mm512_undefined(), (__mmask32)(-1), (A), (B), (I))
|
|
|
|
|
|
|
|
#define _mm512_mask_shrdi_epi64(S, U, A, B, I) __extension__ ({ \
|
|
|
|
(__m512i)__builtin_ia32_vpshrdq512_mask((__v8di)(A), \
|
|
|
|
(__v8di)(B), \
|
|
|
|
(int)(I), \
|
|
|
|
(__v8di)(S), \
|
|
|
|
(__mmask8)(U)); })
|
|
|
|
|
|
|
|
#define _mm512_maskz_shrdi_epi64(U, A, B, I) \
|
2018-05-31 02:02:11 +08:00
|
|
|
_mm512_mask_shrdi_epi64(_mm512_setzero_si512(), (U), (A), (B), (I))
|
[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
|
|
|
|
|
|
|
#define _mm512_shrdi_epi64(A, B, I) \
|
|
|
|
_mm512_mask_shrdi_epi64(_mm512_undefined(), (__mmask8)(-1), (A), (B), (I))
|
|
|
|
|
|
|
|
#define _mm512_mask_shrdi_epi32(S, U, A, B, I) __extension__ ({ \
|
|
|
|
(__m512i)__builtin_ia32_vpshrdd512_mask((__v16si)(A), \
|
|
|
|
(__v16si)(B), \
|
|
|
|
(int)(I), \
|
|
|
|
(__v16si)(S), \
|
|
|
|
(__mmask16)(U)); })
|
|
|
|
|
|
|
|
#define _mm512_maskz_shrdi_epi32(U, A, B, I) \
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2018-05-31 02:02:11 +08:00
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_mm512_mask_shrdi_epi32(_mm512_setzero_si512(), (U), (A), (B), (I))
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[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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#define _mm512_shrdi_epi32(A, B, I) \
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_mm512_mask_shrdi_epi32(_mm512_undefined(), (__mmask16)(-1), (A), (B), (I))
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#define _mm512_mask_shrdi_epi16(S, U, A, B, I) __extension__ ({ \
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(__m512i)__builtin_ia32_vpshrdw512_mask((__v32hi)(A), \
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(__v32hi)(B), \
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(int)(I), \
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(__v32hi)(S), \
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(__mmask32)(U)); })
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#define _mm512_maskz_shrdi_epi16(U, A, B, I) \
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2018-05-31 02:02:11 +08:00
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_mm512_mask_shrdi_epi16(_mm512_setzero_si512(), (U), (A), (B), (I))
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[x86][icelake][vbmi2]
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557
llvm-svn: 321487
2017-12-27 19:25:07 +08:00
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#define _mm512_shrdi_epi16(A, B, I) \
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_mm512_mask_shrdi_epi16(_mm512_undefined(), (__mmask32)(-1), (A), (B), (I))
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shldv_epi64(__m512i __S, __mmask8 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvq512_mask ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shldv_epi64(__mmask8 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvq512_maskz ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shldv_epi64(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvq512_mask ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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(__mmask8) -1);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shldv_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvd512_mask ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shldv_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvd512_maskz ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shldv_epi32(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvd512_mask ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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(__mmask16) -1);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shldv_epi16(__m512i __S, __mmask32 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvw512_mask ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shldv_epi16(__mmask32 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvw512_maskz ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shldv_epi16(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshldvw512_mask ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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(__mmask32) -1);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shrdv_epi64(__m512i __S, __mmask8 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvq512_mask ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shrdv_epi64(__mmask8 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvq512_maskz ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shrdv_epi64(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvq512_mask ((__v8di) __S,
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(__v8di) __A,
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(__v8di) __B,
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(__mmask8) -1);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shrdv_epi32(__m512i __S, __mmask16 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvd512_mask ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shrdv_epi32(__mmask16 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvd512_maskz ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shrdv_epi32(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvd512_mask ((__v16si) __S,
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(__v16si) __A,
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(__v16si) __B,
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(__mmask16) -1);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_mask_shrdv_epi16(__m512i __S, __mmask32 __U, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvw512_mask ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_maskz_shrdv_epi16(__mmask32 __U, __m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvw512_maskz ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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__U);
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}
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static __inline__ __m512i __DEFAULT_FN_ATTRS
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_mm512_shrdv_epi16(__m512i __S, __m512i __A, __m512i __B)
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{
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return (__m512i) __builtin_ia32_vpshrdvw512_mask ((__v32hi) __S,
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(__v32hi) __A,
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(__v32hi) __B,
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(__mmask32) -1);
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}
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#undef __DEFAULT_FN_ATTRS
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#endif
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