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llvm-project/llvm/test/CodeGen/PowerPC/vec_fneg.ll

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PowerPC: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. This patch: - Removes -march if the .ll file already has a matching `target triple` directive or -mtriple argument. - In all other cases changes -march=ppc32/-march=ppc64 to -mtriple=ppc32--/-mtriple=ppc64-- See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309754
2017-08-02 06:20:41 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | FileCheck %s -check-prefix=CHECK-NOVSX
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
[PPC] Legalize FNEG on PPC when possible Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
2016-02-27 05:59:44 +08:00
; RUN: -mattr=+altivec -mattr=+vsx | FileCheck %s
PowerPC: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. This patch: - Removes -march if the .ll file already has a matching `target triple` directive or -mtriple argument. - In all other cases changes -march=ppc32/-march=ppc64 to -mtriple=ppc32--/-mtriple=ppc64-- See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309754
2017-08-02 06:20:41 +08:00
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu \
[PPC] Legalize FNEG on PPC when possible Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
2016-02-27 05:59:44 +08:00
; RUN: -mattr=+altivec -mattr=-vsx | FileCheck %s \
; RUN: -check-prefix=CHECK-NOVSX
New test case. llvm-svn: 40587
2007-07-30 15:52:03 +08:00
[PPC] Legalize FNEG on PPC when possible Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
2016-02-27 05:59:44 +08:00
define void @test_float(<4 x float>* %A) {
; CHECK-LABEL: test_float
; CHECK-NOVSX-LABEL: test_float
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp2 = load <4 x float>, <4 x float>* %A
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%tmp3 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp2
New test case. llvm-svn: 40587
2007-07-30 15:52:03 +08:00
store <4 x float> %tmp3, <4 x float>* %A
ret void
[PPC] Legalize FNEG on PPC when possible Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
2016-02-27 05:59:44 +08:00
; CHECK: xvnegsp
; CHECK: blr
; CHECK-NOVSX: vsubfp
; CHECK-NOVSX: blr
}
define void @test_double(<2 x double>* %A) {
; CHECK-LABEL: test_double
; CHECK-NOVSX-LABEL: test_double
%tmp2 = load <2 x double>, <2 x double>* %A
%tmp3 = fsub <2 x double> < double -0.000000e+00, double -0.000000e+00 >, %tmp2
store <2 x double> %tmp3, <2 x double>* %A
ret void
; CHECK: xvnegdp
; CHECK: blr
; CHECK-NOVSX: fneg
; CHECK-NOVSX: fneg
; CHECK-NOVSX: blr
New test case. llvm-svn: 40587
2007-07-30 15:52:03 +08:00
}