forked from OSchip/llvm-project
66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
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# This file tests combining three consecutive ISELs scenario.
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# RUN: llc -ppc-gen-isel=false -run-pass ppc-expand-isel -o - %s | FileCheck %s
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--- |
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%add = add nsw i32 %i, 1
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%cond = select i1 %cmp, i32 %add, i32 %j
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ret i32 %cond
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}
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...
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---
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name: testExpandISEL
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%x3' }
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- { reg: '%x4' }
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- { reg: '%x5' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %x3, %x4, %x5
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%r4 = ADDI %r3, 1
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%cr0 = CMPWI %r3, 0
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%r5 = ISEL %r3, %r4, %cr0gt
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%r3 = ISEL %r4, %r5, %cr0gt
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%r4 = ISEL %r3, %r5, %cr0gt
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; CHECK: BC %cr0gt, %[[TRUE:bb.[0-9]+]]
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; CHECK: %[[FALSE:bb.[0-9]+]]
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; CHECK: %r5 = ORI %r4, 0
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; CHECK: %r3 = ORI %r5, 0
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; CHECK: %r4 = ORI %r5, 0
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; CHECK: B %[[SUCCESSOR:bb.[0-9]+]]
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; CHECK: [[TRUE]]
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; CHECK: %r5 = ADDI %r3, 0
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; CHECK: %r3 = ADDI %r4, 0
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; CHECK: %r4 = ADDI %r3, 0
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%x5 = EXTSW_32_64 %r5
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%x3 = EXTSW_32_64 %r3
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...
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