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llvm-project/llvm/test/CodeGen/X86/pr34177.ll

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[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Regenerate test Split check-prefixes to support a future commit llvm-svn: 351362
2019-01-17 02:00:09 +08:00
; RUN: llc < %s -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512F
; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512VL
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
[X86] Regenerate test Split check-prefixes to support a future commit llvm-svn: 351362
2019-01-17 02:00:09 +08:00
define void @test(<4 x i64> %a, <4 x x86_fp80> %b, <8 x x86_fp80>* %c) local_unnamed_addr {
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-LABEL: test:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: vpextrq $1, %xmm0, %r8
; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [2,3]
; CHECK-NEXT: vmovq %xmm1, %r9
; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm2
; CHECK-NEXT: vmovq %xmm2, %rdx
; CHECK-NEXT: vpextrq $1, %xmm1, %rsi
; CHECK-NEXT: vpextrq $1, %xmm2, %rax
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: vmovq %xmm0, %rcx
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: negq %rcx
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fld1
; CHECK-NEXT: fldz
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fld %st
; CHECK-NEXT: fcmove %st(2), %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: cmpq %rax, %rsi
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fld %st(1)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fcmove %st(3), %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: cmpq %rdx, %r9
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: fld %st(2)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fcmove %st(4), %st
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
; CHECK-NEXT: movl $1, %eax
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: cmpq %r8, %rax
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fxch %st(3)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fcmove %st(4), %st
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
; CHECK-NEXT: fstp %st(4)
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt 70(%rdi)
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt 50(%rdi)
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt 30(%rdi)
; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
; CHECK-NEXT: fstpt 10(%rdi)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fadd %st, %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: fstpt 60(%rdi)
Revert "Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC" This reverts commit f0e85c194ae5e87476bc767304470dec85b6774f. llvm-svn: 333953
2018-06-05 05:20:45 +08:00
; CHECK-NEXT: fxch %st(1)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fadd %st, %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: fstpt 40(%rdi)
Revert "Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC" This reverts commit f0e85c194ae5e87476bc767304470dec85b6774f. llvm-svn: 333953
2018-06-05 05:20:45 +08:00
; CHECK-NEXT: fxch %st(1)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fadd %st, %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: fstpt 20(%rdi)
[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly Summary: When calculating clobbers for MS style inline assembly we fail if the asm clobbers stack top because we print st(0) and try to pass it through the gcc register name check. This was found with when I attempted to make a emms/femms clobber all ST registers. If you use emms/femms in MS inline asm we would try to use st(0) as the clobber name but clang would think that wasn't a valid clobber name. This also matches what objdump disassembly prints. It's also what is printed by gcc -S. Reviewers: RKSimon, rnk, efriedma, spatel, andreadb, lebedev.ri Reviewed By: rnk Subscribers: eraman, gbedwell, lebedev.ri, llvm-commits Differential Revision: https://reviews.llvm.org/D57621 llvm-svn: 352985
2019-02-03 15:53:39 +08:00
; CHECK-NEXT: fadd %st, %st
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
; CHECK-NEXT: fstpt (%rdi)
%1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, %a
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
%2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer
[x86] preserve test intent by removing undef We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we make those fixes. llvm-svn: 332500
2018-05-17 01:58:08 +08:00
%3 = fadd <4 x x86_fp80> %2, %2
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC llvm-svn: 333961
2018-06-05 06:09:26 +08:00
%4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> %b, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
store <8 x x86_fp80> %4, <8 x x86_fp80>* %c, align 16
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC When v1i1 is legal (e.g. AVX512) the legalizer can reach a case where a v1i1 SETCC with an illgeal vector type operand wasn't scalarized (since v1i1 is legal) but its operands does have to be scalarized. This used to assert because SETCC was missing from the vector operand scalarizer. This patch attemps to teach the legalizer to handle these cases by scalazring the operands, converting the node into a scalar SETCC node. Differential revision: https://reviews.llvm.org/D36651 llvm-svn: 311071
2017-08-17 16:06:36 +08:00
unreachable
}