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llvm-project/llvm/test/MC/Mips/micromips/invalid.s

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[mips] Fix the definitions of the EVA instructions Correct their availability to their respective ISAs. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D44209 llvm-svn: 327403
2018-03-13 22:39:44 +08:00
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips,eva 2>%t1
[mips][ias] Range check uimm4 operands and fixed a bug this revealed. Summary: The bug was that the sldi instructions have immediate widths dependant on their element size. So sldi.d has a 1-bit immediate and sldi.b has a 4-bit immediate. All of these were using 4-bit immediates previously. Reviewers: vkalintiris Subscribers: llvm-commits, atanasyan, dsanders Differential Revision: http://reviews.llvm.org/D14018 llvm-svn: 252297
2015-11-06 20:41:43 +08:00
# RUN: FileCheck %s < %t1
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 19:16:56 +08:00
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
[mips] Range check simm4. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16811 llvm-svn: 263220
2016-03-11 19:37:50 +08:00
addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
[mips][ias] Range check uimm10 operands Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 llvm-svn: 255112
2015-12-09 21:48:05 +08:00
break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
[mips] Range check simm9 and fix a bug this revealed. Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
2016-03-31 21:15:23 +08:00
cachee 0, -513($7) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
cachee 0, 512($7) # CHECK: :[[@LINE]]:13: error: expected memory with 9-bit signed offset
[mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
2015-12-21 21:08:58 +08:00
# FIXME: Check '0 < pos + size <= 32' constraint on ext
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
2015-12-21 21:08:58 +08:00
ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
[mips] Range check simm9 and fix a bug this revealed. Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
2016-03-31 21:15:23 +08:00
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 0, -1 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ins $2, $3, 0, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
jraddiusp -1 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp -4 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
[mips] Range check simm7. Summary: Also renamed li_simm7 to li16_imm since it's not a simm7 and has an unusual encoding (it's a uimm7 except that 0x7f represents -1). Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18145 llvm-svn: 264056
2016-03-22 22:40:00 +08:00
li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
[mips] Range check simm9 and fix a bug this revealed. Summary: The bug was that microMIPS's [ls]w[lr]e instructions claimed to support a 12-bit offset when it is only 9-bit. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18434 llvm-svn: 265010
2016-03-31 21:15:23 +08:00
prefe 0, -513($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
prefe 0, 512($7) # CHECK: :[[@LINE]]:12: error: expected memory with 9-bit signed offset
[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
2016-05-04 20:02:12 +08:00
rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions Differential Revision: http://reviews.llvm.org/D19857 llvm-svn: 268491
2016-05-04 20:02:12 +08:00
rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-27 00:35:41 +08:00
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
[mips] Trivial corrections to range checked immediates. Summary: SYNC has a 5-bit unsigned immediate. Move MIPS16-specific pcrel16 operand to Mips16 files. Reviewers: vkalintiris Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D18755 llvm-svn: 265947
2016-04-11 23:20:40 +08:00
sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
swe $2, -513($gp) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
swe $2, 512($gp) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
swe $33, 8($gp) # CHECK: :[[@LINE]]:7: error: invalid register number
swe $2, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions Differential Revision: http://reviews.llvm.org/D17989 llvm-svn: 267693
2016-04-27 19:02:23 +08:00
sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
lle $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lle $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lwe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
lwe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
lwe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
lwe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
sbe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
sbe $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
sce $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
she $4, 8($33) # CHECK: :[[@LINE]]:13: error: invalid register number
[mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructions Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
2016-04-29 16:36:54 +08:00
she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
[mips] Accept 32-bit offsets for lh and lhu commands This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
2018-05-11 00:01:18 +08:00
lh $2, -2147483649($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
lh $2, 2147483648($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
2016-05-18 14:54:59 +08:00
lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
[mips] Accept 32-bit offsets for lh and lhu commands This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
2018-05-11 00:01:18 +08:00
lhu $4, -2147483649($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
lhu $4, 2147483648($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 32-bit signed offset
[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
2016-05-18 14:54:59 +08:00
lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
[mips][microMIPS] Implement LWP and SWP instructions Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
2016-05-09 16:07:28 +08:00
lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
# FIXME: This ought to point at the $34 but memory is treated as one operand.
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
[mips][microMIPS] Implement LWP and SWP instructions Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
2016-05-09 16:07:28 +08:00
lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register number
[mips][microMIPS] Implement LWP and SWP instructions Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
2016-05-09 16:07:28 +08:00
swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
[mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
2016-06-15 15:46:24 +08:00
andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid register number
[mips] Fix microMIPS loads and stores. Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
2018-04-30 17:44:44 +08:00
lb $4, -2147483649($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
lb $4, 2147483648($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lb $4, 8($32) # CHECK: :[[@LINE]]:12: error: invalid register number
lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid register number
[mips] Fix microMIPS loads and stores. Previously these instructions were unselectable and instead were generated through the instruction mapping tables. Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46055 llvm-svn: 331165
2018-04-30 17:44:44 +08:00
lbu $4, -2147483649($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
lbu $4, 2147483648($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
[mips] Show an error if register number is out of range Current code does not check that a register number is in the 0-31 range. Sometimes the parser checks that later for some kinds of instructions, but that leads to unclear / incorrect error messages like that: % cat test.s .text lb $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux test.s:2:10: error: expected memory with 16-bit signed offset lb $4, 8($32) ^ Sometimes the parser just crashes: % cat test.s .text lw $4, 8($32) % llvm-mc test.s -triple=mips64-unknown-linux This patch resolves the problem by checking that register number after '$' sign is in the 0-31 range. If the number is out of the range the parser shows the `invalid register number` error, but treats invalid register number as a normal one to continue parsing and catch other possible errors. Differential Revision: https://reviews.llvm.org/D45919 llvm-svn: 330732
2018-04-25 00:14:00 +08:00
lbu $4, 8($32) # CHECK: :[[@LINE]]:13: error: invalid register number