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llvm-project/llvm/test/MC/RISCV/rv32dc-valid.s

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[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases -show-encoding \
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \
[RISCV] Support llvm-objdump -M no-aliases and -M numeric Summary: Now that llvm-objdump allows target-specific options, we match the `no-aliases` and `numeric` options for RISC-V, as supported by GNU objdump. This is done by overriding the variables used for the command-line options, so that the command-line options are still supported. This patch updates all tests using `llvm-objdump -riscv-no-aliases` to use `llvm-objdump -M no-aliases`. Reviewers: luismarques, asb Reviewed By: luismarques, asb Subscribers: pzheng, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66139 llvm-svn: 371534
2019-09-11 00:24:03 +08:00
# RUN: | llvm-objdump -mattr=+c,+d -M no-aliases -d -r - \
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
#
# RUN: not llvm-mc -triple riscv32 -mattr=+c \
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)
# CHECK-ASM: encoding: [0x7e,0x34]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fldsp fs0, 504(sp)
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp)
# CHECK-ASM: encoding: [0xc6,0xbf]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fsdsp fa7, 504(sp)
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5)
# CHECK-ASM: encoding: [0xf4,0x3f]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fld fa3, 248(a5)
[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands Standardise on check lines: * CHECK-ASM * CHECK-OBJ * CHECK-ASM-AND-OBJ This allows for the addition of tests involving symbol operands, which will not result in identical instructions in both assembly and disassembled object output. This commit doesn't exploit this reworking to increase test coverage of symbol operands - that will come in a future patch. llvm-svn: 341546
2018-09-06 21:41:04 +08:00
# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1)
# CHECK-ASM: encoding: [0xf0,0xbd]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fsd fa2, 248(a1)