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llvm-project/llvm/test/MC/AArch64/directive-cpu-err.s

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AArch64: diagnose unrecognized features in .cpu directive. We were silently ignoring any features we couldn't match up, which led to errors in an inline asm block missing the conventional "\n\t". llvm-svn: 303108
2017-05-16 03:42:15 +08:00
// RUN: not llvm-mc -triple aarch64-linux-gnu %s 2> %t > /dev/null
// RUN: FileCheck %s < %t
.cpu invalid
// CHECK: error: unknown CPU name
.cpu generic+wibble+nowobble
// CHECK: :[[@LINE-1]]:18: error: unsupported architectural extension
// CHECK: :[[@LINE-2]]:25: error: unsupported architectural extension
[AArch64] Tighten up directives tests Move expected-fail cases from directive-cpu.s to directive-cpu-err.s. This allows us to remove the 'not' from the llvm-mc invocation in directive-cpu.s so that this test will fail in unexpected error cases. It also means that we are not relying on all stderr coming before any stdout, which seems fragile. Also make use of CHECK-NEXT to ensure that multiline error messages really are occuring together. And add a test to verify that .cpu with an arch version as extension is rejected. Differential Revision: https://reviews.llvm.org/D47873 llvm-svn: 335586
2018-06-26 17:49:31 +08:00
.cpu generic+nofp
fminnm d0, d0, d1
// CHECK: error: instruction requires: fp-armv8
// CHECK-NEXT: fminnm d0, d0, d1
// CHECK-NEXT: ^
.cpu generic+nosimd
addp v0.4s, v0.4s, v0.4s
// CHECK: error: instruction requires: neon
// CHECK-NEXT: addp v0.4s, v0.4s, v0.4s
// CHECK-NEXT: ^
.cpu generic+nocrc
crc32cx w0, w1, x3
// CHECK: error: instruction requires: crc
// CHECK-NEXT: crc32cx w0, w1, x3
// CHECK-NEXT: ^
.cpu generic+nocrypto+crc
aesd v0.16b, v2.16b
[AArch64] Armv8.2-A: add the crypto extensions This adds MC support for the crypto instructions that were made optional extensions in Armv8.2-A (AArch64 only). Differential Revision: https://reviews.llvm.org/D49370 llvm-svn: 338010
2018-07-26 15:13:59 +08:00
// CHECK: error: instruction requires: aes
[AArch64] Tighten up directives tests Move expected-fail cases from directive-cpu.s to directive-cpu-err.s. This allows us to remove the 'not' from the llvm-mc invocation in directive-cpu.s so that this test will fail in unexpected error cases. It also means that we are not relying on all stderr coming before any stdout, which seems fragile. Also make use of CHECK-NEXT to ensure that multiline error messages really are occuring together. And add a test to verify that .cpu with an arch version as extension is rejected. Differential Revision: https://reviews.llvm.org/D47873 llvm-svn: 335586
2018-06-26 17:49:31 +08:00
// CHECK-NEXT: aesd v0.16b, v2.16b
// CHECK-NEXT: ^
.cpu generic+nolse
casa w5, w7, [x20]
// CHECK: error: instruction requires: lse
// CHECK-NEXT: casa w5, w7, [x20]
// CHECK-NEXT: ^
.cpu generic+v8.1-a
// CHECK: error: unsupported architectural extension
// CHECK-NEXT: .cpu generic+v8.1-a
// CHECK-NEXT: ^
[AArch64] Armv8.2-A: add the crypto extensions This adds MC support for the crypto instructions that were made optional extensions in Armv8.2-A (AArch64 only). Differential Revision: https://reviews.llvm.org/D49370 llvm-svn: 338010
2018-07-26 15:13:59 +08:00
.cpu generic+noaes
aese v0.16b, v1.16b
// CHECK: error: instruction requires: aes
// CHECK-NEXT: aese v0.16b, v1.16b
// CHECK-NEXT: ^
.cpu generic+nosha2
sha1h s0, s1
// CHECK: error: instruction requires: sha2
// CHECK-NEXT: sha1h s0, s1
// CHECK-NEXT: ^
.cpu generic+nosha3
sha512h q0, q1, v2.2d
// CHECK: error: instruction requires: sha3
// CHECK-NEXT: sha512h q0, q1, v2.2d
// CHECK-NEXT: ^
.cpu generic+nosm4
sm4e v2.4s, v15.4s
// CHECK: error: instruction requires: sm4
// CHECK-NEXT: sm4e v2.4s, v15.4s
// CHECK-NEXT: ^