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llvm-project/llvm/test/MC/AArch64/darwin-reloc-addsubimm.s

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[AArch64] Fix encoding for lsl #12 in add/sub immediates Whenever an add/sub immediate needs a fixup, we set that immediate field to zero, which is correct, but we also set the shift bits to zero, which is not true for instructions that use lsl #12. This patch makes sure that if lsl #12 was used, it will appear in the encoding of the instruction. Differential Revision: https://reviews.llvm.org/D23930 llvm-svn: 281898
2016-09-19 19:10:18 +08:00
// RUN: llvm-mc -triple=aarch64-darwin -filetype=obj %s -o - | \
// RUN: llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
// OBJ-LABEL: Disassembly of section __TEXT,__text:
add x2, x3, _data@pageoff
// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12 _data
add x2, x3, #_data@pageoff, lsl #12
// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12 _data