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llvm-project/llvm/test/CodeGen/X86/setcc.ll

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[x86] regenerate checks; NFC llvm-svn: 296628
2017-03-01 22:41:57 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Propagate zest through logical shift. llvm-svn: 91378
2009-12-15 08:41:36 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. llvm-svn: 91381
2009-12-15 08:53:42 +08:00
; rdar://7329206
; Use sbb x, x to materialize carry bit in a GPR. The value is either
; all 1's or all 0's.
Propagate zest through logical shift. llvm-svn: 91378
2009-12-15 08:41:36 +08:00
define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: t1:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl $26, %edi
; CHECK-NEXT: seta %al
; CHECK-NEXT: shll $5, %eax
; CHECK-NEXT: retq
%t0 = icmp ugt i16 %x, 26
%if = select i1 %t0, i16 32, i16 0
ret i16 %if
Propagate zest through logical shift. llvm-svn: 91378
2009-12-15 08:41:36 +08:00
}
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. llvm-svn: 91381
2009-12-15 08:53:42 +08:00
define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: t2:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
; CHECK-NEXT: xorl %eax, %eax
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK-NEXT: cmpl $26, %edi
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
; CHECK-NEXT: setb %al
; CHECK-NEXT: shll $5, %eax
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK-NEXT: retq
%t0 = icmp ult i16 %x, 26
%if = select i1 %t0, i16 32, i16 0
ret i16 %if
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. llvm-svn: 91381
2009-12-15 08:53:42 +08:00
}
define i64 @t3(i64 %x) nounwind readnone ssp {
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: t3:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
; CHECK-NEXT: xorl %eax, %eax
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK-NEXT: cmpq $18, %rdi
[x86] don't blindly transform SETB into SBB I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
2017-03-13 02:28:48 +08:00
; CHECK-NEXT: setb %al
; CHECK-NEXT: shlq $6, %rax
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK-NEXT: retq
%t0 = icmp ult i64 %x, 18
%if = select i1 %t0, i64 64, i64 0
ret i64 %if
Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. llvm-svn: 91381
2009-12-15 08:53:42 +08:00
}
[X86] Fix the (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) fold We didn't check for the necessary preconditions before folding a mask/shift into a single mask. This fixes PR24516. llvm-svn: 245544
2015-08-20 17:00:56 +08:00
@v4 = common global i32 0, align 4
define i32 @t4(i32 %a) {
; CHECK-LABEL: t4:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
; CHECK-NEXT: movq _v4@{{.*}}(%rip), %rax
; CHECK-NEXT: cmpl $1, (%rax)
[DAGCombiner] fold binops with constant into select-of-constants This is part of the ongoing attempt to improve select codegen for all targets and select canonicalization in IR (see D24480 for more background). The transform is a subset of what is done in InstCombine's FoldOpIntoSelect(). I first noticed a regression in the x86 avx512-insert-extract.ll tests with a patch that hopes to convert more selects to basic math ops. This appears to be a general missing DAG transform though, so I added tests for all standard binops in rL296621 (PowerPC was chosen semi-randomly; it has scripted FileCheck support, but so do ARM and x86). The poor output for "sel_constants_shl_constant" is tracked with: https://bugs.llvm.org/show_bug.cgi?id=32105 Differential Revision: https://reviews.llvm.org/D30502 llvm-svn: 296699
2017-03-02 06:51:31 +08:00
; CHECK-NEXT: movw $1, %ax
; CHECK-NEXT: adcw $0, %ax
; CHECK-NEXT: shll $16, %eax
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK-NEXT: retq
%t0 = load i32, i32* @v4, align 4
%not.tobool = icmp eq i32 %t0, 0
[X86] Fix the (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) fold We didn't check for the necessary preconditions before folding a mask/shift into a single mask. This fixes PR24516. llvm-svn: 245544
2015-08-20 17:00:56 +08:00
%conv.i = sext i1 %not.tobool to i16
%call.lobit = lshr i16 %conv.i, 15
%add.i.1 = add nuw nsw i16 %call.lobit, 1
%conv4.2 = zext i16 %add.i.1 to i32
%add = shl nuw nsw i32 %conv4.2, 16
ret i32 %add
}
[X86] Use the right type when folding xor (truncate (shift)) -> setcc The result type of setcc is dependent on whether or not AVX512 is present. We had an X86-specific DAG-combine which assumed that the result type should be i8 when it could be i1. This meant that we would generate illegal setccs which LowerSETCC did not like. Instead, use an appropriate type and zero extend to i8. Also, there were some scenarios where the fold should have fired but didn't because we were overly cautious about the types. This meant that we generated: shrl $31, %edi andl $1, %edi kmovw %edi, %k0 kxnorw %k0, %k0, %k1 kshiftrw $15, %k1, %k1 kxorw %k1, %k0, %k0 kmovw %k0, %eax instead of: testl %edi, %edi setns %al This fixes PR27638. llvm-svn: 268609
2016-05-05 14:00:56 +08:00
define i8 @t5(i32 %a) #0 {
; CHECK-LABEL: t5:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: setns %al
; CHECK-NEXT: retq
[X86] Use the right type when folding xor (truncate (shift)) -> setcc The result type of setcc is dependent on whether or not AVX512 is present. We had an X86-specific DAG-combine which assumed that the result type should be i8 when it could be i1. This meant that we would generate illegal setccs which LowerSETCC did not like. Instead, use an appropriate type and zero extend to i8. Also, there were some scenarios where the fold should have fired but didn't because we were overly cautious about the types. This meant that we generated: shrl $31, %edi andl $1, %edi kmovw %edi, %k0 kxnorw %k0, %k0, %k1 kshiftrw $15, %k1, %k1 kxorw %k1, %k0, %k0 kmovw %k0, %eax instead of: testl %edi, %edi setns %al This fixes PR27638. llvm-svn: 268609
2016-05-05 14:00:56 +08:00
%.lobit = lshr i32 %a, 31
%trunc = trunc i32 %.lobit to i8
%.not = xor i8 %trunc, 1
ret i8 %.not
}
define zeroext i1 @t6(i32 %a) #0 {
; CHECK-LABEL: t6:
[x86] regenerate checks llvm-svn: 281531
2016-09-15 04:21:28 +08:00
; CHECK: ## BB#0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: setns %al
; CHECK-NEXT: retq
[X86] Use the right type when folding xor (truncate (shift)) -> setcc The result type of setcc is dependent on whether or not AVX512 is present. We had an X86-specific DAG-combine which assumed that the result type should be i8 when it could be i1. This meant that we would generate illegal setccs which LowerSETCC did not like. Instead, use an appropriate type and zero extend to i8. Also, there were some scenarios where the fold should have fired but didn't because we were overly cautious about the types. This meant that we generated: shrl $31, %edi andl $1, %edi kmovw %edi, %k0 kxnorw %k0, %k0, %k1 kshiftrw $15, %k1, %k1 kxorw %k1, %k0, %k0 kmovw %k0, %eax instead of: testl %edi, %edi setns %al This fixes PR27638. llvm-svn: 268609
2016-05-05 14:00:56 +08:00
%.lobit = lshr i32 %a, 31
%trunc = trunc i32 %.lobit to i1
%.not = xor i1 %trunc, 1
ret i1 %.not
}
attributes #0 = { "target-cpu"="skylake-avx512" }